From codesign-request@ifi.unizh.ch Sun Jan 4 01:06:11 1998 Return-Path: Received: from clavin.cs.tamu.edu by josef.ifi.unizh.ch with SMTP (PP) id <26804-0@josef.ifi.unizh.ch>; Sun, 4 Jan 1998 01:05:56 +0100 Received: from neuron.cs.tamu.edu (233@neuron [128.194.133.1]) by cs.tamu.edu (8.8.8/8.8.8) with ESMTP id SAA19739 for ; Sat, 3 Jan 1998 18:03:21 -0600 (CST) From: Fabrizio Lombardi Subject: IEEE Int. Workshop On Embedded Fault-Tolerant Systems Received: (from lombardi@localhost) by neuron.cs.tamu.edu (8.8.8/8.8.8) id SAA10142 for codesign@ifi.unizh.ch; Sat, 3 Jan 1998 18:07:27 -0600 (CST) Date: Sat, 3 Jan 1998 18:07:27 -0600 (CST) Message-Id: <199801040007.SAA10142@neuron.cs.tamu.edu> To: codesign@ifi.unizh.ch Status: RO X-Status: X-Keywords: X-UID: 1 Call for Participation " IEEE International Workshop On Embedded Fault-Tolerant Systems" May 22-23, 1998 Boston University, Boston, MA Sponsored by IEEE Computer Society Technical Committee on Fault-Tolerant Computing In cooperation with IFIP Working group 10.4, Boston University, Boston, MA Objectives The goal of this workshop is to provide a forum for researchers to present and exchange research results and advances in the field of Embedded Fault-Tolerant Systems, both hardware and software, and their interactions. Topics Topics of interest to the workshop include (but are not limited to): Fault-tolerant hardware/software co-design of embedded computing systems; Verification and validation of complex embedded computing systems; Hardware/software fault-tolerance tradeoffs; Chip-level design of embedded fault-tolerant systems; Embedded fault-tolerant systems in the aerospace, automotive and telecommunications industries; Applications of embedded fault-tolerant design to medical diagnostics equipment and financial-banking transactions systems; Formal methods and tools for verification and validation of embedded fault-tolerant systems; Case studies. Selected papers will be published in a special issue of The Journal of Supercomputing. An approval for a special issue of IEEE Micro is pending. Participation Send five copies of abstract not exceeding 1000 words to the Program Chair by March 10, 1998. All panel proposals should be received no later than March 10, 1998. For additional information concerning the workshop, please contact the General Chairs. Hotel accommodations will be reserved for the participants of the workshop at the Tremont House Hotel, in downtown Boston. General Chairs Dr. D. Avresky Boston University Dept. of ECE Boston, MA 02215 Phone: (617)- 353-9850 Fax:(617)- 353-6440 Email: avresky@bu.edu Dr. Barry W. Johnson University of Virginia Dept. of El. Eng. Charlottesville, VA 22903 Phone:(804) 924-7623 Fax: (804) 924-8818 Email: bwj@virginia.edu Program Chair Dr. F. Lombardi Texas A\&M University Dept. of Comp. Science College Station, TX 77843 Phone: (409)- 845-5464 Fax: (409)- 847-8578 Email: lombardi@cs.tamu.edu Finance and Registration Chair Dr. V. Strumpen Lab. for Computer Science, MIT 545 Technology Square Cambridge, MA 02139 Phone: (617) 253-1531 FAX: (617) 253-0415 Email: strumpen@theory.lcs.mit.edu Program Committee J. Bruck (USA) R. Harper (USA) H. Verheyen (USA) R. Riter (USA) B. Ciciani (Italy) J. Hlavicka (Czech Rep.)A. Nordsieck, (USA) D. Kaeli (USA) F. Cristian (USA) M. Karpovski (USA) I. Koren (USA) W. Sanders (USA) M. Dal Cin (Germany)J. Lala (USA) Y. Koga (Japan) D. Sieworek(USA) K. Fuchs (USA) H. Levendel (USA) B. Ossfeldt (Sweden)R. Swarz (USA) P. Green (USA) E. Maehle (Germany) D. Powel (France) R. Vidale(USA) J. Hayes (USA) D. Moldovan (USA) A. Pruscino (USA) L. Young (USA) Deadlines Abstract Submission: March 10th, 1998; Notification of Acceptance: April 20th, 1998. From codesign-request@ifi.unizh.ch Mon Jan 26 09:53:41 1998 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <19948-0@josef.ifi.unizh.ch>; Mon, 26 Jan 1998 09:53:18 +0100 Return-Path: X-Received: from rasips1.rasip.fer.hr by josef.ifi.unizh.ch with SMTP (PP) id <01583-0@josef.ifi.unizh.ch>; Wed, 21 Jan 1998 19:41:26 +0100 X-Received: (from wdta@localhost) by rasips1.rasip.fer.hr (8.8.5/8.8.5) id TAA10862 for pilz@ifi.unizh.ch; Wed, 21 Jan 1998 19:39:28 +0100 (MET) From: WDTA Message-Id: <199801211839.TAA10862@rasips1.rasip.fer.hr> Subject: WDTA To: pilz@ifi.unizh.ch Date: Wed, 21 Jan 1998 19:39:27 +0100 (MET) X-Mailer: ELM [version 2.4ME+ PL31 (25)] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit ReSent-Date: Mon, 26 Jan 1998 09:52:01 +0100 (MET) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Message-ID: Status: O X-Status: X-Keywords: X-UID: 2 FPGA designers .. please read .. sorry if you have received this already ------ cut here --------- please feel free to distribute ------------- Call for Papers ABSTRACT DEADLINE MARCH 15th ------------------------------------------------ | 1998 Workshop on Design, Test and Applications | ------------------------------------------------ Dubrovnik President Hotel, Dubrovnik, Croatia, June 8-10, 1998. Aim of the 1998 Workshop on Design, Test and Applications (WDTA'98) is to present novel industrial and academic research and development achievements, trends and forecasts in the area of electronic design, test and wide variety of applications. WDTA will also be a place to share ideas between participants, learn most recent developments and present commercial solutions. ---------- | SPONSORS | ---------- - IEEE Region 8 - IEEE Croatia Section - IEEE Computer Society Croatia Section - Expected: IEEE Computer Society TTTC - Faculty of Electrical Eng. and Computing, University of Zagreb - Croatian Ministry of Science and Technology TOPICS OF INTEREST: ------------------- Abstracts are being solicited for topics of interest that include, but are not limited to: * Design of digital, mixed-signal and analogue circuits, subsystems and systems * System design methodologies * Device and system architectures, design trade-offs * High level synthesis, system specification languages and synthesis tools * VLSI designs and VLSI systems * PLD/FPGA chip architectures, PLD/FPGA-based systems and PLD/FPGA CAD algorithms for synthesis, partitioning, placement and routing * Hard/Soft core designs * Low power design * High performance design * Physical design issues * Design reuse HW/SW codesign * Designs and applications for multimedia * Telecom and consumer electronics designs * Embedded and real-time systems * Reconfigurable systems * MEMS design * IP issues * Design-for-testability * Built-in self-test * Mixed signal testing * Fault simulation * Simulation techniques * High-level test generation * IDDQ * MEMS testing * Advanced test and measurement equipment * Novel SW/HW algorithms and applications from different areas * SW/HW development tools and development environments * Design process management * Novel computer and network equipment and system solutions * Network based computing * Large computer/network system organizations * Industrial applications * Design and education * Forecasting the future SUBMISSION REQUIREMENTS: ------------------------ Abstracts of 500-1000 words must be electronically submitted: a) via submission form on WDTA WEB page (www.rasip.fer.hr/wdta/submit.html) or b) by email (wdta@rasip.fer.hr) following the instructions listed below. Email submissions (b) must contain: 1. Author(s) name(s) and title(s), 2. Affiliation(s), 3. Full correspondence address, phone and fax number and email address of principal author with the statement: "If paper is accepted at least one of the authors will register and present the paper at the Workshop" (1-3. all in ASCII format) 4. Abstract (text and figures in ASCII, PDF or Postscript format). IMPORTANT DATES: ---------------- Abstract submission deadline March 15, 1998. Notification of acceptance April 10, 1998. Advanced registration deadline May 15, 1998. Workshop June, 8-10, 1998. WDTA WEB page: http://www.rasip.fer.hr/wdta USA mirror site: http://vcapp.csee.usf.edu/~wdta E-mail: wdta@rasip.fer.hr OFFICIAL LANGUAGE ----------------- Official language of the Workshop will be English. LOCATION & TRAVEL ----------------- "Those who seek paradise on Earth should come to Dubrovnik and see Dubrovnik" (Bernard Shaw). Dubrovnik will be just the way you are yourself when you come to it. And you will leave it the way Dubrovnik is. Unique. Perfect. Average temperature of 21.9 degrees Celsius (72 F) and see warm enough for swimming (avg. temp 20.9C=69F) makes June best time to visit Dubrovnik and see it's cultural heritage. More details on Dubrovnik, tourist and travel information can be found on WDTA WEB page. UNIVERSITY BOOTH ---------------- University booth will be organized where student research results can be presented. For more details please contact General Chair. REGISTRATION ------------ Registration details can be found on WDTA WEB page or can be requested by sending email to wdta@rasip.fer.hr. Limited number of rooms at reduced rates have been reserved for WDTA participants and therefore advanced registration is encouraged. Inexpensive student accommodation will also be available. COMMERCIAL PRESENTATIONS & EXHIBITION ------------------------------------- Commercial Exhibition will be organized during the Workshop, focussing on electronic components (such as PLDs/FPGAs), design tools, test and measurement equipment and computer and networking equipment. Please see if your company or company you do bussiness with would be interested in presenting the products. Our intention is to focus on Central and Eastern Europe markets. For further information please contact General Chair. General Chair: -------------- Mario Kovac University of Zagreb FER, Unska 3 10000 Zagreb, Croatia tel: +385 1 6129-759 fax: +385 1 6129-809 email: mario.kovac@fer.hr Program Committee: ------------------ - Athan Stephen P., - Bolsens Ivo, Uni. of South Florida, USA IMEC, Belgium - Brown Stephen D., - Courtois Bernard, University of Toronto, Canada TIMA CMP, France - Dutt Nikil, - Gajski Daniel D., Uni. of California Irvine, USA Uni. of California Irvine, USA - Gregoretti Francesco, - Hermida Roman, Ploitecnico di Torino, Italy Uni. Complutense, Spain - Huss Sorin Alexander, - Krajcar Slavko, Darmstadt Uni., Germany University of Zagreb, Croatia - Kurdahi Fadi, - Novak Franc, Uni. of California Irvine, USA Institut Jozef Stefan,Slovenia - Olbrich Thomas, - Rammig Franz Josef, AMS International AG, Austria Uni. Paderborn/HNI, Germany - Ranganathan N., - Rencz Marta, Uni. of South Florida, USA MicReD Ltd, Hungary - Ribari_ Slobodan, - Rohleder Rhondalee, University of Zagreb, Croatia QuickLogic Corporation, USA - Stefanakos Elias K., - Ubar Raimund, Uni. of South Florida, ISA Tallinn Technical Uni.,Estonia - Videira Idalina J.M., - Vranesic Zvonko G., IST/INESC, Portugal University of Toronto, Canada - Wehn Norbert, - Wickerhauser Mladen Victor, Uni. Kaiserslautern, Germany Washington Uni. St.Louis,USA - Zagar Mario, - Zajc Baldomir, University of Zagreb, Croatia Uni. of Ljubljana, Slovenia - Zorian Yervant, LogicVision, Inc., USA ------------------------------ | ABSTRACT DEADLINE MARCH 15th | ------------------------------ From codesign-request@ifi.unizh.ch Mon Feb 2 20:16:04 1998 Return-Path: Received: from pol88b.polito.it by josef.ifi.unizh.ch with SMTP (PP) id <16021-0@josef.ifi.unizh.ch>; Mon, 2 Feb 1998 20:15:48 +0100 Received: from gandalf. (gandalf.polito.it) by polito.it (PMDF V4.2-15 #3020) id <01IT47XFHJXCQOHFNY@polito.it>; Mon, 2 Feb 1998 20:15:50 GMT+1 Received: from localhost by gandalf. (SMI-8.6/SMI-SVR4) id UAA06533; Mon, 2 Feb 1998 20:14:47 +0100 Date: Mon, 02 Feb 1998 20:14:47 +0100 From: Luciano Lavagno Subject: Job opportunity at Politecnico di Torino To: esterel-users@sophia.inria.fr, codesign@ifi.unizh.ch, delen@eln1.polito.it, polis-users@ic.eecs.berkeley.edu Cc: lavagno@gandalf.polito.it Message-id: <199802021914.UAA06533@gandalf.> X-Envelope-to: codesign@ifi.unizh.ch MIME-version: 1.0 X-Mailer: exmh version 1.6.9 8/22/96 Content-type: text/plain; charset=us-ascii Content-transfer-encoding: 7BIT Status: RO X-Status: X-Keywords: X-UID: 3 Research Associate position in CAD for embedded system design The Department of Electronics, Politecnico di Torino, Italy, invites applications for a Research Associate-level position in the area of embedded system design. The appointment can begin as soon as March 15, 1998, and last until March 31, 2000. The research focus is on scheduling, allocation and performance estimation of mixed hardware/software implementations of embedded systems. The gross salary level is between 24000 and 48000 ECUs per year (net between 16000 and 30000 ECUs per year), depending on qualifications and experience. For full consideration, applications should be submitted by February 15, 1998. However, applications will be accepted until the position is filled. Requirements: - MS or PhD (or equivalent, e.g., Italian "Laurea" is OK) in Electrical Engineering or Computer Science - Good knowledge about embedded systems and modern micro-processor architectural features (pipelining, superscalarity, caching, ...). Familiarity with Discrete Event simulation concepts is also appreciated. - Good experience in C/C++ programming (UNIX and/or Windows NT) - Good understanding of written and spoken English Applicants should send as soon as possible a letter of intent, resume and (optionally) names of references BY E-MAIL to prof. Francesco Gregoretti (gregor@polimage.polito.it). For additional information about the research group and the University, see http://polimage.polito.it/groups/hwswgroup.html and http://www.polito.it Best regards, Luciano Lavagno -- Luciano Lavagno +39-11-564-4150 (fax 4099) lavagno@polito.it Dip. di Elettronica, Politecnico, C. Duca degli Abruzzi 24, 10129 Torino, ITALY http://www-cad.eecs.berkeley.edu/~luciano/ http://polimage.polito.it/~lavagno From codesign-request@ifi.unizh.ch Thu Feb 5 19:18:11 1998 Return-Path: Received: from imag.imag.fr by josef.ifi.unizh.ch with SMTP (PP) id <09027-0@josef.ifi.unizh.ch>; Thu, 5 Feb 1998 19:18:07 +0100 Received: from verdon.imag.fr (verdon.imag.fr [147.171.129.20]) by imag.imag.fr (8.8.5/8.8.5) with ESMTP id TAA02202; Thu, 5 Feb 1998 19:18:23 +0100 (MET) Received: (from jerraya@localhost) by verdon.imag.fr (8.6.11/8.6.9) id TAA17880; Thu, 5 Feb 1998 19:18:29 +0100 Date: Thu, 5 Feb 1998 19:18:29 +0100 From: Ahmed Amine Jerraya Message-Id: <199802051818.TAA17880@verdon.imag.fr> X-Mailer: Mail User's Shell (7.2.5 10/14/92) To: isss-people@ics.UCI.EDU, codesign@ifi.unizh.ch Subject: CODES/CASHE'98: Advance Program Status: RO X-Status: X-Keywords: X-UID: 4 ADVANCE PROGRAM ======= ======= 6th International Workshop on Hardware/Software Co-Design Codes/CASHE '98 Seattle, Washington - 15-18 March 1998 This year we received 66 papers of which 24 were selected by the technical program committee to appear in the proceeidngs. An additional 15 papers were selected to be presented in the poster sessions. The advance program and the registration form for Codes'98 are now on the regular workshop web pages: http://www.cs.washington.edu/research/codes98/ http://polimage.polito.it/codes98/ Advance Registration deadline: Febryary 28th 1998 See you in Seattle. Ahmed ------------------------------------------------------------------------- Codes/CASHE '98 Advance Program Sunday, March 15 19:00-22:00 - Reception Monday, March 16 07:45-08:45 - Registration & Breakfast Buffet 08:45-09:00 - Opening Session Welcome from chairs Organization of program 09:00-10:20 - Session 1: System Level Modeling Papers: - An Analysis-based Approach to Composition of Distributed Embbeded Systems P. Chou and G. Borriello - Combining Multiple Models of Computation for Scheduling and Allocation D. Ziegenbein, R. Ernst, K. Richter, J. Teich and L. Tiele - Modeling Reactive Systems in Java C. Passerone, R. Passerone, C. Sansoe, J. Martin, A.Sangiovanni-Vincentelli and R. McGeer Posters: - A Unified Component Modeling Approach for Performance Estimation in Hardware/Software Codesign J. Grode and J. Madsen 10:20-10:40 - Break 10:40-12:00 - Session 2: Partitioning Papers: - Energy-Conscious HW/SW-Paritioning of Embedded Systems: A Case Study on an MPEG-2 Encoder J. Henkel and Y. Li - Hipart: A New Hierarchical Semi-Interactive HW/SW Partitioning Approach with Fast Debugging for Real-Time Embedded Systems T. Hollstein, J. Becker, A. Kirschbaum, M. Glesner - Towards Interprocess Communication and Interface Synthesis for a Heterogeneous Real-Time Rapid Prototyping Environment F. Fischer, A. Muth, Georg F=E4rber Posters: - A Grouping Partitioning Technique with Automatic Criterion Selection for the Codesign Process J.A. Maestro and D. Mozos 12:00-13:30 - Lunch 13:30-14:50 - Session 3: Communication and Interface Synthesis Papers: - Domain-Specific Interface Generation from Dataflow Specifications M. Eisenring and J. Teich - Communication Synthesis and HW/SW Integration for Embedded System Design G. Gognat, M. Auguin, L. Bianco, A. Pegatoquet - Communication Estimation for Hardware/Software Codesign P. Voigt Knudsen and J. Madsen Posters: - Realizability and Synthesis of Interface Controllers A. El-Aboudi, E.M. Aboulhamid, E. Cerny 14:50-15:05 - Break 15:05-17:05 - Invited Talks - FlexWare: A Flexible Hardware/Software Development Encironment and its Application to Consumer Multimedia Product Designs Dr. Pierre. Paulin, SGS-Thomson Microelectronics, Grenoble, France - Smartbadges: A Wearable Computer and Communication System Prof. Dr. Gerald Q. Maguire Jr., Royal Institute of Technology, Stockholm, Sweden Dr. Mark T. Smith, Hewlett-Packard Research Laboratories, Paolo Alto, California, USA Dr. H.W. Peter Beadle, University of Wollongong, Wollongong, Australia Tuesday, March 17 08:00-09:00 - Breakfast Buffet 09:00-10:20 - Session 4: Cosimulation Papers: - Software Timing Analysis Using HW/SW Cosimulation and Instruction Set Simulator J. Liu, M. Lajolo, A. Sangiovanni-Vincentelli - Optimistic Distributed Timed Cosimulation Based on Thread Simulation Model S. Yoo and K. Choi - Fast Dynamic Analysis of Complex HW/SW Systems based on Abstract State Machine Models G. Del Castillo and W. Hardt Posters: - A High Level Object Cosimulation Technique for Real-Time HW/SW Systems O. Pasquier and J.P. Calvez - Integrated System Level Simulation Techniques for the Design of Embedded Systems U. Freund, V. Zerbe, G. Schorcht - Virtual Prototyping, a Case Study in Dataflow Oriented Codesign H. Holten-Lund, M. L=FCtken, J. Madsen, S. Perdersen - Object-Oriented Design of ATM Switch Hardware in a Telecommunication Network Simulation Environment G. Post, A. M=FCller, R. Schoenen 10:20-10:40 - Break 10:40-12:00 - Session 5: Scheduling Papers: - A Path Analysis based Partitioning for Time Constrained Embedded Systems L. Bianco, M. Auguin, G. Gogniat, AL Pegatoquet - Schedulability Analysis of Heterogeneous Systems for Performance Message Sequence Chart F. Slomka, J. Zant, L. Lambert - TGFF: Task Graphs for Free R.P. Dick, D. L. Rhodes, W. Wolf Posters: - Rapid Prototyping of Embedded Systems Running Concurrent Applications with Task-level Dynamics: Hardware Architecture Selection, Mapping, and Real-time Scheduler Selection A. Kalavade and P. Mogh=E9 - Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems P. Eles, K. Kuchcinski, Z. Peng, A. Doboli, P. Pop - An RTOS Simulator with Synchronous Semantics E. M. Sentovich - Quasi-Static Scheduling of Free-Choice Petri Nets M. Sgroi, L. Lavagno, A. Sangiovanni-Vincentelli 12:00-13:30 - Lunch 13:30-14:50 - Session 6: Case Studies Papers: - A Hardware/Software Prototyping Environment for Dynamically Reconfigurable Embedded Systems J. Fleischmann, K. Buchenrieder, R. Kress - Hardware/Software Codesign of an ATM Network Interface Card: a Case Study J.M. Daveau, G. Marchioro, A.A. Jerraya - A Case Study on Modeling Shared Memory Access Effects during Performance Analysis of HW/SW Systems M. Lajolo, A. Raghunathan, S. Dey, L. Lavagno, A.Sangiovanni-Vincentelli Posters: - Hardware-Software Run-Time Systems and Robotics: A Case Study V.J. Mooney III, D. Ruspini, O. Khatib, G. De Micheli - A Case Study in Heterogeneous Implementation of Automotive Real-Time Systems J. Axelsson - Reconfigurable Processing as a Target Architecture for Codesign W. Fornaciari, L. Pozzi, M.G. Sami 14:50-15:05 - Break Group Discussion: 15:05-17:00 18:00-22:00 - Workshop Dinner at the Boeing Museum of flight Wednesday, March 18 08:00-09:00 - Breakfast Buffet 09:00-10:20 - Session 7: System on Chip Papers: - The Construction of a Retargetable Simulator for an Architecture Template B. Kienhuis, E. Deprettere, K. Vissers, P. von der Wolf - HDL Code Restructuring Using Timed Decision Tables J. Li and R. Gupta - Instruction Subsetting: Trading Power for Programmability W.E. Dougherty, D.J. Pursley, D.E. Thomas Posters: - Building an Executing Y-charts for Heterogeneous System Design P. van der Wolf and K. Vissers - An Embedded Software Programming Language for Application Specific Datapath Width Processors A. Inoue, H. Tomiyama, T. Shimizu, H. Kanbara, H. Yasuura 10:20-10:40 - Break 10:40-12:00 - Session 8: System Level Modeling - RECOD: A Retiming Heuristic To Optimize Resource And Memory Utilization in HW/SW Codesigns K.S. Chatha and R. Vemuri - Task Level Memory Hierarchy for Low Power Real-Time Systems Y. Li, W. Wolf, J. Henkel - Memory Size Estimation for Multimedia Applications P. Grun, F. Balasa, N. Dutt 12:00-13:30 - Lunch 13:30-15:00 - Closing Session Five minute statements by attendees Closing remarks -- ------------------- PLEASE NOTE THE CHANGEs IN PHONE AND FAX NUMBERS ------ Ahmed Amine JERRAYA, Ph. D | Office: (+33) 476 574 759 ------ System-Level Synthesis Group | Home : (+33) 476 096 014 ------ TIMA/INPG 46 Ave Felix Viallet | Fax : (+33) 476 473 814 ------ F-38031 Grenoble Cedex FRANCE | E_mail: ahmed.jerraya@imag.fr From codesign-request@ifi.unizh.ch Tue Feb 10 11:53:49 1998 Return-Path: Received: from imag.imag.fr by josef.ifi.unizh.ch with SMTP (PP) id <12518-0@josef.ifi.unizh.ch>; Tue, 10 Feb 1998 11:53:33 +0100 Received: from verdon.imag.fr (verdon.imag.fr [147.171.129.20]) by imag.imag.fr (8.8.5/8.8.5) with ESMTP id LAA24896; Tue, 10 Feb 1998 11:53:47 +0100 (MET) Received: (from jerraya@localhost) by verdon.imag.fr (8.6.11/8.6.9) id LAA05172; Tue, 10 Feb 1998 11:53:52 +0100 Date: Tue, 10 Feb 1998 11:53:52 +0100 From: Ahmed Amine Jerraya Message-Id: <199802101053.LAA05172@verdon.imag.fr> X-Mailer: Mail User's Shell (7.2.5 10/14/92) To: isss-people@ics.UCI.EDU, codesign@ifi.unizh.ch Subject: Advance registration deadline: Codes/CASHE'98 Status: RO X-Status: X-Keywords: X-UID: 5 Dear Collegues, Advance registration and Hotel reservation for Codes/CASHE '98: I would like to bring your attention to the fact that you need to register before 28 February in order to have the special advance registration rate. Please note also that you need to make your hotel reservation before 20 February in order to have the special rate in the Hotel. The advance program and the registration form for Codes'98 are now on the regular workshop web pages: http://www.cs.washington.edu/research/codes98/ http://polimage.polito.it/codes98/ See you in Seattle Ahmed -- ------------------- PLEASE NOTE THE CHANGEs IN PHONE AND FAX NUMBERS ------ Ahmed Amine JERRAYA, Ph. D | Office: (+33) 476 574 759 ------ System-Level Synthesis Group | Home : (+33) 476 096 014 ------ TIMA/INPG 46 Ave Felix Viallet | Fax : (+33) 476 473 814 ------ F-38031 Grenoble Cedex FRANCE | E_mail: ahmed.jerraya@imag.fr From codesign-request@ifi.unizh.ch Tue Feb 10 18:01:07 1998 Return-Path: Received: from igw3.watson.ibm.com by josef.ifi.unizh.ch with SMTP (PP) id <25518-0@josef.ifi.unizh.ch>; Tue, 10 Feb 1998 18:00:39 +0100 Received: from mailhub.watson.ibm.com (mailhub.watson.ibm.com [9.2.250.97]) by igw3.watson.ibm.com (8.8.7/07-11-97) with ESMTP id MAA11926 for ; Tue, 10 Feb 1998 12:00:50 -0500 Received: from chameleon.watson.ibm.com (chameleon.watson.ibm.com [9.2.220.64]) by mailhub.watson.ibm.com (8.8.7/07-14-97) with SMTP id MAA08820 for ; Tue, 10 Feb 1998 12:00:49 -0500 Received: by chameleon.watson.ibm.com (AIX 4.1/UCB 5.64/6/25/96) id AA28652; Tue, 10 Feb 1998 12:00:48 -0500 Date: Tue, 10 Feb 1998 12:00:48 -0500 Message-Id: <9802101700.AA28652@chameleon.watson.ibm.com> From: Leon Stok To: codesign@ifi.unizh.ch Subject: CFP IWLS98 Status: RO X-Status: X-Keywords: X-UID: 6 If you did not write your paper for the IWLS98 yet, you better get started quickly!!!! Only 1.5 weeks to go till the submission deadline for: 1998 IEEE/ACM International Workshop on Logic Synthesis Granlibakken Resort, Lake Tahoe,California June 7-10 , 1998 (this is the week before DAC, to be held in San Fransisco) Call for Participation Submission DEADLINE: Feb 20, 1998 (Papers submitted to IWLS are eligible for submission to ICCAD.) See http://domino.watson.ibm.com/IWLS98/IWLS98.NSF for more information. From codesign-request@ifi.unizh.ch Mon Feb 16 02:00:52 1998 Return-Path: Received: from clavin.cs.tamu.edu by josef.ifi.unizh.ch with SMTP (PP) id <12328-0@josef.ifi.unizh.ch>; Mon, 16 Feb 1998 02:00:43 +0100 Received: from neuron.cs.tamu.edu (233@neuron [128.194.133.1]) by cs.tamu.edu (8.8.8/8.8.8) with ESMTP id SAA03917 for ; Sun, 15 Feb 1998 18:57:58 -0600 (CST) From: Fabrizio Lombardi Received: (from lombardi@localhost) by neuron.cs.tamu.edu (8.8.8/8.8.8) id SAA13106 for codesign@ifi.unizh.ch; Sun, 15 Feb 1998 18:58:03 -0600 (CST) Date: Sun, 15 Feb 1998 18:58:03 -0600 (CST) Message-Id: <199802160058.SAA13106@neuron.cs.tamu.edu> To: codesign@ifi.unizh.ch Subject: 1998 IEEE Int. Workshop Memory Technology, Design, and Testing Status: RO X-Status: X-Keywords: X-UID: 7 1998 IEEE International Workshop on MEMORY Technology, Design, and Testing August 24--25, 1998 CALL FOR PAPERS San Jose, California Sponsored by: IEEE Computer Society, Technical Committee on Test Technology and Technical Committee on VLSI. In cooperation with: IEEE Solid-State Circuit Society. The workshop will include all aspects of memory design, process technologies, and testability related topics. Memory circuit designs, cell structures, fabrication processes, design architectures and related testing and verification methods for SRAM, DRAM, Flash and non-volatile memories, EPROM, EEPROM, embedded memories, logic-enhanced and FIFO memories, 3-D memories, and content addressable memories. Representative topics are: Memory fault modeling and test generation Built-in test and testable designs for memories Concurrent checking and memory fault diagnosis Quality and reliability issues Space applications and radiation hardening issues Memory failure and yield analysis High-speed, innovative designs Fault isolation, reconfiguration and repair Multiported, multibuffered memories Logic-enhanced and programmable memories Application-specific and embedded memories Multimegabit SRAMs and DRAMs CMOS, BiCMOS and bipolar designs for high yield and reliability If you are interested in giving a tutorial please contact the Tutorial Chair as early as possible. For consideration for the regular technical program, please submit five (5) copies of an extended abstract of about one thousand words of original work on any aspect of memory technology, design, and testing to either Program Chair. Submissions should include full names and affiliations of authors and contact information, and should indicate the intended presenter. Submissions are due February 25, 1998. Acceptance notification will be on March 31, 1998. Final papers will be due May 15, 1998 and must be in postscript format. Presentation time slots will average 30 minutes. GENERAL CHAIR Fabrizio Lombardi Computer Science MS 3112 Texas A&M University College Station TX 77843, USA 409/845-5464; fax 847-8578 lombardi@cs.tamu.edu LOCAL ARRANGEMENTS Craig Soldat, Hewlett-Packard 351 E Evelyn Ave San Jose CA 95035, USA 415/694--3499; craig_soldat@hp.com TUTORIALS CHAIR Bruce Cockburn Elec. and Comp. Engg. MS 238 CEB University of Alberta Edmonton AB T6G 2G7, Canada 403/492-3827; fax 492-1811 cockburn@ee.ualberta.ca FINANCE CHAIR Duncan "Hank" Walker Computer Science MS 3112 Texas A&M University College Station TX 77843, USA 409/862-4387; walker@cs.tamu.edu walker@cs.tamu.edu PUBLICITY CHAIR Fred "Jackie" Meyer Computer Science MS 3112 Texas A&M University College Station TX 77843, USA 409/845-1014; fmeyer@cs.tamu.edu STEERING COMMITTEE Rochit Rajsuman, Chair Equator Technologies 408/260-0599 X337 rajsuman@equator.com Bernard Courtois, TIMA Grenoble, France Ad van de Goor, Delft Univ. of Technology, The Netherlands Yervant Zorian, LogicVision San Jose CA, USA PROGRAM COMMITTEE Thomas Wik, PROGRAM co-CHAIR LSI Logic, MS E--194 1551 McCarthy Blvd, Milpitas CA 95035, USA 408/954-4471; fax 433-4561; trw@lsil.com David Lepejian, PROGRAM co-CHAIR Heuristic Physics Laboratories 1649 S Main Street, Milpitas CA 95035, USA 408/263-1466; fax 263-1584; dyl@hpl.com Glenn Chapman, Simon Fraser Univ. Bernard Courtois, TIMA Bob Evans, MosAid Paul Franzon, NCSU Ad van de Goor, Delft Univ. of Tech. Susumu Horiguchi, JAIST Omar Kebichi, Mentor Graphics Jim Lewandowski, Bell Labs Sankaran Menon, TI Sharon Murray, Medtronic Micro-Rel Ceredig Roberts, Micron Konrad Schoenemann, Siemens AG Ying Shiau, Cypress Semiconductor Stu Tewksbury, WV Univ. Seiken Yano, NEC Yervant Zorian, LogicVision From codesign-request@ifi.unizh.ch Wed Feb 18 11:27:10 1998 Return-Path: Received: from 140.114.87.70 by josef.ifi.unizh.ch with SMTP (PP) id <01229-0@josef.ifi.unizh.ch>; Wed, 18 Feb 1998 11:26:59 +0100 Received: (from isss98@localhost) by cs.nthu.edu.tw (thcs.2/cs20) id SAA01416 for codesign@ifi.unizh.ch; Wed, 18 Feb 1998 18:23:03 +0800 (CST) From: isss98 Message-Id: <199802181023.SAA01416@cs.nthu.edu.tw> Subject: ISSS98 2nd Call for Papers To: codesign@ifi.unizh.ch Date: Wed, 18 Feb 1998 18:23:03 +0800 (CST) X-Mailer: ELM [version 2.4ME+ PL34C (25)] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Status: RO X-Status: X-Keywords: X-UID: 8 I apologize if you receive multiple copies of this message or if you don't want to be in the mailing list. If you don't want to be in the mailing list, please send a mail to isss98@cs.nthu.edu.tw. Thanks. ****************************************************************************** ISSS'98 2ND CALL FOR PAPERS 11th INTERNATIONAL SYMPOSIUM ON SYSTEM SYNTHESIS Hsinchu, Taiwan, R.O.C., December 2-4, 1998 ****************************************************************************** ISSS'98 is the 11th in a very successful series of symposia oriented towards design automation professionals. At the symposium the latest results in emerging system design and synthesis technologies are presented. Original technical papers on, but not limited to, the following topics are invited: System-level synthesis: Partitioning, transformations, design reuse, quality measure, estimation, specification languages and models, intermediate forms, embedded processor synthesis. Hardware-software co-design: Hardware/software tradeoffs, interfaces and communications, co-simulation, co-emulation and co-synthesis, embedded system architectures, system exploration, system testbench development, design automation for rapid system prototyping. Programmable (multi-) processor-based design and synthesis: ASIPs, code generation, instruction-set specification, design and simulation, high-level code transformations. System design experience and methodologies: Application-specific parallel/distributed systems, industrial telecom, robotics, vision, video, audio and speech processing systems, formalized design methodology, process management. Embedded and real-time system software: Software development, constraint specification, process scheduling, real-time operating systems, distributed systems. High-level and architectural synthesis: Datapath, control, memory, and interface synthesis from behavioral specifications, clocking/timing optimization, physical design models for high-level tradeoffs, hardware accelerators/coprocessors. Synthesis for low power, testability and verifiability in the above areas. --------------------------------------------------------------------------- Submitted papers should be 6 pages or less in IEEE 2-column style (10pt), as close as possible to the final content. They should clearly specify contributions and results, and include a separate cover page with the following: paper title, complete name, address, telephone, fax, and email address of each author, identification of the corresponding author, and the category (numbered 1-7 above) most closely matching the paper's content. Papers exceeding the page limit will be returned to the authors. Submissions simultaneously sent to other forums will not be considered. The symposium proceedings will be published by the IEEE Computer Society Press. Everyone is strongly encouraged to submit the paper and cover page electronically as explained on our web page (http://www.cs.nthu.edu.tw/~isss98/ under the "Call for papers/submission instructions"). If you do not have access to a web browser you may also send the uuencoded gzipped (standard) Postscript paper and separate cover page (in ASCII format) to the email address ``isss98@cs.nthu.edu.tw''. If electronic submission is infeasible, 8 copies of the paper should be send along with the cover page to the Program Chair at the following address: Allen C.-H. Wu, ISSS'98 Computer Science Department Tsing Hua University Hsinchu, Taiwan 30043 Tel: 886-3-5715131 ext 3517 Fax: 886-3-5723694 Email: chunghaw@cs.nthu.edu.tw, isss98@cs.nthu.edu.tw =========================================================================== Author's schedule: Submission deadline: April 5, 1998 Notification of Acceptance: June 5, 1998 Camera-ready copies: July 5, 1998 ============================================================================ Steering Committee: General Chair: Francky Catthoor, IMEC Honorary Chair: C. L. Liu, Tsing Hua University Program Chair: Allen C.-H. Wu, Tsing Hua University Publications Chair: Liang-Gee Chen. Taiwan University Panels Chair: Nikil Dutt, University of California, Irvine Publicity Co-Chairs: Jyuo-Min Shyu, Industrial Technology Research Institute Ing-Jer Huang, Sun Yat-Sen University Finance Chair: Wen-Zen Shen, Chiao Tung University Local Arrangement Chair Steve Y.-L. Lin, Tsing Hua University Past Chair: Frank Vahid, University of California, Riverside ============================================================================ Technical program committee: Marleen Ade, K.U. Leuven Gaetano Borriello, Univ. Washington Raul Camposano, Synopsys Nikil Dutt, U.C. Irvine Rolf Ernst, Tech. Univ. Braunschweig Masahiro Fujita, Fujitsu Daniel Gajski, U.C. Irvine Cathy Gebotys, Univ. Waterloo Yu-Chin Hsu, Avant! Ahmed A. Jerraya, TIMA Kayhan Kucukcakar, Motorola Fadi Kurdahi, U.C. Irvine Steve Y.L. Lin, Tsing Hua Univ. Paul Lippens, Philips Jan Madsen, Tech. Univ. Denmark Lev Markov, Mentor Graphics Peter Marwedel, Univ. Dortmund Vijay Nagasamy, VSIS Inc. Yukihiro Nakamura, Kyoto Univ. Sanjiv Narayan, Ambit Design Systems Kevin O'brien, Leda B. Ramakrishna (Bob) Rau, HP Labs. Wolfgang Rosenstiel, Univ. Tubingen, FZI Edwin Sha, Univ. Notre Dame Leon Stok, IBM Donald Thomas, CMU Diederik Verkest, IMEC Kazutoshi Wakabayashi, NEC Robert Walker, Kent State Univ. Wayne Wolf, Princeton Hiroto Yasuura, Kyushu Univ. ****************************************************************************** Check the WWW at ``http://www.cs.nthu.edu.tw/~isss98/'' for the latest ISSS'98 related information. Sponsored by IEEE CS Technical Commitee on Design Automation (approval pending) and ACM SIGDA (approval pending). In Cooperation with Ministry of Education, R.O.C.(approval pending) and National Science Council, R.O.C.(approval pending). ****************************************************************************** From codesign-request@ifi.unizh.ch Thu Feb 19 16:29:28 1998 Return-Path: Received: from igw3.watson.ibm.com by josef.ifi.unizh.ch with SMTP (PP) id <10473-0@josef.ifi.unizh.ch>; Thu, 19 Feb 1998 15:31:21 +0100 Received: from mailhub.watson.ibm.com (mailhub.watson.ibm.com [9.2.250.97]) by igw3.watson.ibm.com (8.8.7/07-11-97) with ESMTP id JAA07962 for ; Thu, 19 Feb 1998 09:31:27 -0500 Received: from chameleon.watson.ibm.com (chameleon.watson.ibm.com [9.2.220.64]) by mailhub.watson.ibm.com (8.8.7/Feb-10-98) with SMTP id JAA07738 for ; Thu, 19 Feb 1998 09:31:26 -0500 Received: by chameleon.watson.ibm.com (AIX 4.1/UCB 5.64/6/25/96) id AA38758; Thu, 19 Feb 1998 09:31:24 -0500 Date: Thu, 19 Feb 1998 09:31:24 -0500 Message-Id: <9802191431.AA38758@chameleon.watson.ibm.com> From: Leon Stok To: codesign@ifi.unizh.ch Subject: IWLS98 Submission Deadline Status: RO X-Status: X-Keywords: X-UID: 9 ------------------------------------- NEW Submission DEADLINE: Mar 15, 1998 ------------------------------------- ( The submission server will not accept papers for review anymore after Monday Mar 16, 8AM EST ) 1998 IEEE/ACM International Workshop on Logic Synthesis ------------------------------------------------------- Granlibakken Resort, Lake Tahoe, California June 7-10 , 1998 Call for Papers See http://domino.watson.ibm.com/IWLS98/IWLS98.NSF for more information. From codesign-request@ifi.unizh.ch Thu Feb 26 16:07:18 1998 Return-Path: Received: from zodiac.cbl.ncsu.edu by josef.ifi.unizh.ch with SMTP (PP) id <02462-0@josef.ifi.unizh.ch>; Wed, 25 Feb 1998 22:42:16 +0100 Received: (from brglez@localhost) by zodiac.cbl.ncsu.edu (8.8.7/8.8.7) id QAA07502 for codesign@ifi.unizh.ch; Wed, 25 Feb 1998 16:35:31 -0500 (EST) Date: Wed, 25 Feb 1998 16:35:31 -0500 (EST) Message-Id: <199802252135.QAA07502@zodiac.cbl.ncsu.edu> From: Franc Brglez Subject: Call for participation - CAD heuristics experiments Status: RO X-Status: X-Keywords: X-UID: 10 Hello, If you work in the area of CAD of microelectronic systems or heuristics to solve NP-hard problems, some items in this message may be of interest. The purpose is to (1) alert you to new postings on our web-server, in particular under http://www.cbl.ncsu.edu/experiments/ (2) invite you to participate in the new generation of design and execution of peer-reviewed collaborative experiments, using workflows on the Web. With your participation, we hope to present some of this effort as -- part of a session during International Workshop on Logic Synthesis (IWLS'98) (http://domino.watson.ibm.com/IWLS98/IWLS98.NSF) -- part of the Vela Project demo in the University Booth during DAC'98 (http://erebor.cudenver.edu/sigdabooth/,http://www.dac.com) -- part of a joint-session proposal to ICCAD'98 (http://www.iccad.com) The recent first-generation capability to synthesize a large number of equivalence class circuit mutants from a copy of a known design, maintaining either wiring signature invariance or entropy signature invariance, motivated us to conduct a series of statistical experiments with algorithms in layout, logic, and test synthesis. These experiments are beginning to address tests of hypothesis such as "Is the improvement due to the choice of the algorithm or due to chance?" Wide participation and a number of peer-reviewed experiments are required to resolve such issues. The first such discussions may take place at IWLS'98. In particular, thousands of experiments with hundreds of current circuit mutants, posted under http://www.cbl.ncsu.edu/experiments/ already raise such issues in logic minimization and variable ordering of ROBDDs. For example, some but not all of the mutants of well-known and relatively simple circuits such as C1355, appear as a serious challenge for ROBDD variable ordering algorithms but not for atpg algorithms, etc. If you feel this message reached you in error or out-of-context, we apologize. We will not repeat it again. -- Dr. Franc Brglez Collaborative Benchmarking Laboratory (CBL) Dept. of Computer Science NC State University, Box 7550 Raleigh, NC 27695-7550, USA phone: 919-515-9675 e-mail: brglez@cbl.ncsu.edu fax: 919-513-1895 WWW: http://www.cbl.ncsu.edu/~brglez anonymous ftp: ftp.cbl.ncsu.edu autoreply: info@cbl.ncsu.edu From codesign-request@ifi.unizh.ch Mon Mar 9 18:06:56 1998 Return-Path: Received: from cs20.cs.nthu.edu.tw by josef.ifi.unizh.ch with SMTP (PP) id <26876-0@josef.ifi.unizh.ch>; Mon, 9 Mar 1998 16:15:52 +0100 Received: (from isss98@localhost) by cs.nthu.edu.tw (thcs.2/cs20) id XAA10384 for codesign@ifi.unizh.ch; Mon, 9 Mar 1998 23:11:10 +0800 (CST) From: isss98 Message-Id: <199803091511.XAA10384@cs.nthu.edu.tw> Subject: ISSS98 3rd Call for Papers To: codesign@ifi.unizh.ch Date: Mon, 9 Mar 1998 23:11:10 +0800 (CST) X-Mailer: ELM [version 2.4ME+ PL34C (25)] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Status: RO X-Status: X-Keywords: X-UID: 11 I apologize if you receive multiple copies of this message or if you don't want to be in the mailing list. If you don't want to be in the mailing list, please send a mail to isss98@cs.nthu.edu.tw. Thanks. ****************************************************************************** ISSS'98 3RD CALL FOR PAPERS 11th INTERNATIONAL SYMPOSIUM ON SYSTEM SYNTHESIS Hsinchu, Taiwan, R.O.C., December 2-4, 1998 ****************************************************************************** ISSS'98 is the 11th in a very successful series of symposia oriented towards design automation professionals. At the symposium the latest results in emerging system design and synthesis technologies are presented. Original technical papers on, but not limited to, the following topics are invited: System-level synthesis: Partitioning, transformations, design reuse, quality measure, estimation, specification languages and models, intermediate forms, embedded processor synthesis. Hardware-software co-design: Hardware/software tradeoffs, interfaces and communications, co-simulation, co-emulation and co-synthesis, embedded system architectures, system exploration, system testbench development, design automation for rapid system prototyping. Programmable (multi-) processor-based design and synthesis: ASIPs, code generation, instruction-set specification, design and simulation, high-level code transformations. System design experience and methodologies: Application-specific parallel/distributed systems, industrial telecom, robotics, vision, video, audio and speech processing systems, formalized design methodology, process management. Embedded and real-time system software: Software development, constraint specification, process scheduling, real-time operating systems, distributed systems. High-level and architectural synthesis: Datapath, control, memory, and interface synthesis from behavioral specifications, clocking/timing optimization, physical design models for high-level tradeoffs, hardware accelerators/coprocessors. Synthesis for low power, testability and verifiability in the above areas. --------------------------------------------------------------------------- Submitted papers should be 6 pages or less in IEEE 2-column style (10pt), as close as possible to the final content. They should clearly specify contributions and results, and include a separate cover page with the following: paper title, complete name, address, telephone, fax, and email address of each author, identification of the corresponding author, and the category (numbered 1-7 above) most closely matching the paper's content. Papers exceeding the page limit will be returned to the authors. Submissions simultaneously sent to other forums will not be considered. The symposium proceedings will be published by the IEEE Computer Society Press. Everyone is strongly encouraged to submit the paper and cover page electronically as explained on our web page (http://www.cs.nthu.edu.tw/~isss98/ under the "Call for papers/submission instructions"). If you do not have access to a web browser you may also send the uuencoded gzipped (standard) Postscript paper and separate cover page (in ASCII format) to the email address ``isss98@cs.nthu.edu.tw''. If electronic submission is infeasible, 8 copies of the paper should be send along with the cover page to the Program Chair at the following address: Allen C.-H. Wu, ISSS'98 Computer Science Department Tsing Hua University Hsinchu, Taiwan 30043 Tel: 886-3-5715131 ext 3517 Fax: 886-3-5723694 Email: chunghaw@cs.nthu.edu.tw, isss98@cs.nthu.edu.tw =========================================================================== Author's schedule: Submission deadline: April 5, 1998 Notification of Acceptance: June 5, 1998 Camera-ready copies: July 5, 1998 ============================================================================ Steering Committee: General Chair: Francky Catthoor, IMEC Honorary Chair: C. L. Liu, Tsing Hua University Program Chair: Allen C.-H. Wu, Tsing Hua University Publications Chair: Liang-Gee Chen. Taiwan University Panels Chair: Nikil Dutt, University of California, Irvine Publicity Co-Chairs: Jyuo-Min Shyu, Industrial Technology Research Institute Ing-Jer Huang, Sun Yat-Sen University Finance Chair: Wen-Zen Shen, Chiao Tung University Local Arrangement Chair Steve Y.-L. Lin, Tsing Hua University Past Chair: Frank Vahid, University of California, Riverside ============================================================================ Technical program committee: Marleen Ade, K.U. Leuven Gaetano Borriello, Univ. Washington Raul Camposano, Synopsys Nikil Dutt, U.C. Irvine Rolf Ernst, Tech. Univ. Braunschweig Masahiro Fujita, Fujitsu Daniel Gajski, U.C. Irvine Cathy Gebotys, Univ. Waterloo Yu-Chin Hsu, Avant! Ahmed A. Jerraya, TIMA Kayhan Kucukcakar, Motorola Fadi Kurdahi, U.C. Irvine Steve Y.L. Lin, Tsing Hua Univ. Paul Lippens, Philips Jan Madsen, Tech. Univ. Denmark Lev Markov, Mentor Graphics Peter Marwedel, Univ. Dortmund Vijay Nagasamy, VSIS Inc. Yukihiro Nakamura, Kyoto Univ. Sanjiv Narayan, Ambit Design Systems Kevin O'brien, Leda B. Ramakrishna (Bob) Rau, HP Labs. Wolfgang Rosenstiel, Univ. Tubingen, FZI Edwin Sha, Univ. Notre Dame Leon Stok, IBM Donald Thomas, CMU Diederik Verkest, IMEC Kazutoshi Wakabayashi, NEC Robert Walker, Kent State Univ. Wayne Wolf, Princeton Hiroto Yasuura, Kyushu Univ. ****************************************************************************** Check the WWW at ``http://www.cs.nthu.edu.tw/~isss98/'' for the latest ISSS'98 related information. Sponsored by IEEE CS Technical Commitee on Design Automation (approval pending) and ACM SIGDA (approval pending). In Cooperation with Ministry of Education, R.O.C.(approval pending) and National Science Council, R.O.C.(approval pending). ****************************************************************************** From codesign-request@ifi.unizh.ch Mon Mar 16 09:24:19 1998 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <00597-0@josef.ifi.unizh.ch>; Mon, 16 Mar 1998 09:24:05 +0100 Return-Path: X-Received: from pol88b.polito.it by josef.ifi.unizh.ch with SMTP (PP) id <11644-0@josef.ifi.unizh.ch>; Fri, 13 Mar 1998 17:53:06 +0100 X-Received: from chiusella.polito.it.polito.it (chiusella.polito.it) by polito.it (PMDF V4.2-15 #3020) id <01IUMJVLL1W001DLTS@polito.it>; Fri, 13 Mar 1998 17:40:44 GMT+1 X-Received: by chiusella.polito.it.polito.it (4.1/SMI-4.1) id AA15198; Fri, 13 Mar 98 17:40:43 +0100 Date: Fri, 13 Mar 1998 17:40:43 +0100 From: tttc@chiusella.polito.it (Paolo Prinetto) Subject: IEEE TTTC - C98FMTGF - call for papers To: pilz@ifi.unizh.ch Message-id: <9803131640.AA15198@chiusella.polito.it.polito.it> X-Envelope-to: pilz@ifi.unizh.ch Content-transfer-encoding: 7BIT Apparently-To: PILZ Markus ReSent-Date: Mon, 16 Mar 1998 09:22:43 +0100 (MET) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 12 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % IEEE Computer Society % Test Technology Technical Committee % % % .... FOR YOUR INFORMATION.... % % A free service of the Technical Meeting Group % % % This message contains public information, only, and % the receiver is allowed, and invited, to copy it and % distribute it further. % % % For more information contact % or visit http://www.computer.org/tab/tttc/ % % If you would like to be removed from this mailing list, % please send an e-mail to % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% CALL FOR PARTICIPATION ====================== Call for Participation : IEEE Computer Society International Workshop on Innovative Approaches to Fault Modeling, Test Generation, and Fault Simulation using Hardware Description Languages (C98FMTGF) Co-sponsored by the Computer Society Test Technology Technical Committee, the Center for Semicustom Integrated Systems (CSIS), and the Virginia Tech Informations Systems Center (VISC) Location : University of Virginia Department of Electrical Engineering Thornton Hall Charlottesville, Virginia 22903-2442 Date : August 31 - September 2, 1998 General Chair : James Armstrong Bradley Department of Electrical Engineering Virginia Tech Blacksburg, Virginia 24061-0111 Phone : 540-231-4723 Fax : 540-231-3362 E-mail : jra@vt.edu Program Chair : James Aylor University of Virginia Department of Electrical Engineering Thornton Hall - C219 Charlottesville, Virginia 22903-2442 Phone : 804-924-6100 Fax : 804-924-8818 E-mail : jha@virginia.edu The focus of the workshop is to bring together researchers in the areas of fault modeling, test generation, and fault simulation using hardware description languages (VHDL and Verilog) from industry, government, and academia. The workshop will consists of 3 90 minutes sessions per day with 3 papers presented in each session. Each paper will be limited to 10 pages, and each author will be asked to give a 20 minute presentation with 10 minutes for questions. A proceedings will be created from the papers, and each participant will receive a copy of the proceedings for attending the workshop. The workshop is limited to 50 participants. The cost for attending the workshop is $350 for members of the IEEE Computer Society, and $450 for non-members. There will be a charge for late registration. PROGRAM COMMITTEE ================= James Armstrong Virginia Tech (General Chair) James Aylor University of Virginia (Program Chair) Jacob Abraham University of Texas Todd DeLong University of Virginia F.G. Gray Virginia Tech James Hanna Air Force Research Laboratory John Hayes University of Michigan Barry Johnson University of Virginia Rohit Kapur Synopsys Johan Karlsson Chalmers University of Technology Jake Karrfalt ASC Michael McKinney Texas Instruments, Inc. Zainalabedin Navabi Northeastern University Paolo PRINETTO Politecnico di Torino Pablo P. Sanchez Universidad de Cantabria Matteo SONZA REORDA Politecnico di Torino D. Todd Smith Virginia Military Institute IMPORTANT DATES =============== Abstract submission : 24 April, 1998 Acceptance notification : 22 May, 1998 Paper submission : 22 June, 1998 PARTICIPATION FORM ================== Please complete the following form and return it (along with an abstract if you would like to present a paper) via regular mail or via electronic mail (preferred) to Todd DeLong University of Virginia Department of Electrical Engineering Thornton Hall - E205 Charlottesville, Virginia 22903-2442 Phone : 804-982-2382 Fax : 804-924-8818 E-mail : t.delong@computer.org ============================================================================= Name : Organization : Address Line 1 : Address Line 2 : Address Line 3 : Address Line 4 : Phone : Fax : E-mail : From codesign-request@ifi.unizh.ch Mon Mar 30 13:07:09 1998 Return-Path: Received: from cs20.cs.nthu.edu.tw by josef.ifi.unizh.ch with SMTP (PP) id <20668-0@josef.ifi.unizh.ch>; Mon, 30 Mar 1998 13:05:38 +0200 Received: (from isss98@localhost) by cs.nthu.edu.tw (thcs.2/cs20) id QAA21420 for codesign@ifi.unizh.ch; Mon, 30 Mar 1998 16:04:10 +0800 (CST) From: isss98 Message-Id: <199803300804.QAA21420@cs.nthu.edu.tw> Subject: ISSS98 Final Call for Papers To: codesign@ifi.unizh.ch Date: Mon, 30 Mar 1998 16:04:10 +0800 (CST) X-Mailer: ELM [version 2.4ME+ PL34C (25)] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Status: RO X-Status: X-Keywords: X-UID: 13 I apologize if you receive multiple copies of this message or if you don't want to be in the mailing list. If you don't want to be in the mailing list, please send a mail to isss98@cs.nthu.edu.tw include your old Email address. Thanks. ****************************************************************************** ISSS'98 FINAL CALL FOR PAPERS 11th INTERNATIONAL SYMPOSIUM ON SYSTEM SYNTHESIS Hsinchu, Taiwan, R.O.C., December 2-4, 1998 ****************************************************************************** IMPORTANT NEWS: Upon to many requests the paper submission dead-line will be postponed to 4/13. ****************************************************************************** ISSS'98 is the 11th in a very successful series of symposia oriented towards design automation professionals. At the symposium the latest results in emerging system design and synthesis technologies are presented. Original technical papers on, but not limited to, the following topics are invited: System-level synthesis: Partitioning, transformations, design reuse, quality measure, estimation, specification languages and models, intermediate forms, embedded processor synthesis. Hardware-software co-design: Hardware/software tradeoffs, interfaces and communications, co-simulation, co-emulation and co-synthesis, embedded system architectures, system exploration, system testbench development, design automation for rapid system prototyping. Programmable (multi-) processor-based design and synthesis: ASIPs, code generation, instruction-set specification, design and simulation, high-level code transformations. System design experience and methodologies: Application-specific parallel/distributed systems, industrial telecom, robotics, vision, video, audio and speech processing systems, formalized design methodology, process management. Embedded and real-time system software: Software development, constraint specification, process scheduling, real-time operating systems, distributed systems. High-level and architectural synthesis: Datapath, control, memory, and interface synthesis from behavioral specifications, clocking/timing optimization, physical design models for high-level tradeoffs, hardware accelerators/coprocessors. Synthesis for low power, testability and verifiability in the above areas. --------------------------------------------------------------------------- Submitted papers should be 6 pages or less in IEEE 2-column style (10pt), as close as possible to the final content. They should clearly specify contributions and results, and include a separate cover page with the following: paper title, complete name, address, telephone, fax, and email address of each author, identification of the corresponding author, and the category (numbered 1-7 above) most closely matching the paper's content. Papers exceeding the page limit will be returned to the authors. Submissions simultaneously sent to other forums will not be considered. The symposium proceedings will be published by the IEEE Computer Society Press. Everyone is strongly encouraged to submit the paper and cover page electronically as explained on our web page (http://www.cs.nthu.edu.tw/~isss98/ under the "Call for papers/submission instructions"). If you do not have access to a web browser you may also send the uuencoded gzipped (standard) Postscript paper and separate cover page (in ASCII format) to the email address ``isss98@cs.nthu.edu.tw''. If electronic submission is infeasible, 8 copies of the paper should be send along with the cover page to the Program Chair at the following address: Allen C.-H. Wu, ISSS'98 Computer Science Department Tsing Hua University Hsinchu, Taiwan 30043 Tel: 886-3-5715131 ext 3517 Fax: 886-3-5723694 Email: chunghaw@cs.nthu.edu.tw, isss98@cs.nthu.edu.tw =========================================================================== Author's schedule: Submission deadline: April 5, 1998 Notification of Acceptance: June 5, 1998 Camera-ready copies: July 5, 1998 ============================================================================ Steering Committee: General Chair: Francky Catthoor, IMEC Honorary Chair: C. L. Liu, Tsing Hua University Program Chair: Allen C.-H. Wu, Tsing Hua University Publications Chair: Liang-Gee Chen. Taiwan University Panels Chair: Nikil Dutt, University of California, Irvine Publicity Co-Chairs: Jyuo-Min Shyu, Industrial Technology Research Institute Ing-Jer Huang, Sun Yat-Sen University Finance Chair: Wen-Zen Shen, Chiao Tung University Local Arrangement Chair Steve Y.-L. Lin, Tsing Hua University Past Chair: Frank Vahid, University of California, Riverside ============================================================================ Technical program committee: Marleen Ade, K.U. Leuven Gaetano Borriello, Univ. Washington Raul Camposano, Synopsys Nikil Dutt, U.C. Irvine Rolf Ernst, Tech. Univ. Braunschweig Masahiro Fujita, Fujitsu Daniel Gajski, U.C. Irvine Cathy Gebotys, Univ. Waterloo Yu-Chin Hsu, Avant! Ahmed A. Jerraya, TIMA Kayhan Kucukcakar, Motorola Fadi Kurdahi, U.C. Irvine Steve Y.L. Lin, Tsing Hua Univ. Paul Lippens, Philips Jan Madsen, Tech. Univ. Denmark Lev Markov, Mentor Graphics Peter Marwedel, Univ. Dortmund Vijay Nagasamy, VSIS Inc. Yukihiro Nakamura, Kyoto Univ. Sanjiv Narayan, Ambit Design Systems Kevin O'brien, Leda B. Ramakrishna (Bob) Rau, HP Labs. Wolfgang Rosenstiel, Univ. Tubingen, FZI Edwin Sha, Univ. Notre Dame Leon Stok, IBM Donald Thomas, CMU Diederik Verkest, IMEC Kazutoshi Wakabayashi, NEC Robert Walker, Kent State Univ. Wayne Wolf, Princeton Hiroto Yasuura, Kyushu Univ. ****************************************************************************** Check the WWW at ``http://www.cs.nthu.edu.tw/~isss98/'' for the latest ISSS'98 related information. Sponsored by IEEE CS Technical Commitee on Design Automation (approval pending) and ACM SIGDA (approval pending). In Cooperation with Ministry of Education, R.O.C.(approval pending) and National Science Council, R.O.C.(approval pending). ****************************************************************************** From codesign-request@ifi.unizh.ch Fri Apr 3 07:57:08 1998 Return-Path: Received: from cs20.cs.nthu.edu.tw by josef.ifi.unizh.ch with SMTP (PP) id <15393-0@josef.ifi.unizh.ch>; Fri, 3 Apr 1998 07:56:55 +0200 Received: (from isss98@localhost) by cs.nthu.edu.tw (thcs.2/cs20) id NAA24213 for codesign@ifi.unizh.ch; Fri, 3 Apr 1998 13:48:57 +0800 (CST) From: isss98 Message-Id: <199804030548.NAA24213@cs.nthu.edu.tw> Subject: Submission dead-line extention to 4/13 To: codesign@ifi.unizh.ch Date: Fri, 3 Apr 1998 13:48:56 +0800 (CST) X-Mailer: ELM [version 2.4ME+ PL34C (25)] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Status: RO X-Status: X-Keywords: X-UID: 14 I apologize if you receive multiple copies of this message or if you don't want to be in the mailing list. If you don't want to be in the mailing list, please send a mail to isss98@cs.nthu.edu.tw include your old Email address. Thanks. ****************************************************************************** ISSS'98 FINAL CALL FOR PAPERS (Submission dead-line extention to 4/13) 11th INTERNATIONAL SYMPOSIUM ON SYSTEM SYNTHESIS Hsinchu, Taiwan, R.O.C., December 2-4, 1998 ****************************************************************************** IMPORTANT NEWS: Upon to many requests the paper submission dead-line will be postponed to 4/13. ****************************************************************************** ISSS'98 is the 11th in a very successful series of symposia oriented towards design automation professionals. At the symposium the latest results in emerging system design and synthesis technologies are presented. Original technical papers on, but not limited to, the following topics are invited: System-level synthesis: Partitioning, transformations, design reuse, quality measure, estimation, specification languages and models, intermediate forms, embedded processor synthesis. Hardware-software co-design: Hardware/software tradeoffs, interfaces and communications, co-simulation, co-emulation and co-synthesis, embedded system architectures, system exploration, system testbench development, design automation for rapid system prototyping. Programmable (multi-) processor-based design and synthesis: ASIPs, code generation, instruction-set specification, design and simulation, high-level code transformations. System design experience and methodologies: Application-specific parallel/distributed systems, industrial telecom, robotics, vision, video, audio and speech processing systems, formalized design methodology, process management. Embedded and real-time system software: Software development, constraint specification, process scheduling, real-time operating systems, distributed systems. High-level and architectural synthesis: Datapath, control, memory, and interface synthesis from behavioral specifications, clocking/timing optimization, physical design models for high-level tradeoffs, hardware accelerators/coprocessors. Synthesis for low power, testability and verifiability in the above areas. --------------------------------------------------------------------------- Submitted papers should be 6 pages or less in IEEE 2-column style (10pt), as close as possible to the final content. They should clearly specify contributions and results, and include a separate cover page with the following: paper title, complete name, address, telephone, fax, and email address of each author, identification of the corresponding author, and the category (numbered 1-7 above) most closely matching the paper's content. Papers exceeding the page limit will be returned to the authors. Submissions simultaneously sent to other forums will not be considered. The symposium proceedings will be published by the IEEE Computer Society Press. Everyone is strongly encouraged to submit the paper and cover page electronically as explained on our web page (http://www.cs.nthu.edu.tw/~isss98/ under the "Call for papers/submission instructions"). If you do not have access to a web browser you may also send the uuencoded gzipped (standard) Postscript paper and separate cover page (in ASCII format) to the email address ``isss98@cs.nthu.edu.tw''. If electronic submission is infeasible, 8 copies of the paper should be send along with the cover page to the Program Chair at the following address: Allen C.-H. Wu, ISSS'98 Computer Science Department Tsing Hua University Hsinchu, Taiwan 30043 Tel: 886-3-5715131 ext 3517 Fax: 886-3-5723694 Email: chunghaw@cs.nthu.edu.tw, isss98@cs.nthu.edu.tw =========================================================================== Author's schedule: Submission deadline: April 5, 1998 Notification of Acceptance: June 5, 1998 Camera-ready copies: July 5, 1998 ============================================================================ Steering Committee: General Chair: Francky Catthoor, IMEC Honorary Chair: C. L. Liu, Tsing Hua University Program Chair: Allen C.-H. Wu, Tsing Hua University Publications Chair: Liang-Gee Chen. Taiwan University Panels Chair: Nikil Dutt, University of California, Irvine Publicity Co-Chairs: Jyuo-Min Shyu, Industrial Technology Research Institute Ing-Jer Huang, Sun Yat-Sen University Finance Chair: Wen-Zen Shen, Chiao Tung University Local Arrangement Chair Steve Y.-L. Lin, Tsing Hua University Past Chair: Frank Vahid, University of California, Riverside ============================================================================ Technical program committee: Marleen Ade, K.U. Leuven Gaetano Borriello, Univ. Washington Raul Camposano, Synopsys Nikil Dutt, U.C. Irvine Rolf Ernst, Tech. Univ. Braunschweig Masahiro Fujita, Fujitsu Daniel Gajski, U.C. Irvine Cathy Gebotys, Univ. Waterloo Yu-Chin Hsu, Avant! Ahmed A. Jerraya, TIMA Kayhan Kucukcakar, Motorola Fadi Kurdahi, U.C. Irvine Steve Y.L. Lin, Tsing Hua Univ. Paul Lippens, Philips Jan Madsen, Tech. Univ. Denmark Lev Markov, Mentor Graphics Peter Marwedel, Univ. Dortmund Vijay Nagasamy, VSIS Inc. Yukihiro Nakamura, Kyoto Univ. Sanjiv Narayan, Ambit Design Systems Kevin O'brien, Leda B. Ramakrishna (Bob) Rau, HP Labs. Wolfgang Rosenstiel, Univ. Tubingen, FZI Edwin Sha, Univ. Notre Dame Leon Stok, IBM Donald Thomas, CMU Diederik Verkest, IMEC Kazutoshi Wakabayashi, NEC Robert Walker, Kent State Univ. Wayne Wolf, Princeton Hiroto Yasuura, Kyushu Univ. ****************************************************************************** Check the WWW at ``http://www.cs.nthu.edu.tw/~isss98/'' for the latest ISSS'98 related information. Sponsored by IEEE CS Technical Commitee on Design Automation (approval pending) and ACM SIGDA (approval pending). In Cooperation with Ministry of Education, R.O.C.(approval pending) and National Science Council, R.O.C.(approval pending). ****************************************************************************** From codesign-request@ifi.unizh.ch Sat Apr 11 07:41:57 1998 Return-Path: Received: from 202.141.64.29 by josef.ifi.unizh.ch with SMTP (PP) id <02376-0@josef.ifi.unizh.ch>; Sat, 11 Apr 1998 07:40:32 +0200 Received: from henna.iitd.ernet.in by kriti.iitd.ernet.in (5.x/SMI-SVR4) id AA16423; Sat, 11 Apr 1998 11:02:17 +0600 Received: from eesun01.ee.iitd.ernet.in by henna.iitd.ernet.in (4.1/SMI-4.1-MHS-7.0 ) id AA23402; Sat, 11 Apr 98 11:01:13 IST X-Organisation: Indian Institute of Technology, New Delhi. Received: by eesun01.ee.iitd.ernet.in (SMI-8.6/SMI-SVR4) id LAA16196; Sat, 11 Apr 1998 11:05:20 -0500 Date: Sat, 11 Apr 1998 11:05:20 -0500 From: rkumar@ee.iitd.ernet.in (Dr.C.P.Ravikumar) Message-Id: <199804111605.LAA16196@eesun01.ee.iitd.ernet.in> To: codesign@ifi.unizh.ch, codesign@vhdl.org, Ahmed-Amine.Jerraya@imag.fr Subject: Re: CODES/CASHE'98 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Content-Md5: 6tmVoR34sKhaA42kdfsffg== Status: RO X-Status: X-Keywords: X-UID: 15 CALL FOR PARTICIPATION VLSI Design & Test Workshops August 6-7, 1998 New Delhi, India Sponsored by: IEEE-Computer Society and VLSI Society of India (Confirmation Awaited) Background: During the 11th International Conference on VLSI Design, which was held in Chennai, India, during January 4-7, 1998, three workshops were conducted. These were related to High-level Design, Physical Design, and Testing of VLSI Integrated Circuits. The workshops were created as platforms for informal discussion of ongoing work. There was an enthusiastic response to the workshops. The attendees felt the need to have such workshops on a regular basis. Workshops provide an opportunity to present ongoing projects to peers and receive their feedback. Since no proceedings are brought out after the workshop, there is no copyright release involved. Thus an informal presentation made at the workshop can be refined for possible presentation at a conference or a journal at a later date. It was felt by a large majority of the attendees that the VLSI Design workshops should be held at a time other than the VLSI Design conference. Accordingly, we plan to hold four workshops in New Delhi on August 7, 1998. Topics of Workshops: Workshop on High-level Design will discuss issues related to system-level synthesis, core-based design of SOC, high-level synthesis, logic synthesis, and FPGA synthesis. Workshop on Physical Design will discuss issues related to floor-planning, placement, and routing of high-performance integrated circuits and printed wire boards. Workshop on Testing will discuss issues related to testing and testability of digital, analog, and mixed-signal circuits and systems. Workshop on VLSI Technology will discuss issues related to fabrication and packaging of integrated circuits and systems. Technical Program Committee C.P. Ravikumar, IIT Delhi (Organizing Chair) Program Chairs for the Workshops: High-level Design Workshop : Anshul Kumar, IIT Delhi Physical Design Workshop : B. Bhattacharya, ISI Calcutta Test Workshop : C.P. Ravikumar, IIT Delhi Technology Workshop : Anand Bariya, Natsem (India) Technical Program Committee Vishwani Agrawal, Lucent Technologies, USA Bhargab Bhattacharya, ISI Calcutta Yervant Zorian, Logic Vision, USA Rob Roy, Intel Corporation, USA D.-H. Heo, Intel Corporation, USA Sarma Vrudhula, Arizona State University, USA Kozo Kinoshita, Japan C. Tsui, Hong Kong Univ. of Sci. and Tech. J. Becker, Tech.l Univ. of Dormstadt, Germany M. Sachdev, Philips (The Netherlands) Chandrashekhar, CEERI, Pilani, India Anand Bariya, National Semiconductors (India) P. Palchoudhuri, Bengal Engineering College A. Jain, IIT Kanpur (India) M. Balakrishnan, IIT Delhi (India) Anshul Kumar, IIT Delhi (India) S.D. Sherlekar, Silicon Automation Systems, India Keerti Heragu, Texas Instruments, USA Sandeep Pagey, Cadence Design Systems, India ADDRESS FOR CORRESPONDENCE 1-page abstract of the paper may be sent to C.P. Ravikumar Department of Electrical Engineering Indian Institute of Technology New Delhi 110016 INDIA E-mail submissions are acceptable, if they are in ASCII or PostScript format. Send your submission to rkumar@ee.iitd.ernet.in FAX Submissions may be sent to : 91-11-6966264 IMPORTANT DATES Last Date for submission : April 30, 1998 Notification of acceptance : June 20, 1998 From codesign-request@ifi.unizh.ch Mon Apr 13 20:37:19 1998 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <09931-0@josef.ifi.unizh.ch>; Mon, 13 Apr 1998 20:36:58 +0200 Return-Path: X-Received: from pol88b.polito.it by josef.ifi.unizh.ch with SMTP (PP) id <25828-0@josef.ifi.unizh.ch>; Mon, 13 Apr 1998 00:56:45 +0200 X-Received: from chiusella.polito.it.polito.it (chiusella.polito.it) by polito.it (PMDF V4.2-15 #3020) id <01IVSTSOAXM88WYY0X@polito.it>; Sun, 12 Apr 1998 23:57:59 GMT+1 X-Received: by chiusella.polito.it.polito.it (4.1/SMI-4.1) id AA12017; Sun, 12 Apr 98 23:57:55 +0200 Date: Sun, 12 Apr 1998 23:57:55 +0200 From: tttc@chiusella.polito.it (Paolo Prinetto) Subject: IEEE TTTC - 9th IEEE International Workshop on Rapid System Prototyping To: pilz@ifi.unizh.ch Message-id: <9804122157.AA12017@chiusella.polito.it.polito.it> X-Envelope-to: pilz@ifi.unizh.ch Content-transfer-encoding: 7BIT Apparently-To: PILZ Markus ReSent-Date: Mon, 13 Apr 1998 20:35:00 +0200 (MET DST) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 16 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % IEEE Computer Society % Test Technology Technical Committee % % % .... FOR YOUR INFORMATION.... % % A free service of the Technical Meeting Group % % % This message contains public information, only, and % the receiver is allowed, and invited, to copy it and % distribute it further. % % % For more information contact % or visit http://www.computer.org/tab/tttc/ % % If you would like to be removed from this mailing list, % please send an e-mail to % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% _______________________________________________________________ | 9th IEEE International Workshop on Rapid System Prototyping | --------------------------------------------------------------- Co-sponsored by IEEE Computer Society Technical Committees on: Design Automation, Simulation, Test Technology The IEEE International Workshop on Rapid System Prototyping (RSP) presents and explores the trends in rapid prototyping of Computer Based Systems including, but not limited to, communications, information, and manufacturing systems. The 9th annual workshop will focus on improved approaches to resolving prototyping issues and problems raised by incomplete specifications, increased system complexity and reduced time to market requirements for a multitude of products. The workshop will include a keynote presentation and formal paper sessions with a wide range of system prototyping topics including, but not limited to: - System Emulation - Virtual Prototyping - Hardware-Software Codesign - Tools for Hardware Prototyping - Tools for Software Prototyping - The Role of FPGAs in System Prototyping - Prototyping Case Studies - Very Large Scale System Engineering - Hardware/Software Tradeoffs - System Verification/Validation - Prototype to Product Transition - Prototyping of Real-Time Systems To get more information about the program or registration, please have a look on our web site: ------------------------------------------------------------------------ Marc Engels IMEC VSDM Tel.: +32-16-28.16.17 Kapeldreef 75 Fax.: +32-16-28.15.15 B-3001 Leuven e-mail: engelsm@imec.be Belgium www: http://www.imec.be/ ------------------------------------------------------------------------ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % Paolo PRINETTO % % IEEE Computer Society % Test Technology Technical Committee (Vice Chair) % % Politecnico di Torino % Dip. di Automatica e Informatica % Corso Duca degli Abruzzi 24 % I-10129 Torino TO % Italy % % Tel: + 39 11 564.7007 % Fax: + 39 11 564.7099 % % E-mail: Paolo.Prinetto@polito.it % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% From codesign-request@ifi.unizh.ch Mon Apr 27 10:43:30 1998 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <25947-0@josef.ifi.unizh.ch>; Mon, 27 Apr 1998 10:43:05 +0200 Return-Path: X-Received: from pol88b.polito.it by josef.ifi.unizh.ch with SMTP (PP) id <08332-0@josef.ifi.unizh.ch>; Sat, 25 Apr 1998 00:22:58 +0200 X-Received: from chiusella.polito.it.polito.it (chiusella.polito.it) by polito.it (PMDF V4.2-15 #3020) id <01IW9M40VQR48X4O6L@polito.it>; Sat, 25 Apr 1998 00:20:45 GMT+1 X-Received: by chiusella.polito.it.polito.it (4.1/SMI-4.1) id AA24600; Sat, 25 Apr 98 00:20:44 +0200 Date: Sat, 25 Apr 1998 00:20:44 +0200 From: tttc@chiusella.polito.it (Paolo Prinetto) Subject: IEEE TTTC - 3rd IEEE Int HLDVTW To: pilz@ifi.unizh.ch Message-id: <9804242220.AA24600@chiusella.polito.it.polito.it> X-Envelope-to: pilz@ifi.unizh.ch Content-transfer-encoding: 7BIT Apparently-To: PILZ Markus ReSent-Date: Mon, 27 Apr 1998 10:40:49 +0200 (MET DST) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 17 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % IEEE Computer Society % Test Technology Technical Committee % % % .... FOR YOUR INFORMATION.... % % A free service of the Technical Meeting Group % % % This message contains public information, only, and % the receiver is allowed, and invited, to copy it and % distribute it further. % % % For more information contact % or visit http://www.computer.org/tab/tttc/ % % If you would like to be removed from this mailing list, % please send an e-mail to % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 3rd IEEE International High Level Design Validation and Test Workshop http://www-cse.ucsd.edu/groups/hldvt Sheraton Grande Torrey Pines, La Jolla, California Nov. 12-14, 1998 Call For Participation The Third IEEE International High Level Design Validation and Test Workshop aims to stimulate research in test and validation methodolo- gies for ICs and systems specified using high level descriptions, where high level refers to register-transfer, behavioral, and system level specifications. The goal of the workshop is to provide an infor- mal forum, bringing together designers and test and verification researchers working in validating, debugging, and testing designs, in an effort to address high level design validation and test issues con- currently. Major topics include, but are not limited to, the follow- ing: High Level Design Validation Hardware/Software Co-Validation High Level Design Error Modeling High Level DFT/Synthesis for Test High Level Test Bench Generation High Level ATPG/Fault Simulation Testing Core Based Designs Validation of Microprocessors Hardware/Software Co-Testing Design Error Debug & Diagnosis The Program Committee invites authors to submit an extended summary comprising 1000 words describing original, unpublished recent work. Clearly describe the nature of the work, explain its significance, highlight novel features, and describe its current status. On the title page, please indicate: title, name and affiliations of all authors, and suggested topics. Also identify a contact author and include a complete mailing address, phone number, fax number and E- mail address. Panel proposals are also invited. Submit seven copies of proposals by mail or a Postscript version via E-mail. Submissions are due no later than July 15, 1998. Submit all paper proposals to: For general information, contact: Alex Orailoglu, Program Chair Sujit Dey, General Chair Dept. of Computer Science & Engr. Dept. of Electrical and Computer Engr. University of California, San Diego University of California, San Diego La Jolla, CA 92093-0114 La Jolla, CA 92093-0407 T: 619-534-0914, F: 619-534-7029 T: 619-534-0750, F: 619-534-0415 E-mail: alex@cs.ucsd.edu E-mail: dey@ece.ucsd.edu Authors will be notified of the disposition of their papers by September 4, 1998. The submission of a proposal will be considered evidence that upon acceptance the author(s) will present the paper at the workshop. Authors of accepted papers may submit a full version of their paper by October 5, 1998 for inclusion in an informal digest of papers, which will be distributed only to attendees of the workshop. The Third International High Level Design Validation and Test Workshop is sponsored by the IEEE Computer Society Test Technology Technical Committee and the IEEE Computer Society Design Automation Technical Committee. HLDVT'98 Steering Committee General Chair S. Dey UC San Diego Vice-General Chair P. Marwedel U. Dortmund Program Chair A. Orailoglu UC San Diego Finance Chair P. Varma Duet Technologies Inc. Publicity Chair R. Raina Motorola Inc. Panels Chair M. Fujita Fujitsu Labs Proceedings Chair V. Nagasamy VSIS, Inc. Local Arrangements Chair R. Gupta UC Irvine European Liaison B. Courtois TIMA Asian Liaison H. Yasuura Kyushu University Industry Liaison J-P. Masbou Intel Corp. Program Committee (to include) M. Abadir - Motorola Inc. J. Abraham - Univ. of Texas T. Ambler - Univ. of Texas A. Basu - Indian Institute of Tech., KGP R. Bergamaschi - IBM S. Bhatia - Duet Technologies F. Brglez - NCSU F. Catthoor - IMEC K-T. Cheng - UCSB H. Date - Kyushu Univ. D. Dill - Stanford Univ. J.P. Hayes - Univ. of Michigan J. Jess - Eindhoven Univ R. Karri - Lucent Bell Labs D. Ku - Escalade M. Lee - Avant! S. Leef - Mentor Graphics L. Lavagno - Politecnico di Torino J. Lu - National Semiconductor E.J. McCluskey - Stanford Univ. C. Papachristou - CWRU I. Pomeranz - Univ. of Iowa M. Potkonjak - UCLA P. Prinetto - Politecnico di Torino J. Rajski - Mentor Graphics W. Rosenstiel - Tuebingen Univ B. Rouzeyre - LIRMM R. Roy - Intel A. Takahara - NTT Y. Zorian - LogicVision %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % Paolo PRINETTO % % IEEE Computer Society % Test Technology Technical Committee (Vice Chair) % % Politecnico di Torino % Dip. di Automatica e Informatica % Corso Duca degli Abruzzi 24 % I-10129 Torino TO % Italy % % Tel: + 39 11 564.7007 % Fax: + 39 11 564.7099 % % E-mail: Paolo.Prinetto@polito.it % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% From codesign-request@ifi.unizh.ch Thu May 14 08:03:54 1998 Return-Path: Received: from susie.EECS.Berkeley.EDU by josef.ifi.unizh.ch with SMTP (PP) id <05388-0@josef.ifi.unizh.ch>; Wed, 13 May 1998 18:37:55 +0200 Received: from susie.EECS.Berkeley.EDU (localhost [127.0.0.1]) by susie.EECS.Berkeley.EDU (8.8.8/8.8.3) with SMTP id JAA18511; Wed, 13 May 1998 09:37:47 -0700 (PDT) Sender: tbassam@ic.eecs.berkeley.edu Message-ID: <3559CC55.4DAA@ic.eecs.berkeley.edu> Date: Wed, 13 May 1998 09:37:41 -0700 From: Bassam Tabbara Reply-To: tbassam@eecs.berkeley.edu Organization: UC Berkeley X-Mailer: Mozilla 3.01Gold (X11; I; OSF1 V4.0 alpha) MIME-Version: 1.0 Newsgroups: comp.arch.embedded,comp.cad.synthesis,comp.arch.fpga,comp.lsi.cad,sci.electronics.cad,comp.sys.6809,comp.sys.m68k,comp.soft-sys.ptolemy CC: Bassam Tabbara , codesign@ifi.unizh.ch, codesign@cadence.com, isss-people@ics.uci.edu, codesign@vhdl.org Subject: SRC TTC: Design of Embedded Systems: Models, Validation, and Synthesis Content-Type: multipart/mixed; boundary="------------6488773C6F59" Status: RO X-Status: X-Keywords: X-UID: 18 This is a multi-part message in MIME format. --------------6488773C6F59 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Employees of Semiconductor Research Corporation's participating member organizations are invited to attend: SRC's Technology Transfer Course Please circulate within SRC member companies (see http://www.src.org/about/roster.dgw for list). Design of Embedded Systems: Models, Validation, and Synthesis Location: University of California at Berkeley Date: June 11 (8AM-4:30PM) & June 12 (8AM-3PM) Contact Information: polis-tutorial@ic.eecs.berkeley.edu For more details please check: http://www-cad.eecs.berkeley.edu/~polis/announce.html Thank You. -The POLIS Team P.S. Apologies for duplicate copies of this announcement -- ____________________________________________________________________ Bassam Tabbara 211-150 Cory Hall EECS Department U.C. Berkeley Berkeley, CA 94720 Title: EECS Ph.D. Student Group: CAD (Hardware Software Co-design) Office: Cory Hall 550-B2 Phone: (510) 643-5187 Fax: (510) 643-5052 email: tbassam@ic.eecs.berkeley.edu tbassam@computer.org www: http://www.EECS.Berkeley.EDU/~tbassam ____________________________________________________________________ --------------6488773C6F59 Content-Type: text/plain; charset=us-ascii; name="announce.html" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="announce.html" Announcing SRC's Technology Transfer Course Please circulate within SRC member companies (see http://www.src.org/about/roster.dgw for list). Design of Embedded Systems: Models, Validation, and Synthesis Location: University of California at Berkeley Date: June 11 (8AM-4:30PM) & June 12 (8AM-3PM) Contact Information: polis-tutorial@ic.eecs.berkeley.edu Description This two-day tutorial covers several fundamental issues in the design of embedded real-time systems. Embedded real-time systems are ubiquitous in today's world, their numbers tend to increase exponentially. Yet the design methodology used is still based on older tools and practices designed with very different goals than those for embedded systems. The most important characteristic of these systems is the massive use of programmable components to achieve the design goals. Hence their design requires the use and optimization of both hardware and software. In this tutorial, we begin by outlining the revolution that is taking place in the electronic industry due to the advent of deep submicron and the continuing pressure on time-to-market. We present the notion of System Level Design, and IP-based design, and underline the challenges we will have to face. Then we focus on a top-down, constraint-driven design methodology that emphasizes the analysis and optimization of the top part of the design where all the important algorithmic and architectural decisions are taken, followed by design exploration, evaluation, iteration, and then final implementation. The framework for functional design, architecture selection, hardware-software co-design, software optimization, and real-time operating system design will be POLIS. We will use this environment developed at UC Berkeley to illustrate some of the key points of the design methodology. Participants will get a chance to see this methodology in action through hands-on lab sessions using the POLIS toolset. The course is aimed at two basic goals: 1. providing system designers with a practical perspective on new methodologies for hardware/software co-design of embedded controllers 2. exposing CAD engineers to the problems to be overcome in system design and presenting new algorithms and approaches to the solution of these problems It is preferable if attendees have some exposure to logic synthesis and simulation, but familiarity with digital design and basic CAD algorithms is sufficient. Tutorial material including lab handouts and solutions will be available to the attendees. The reference for this tutorial is the book written by the POLIS team: "Hardware-Software Co-Design of Embedded Systems: The POLIS Approach", by Felice Balarin, Massimiliano Chiodo, Paolo Giusto, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Claudio Passerone, Alberto Sangiovanni-Vincentelli, Ellen Sentovich, Kei Suzuki, and Bassam Tabbara, Kluwer Academic Publishers, MA, USA, May 1997. Course Plan Note: Lab sessions are marked with double asterix (**) Thursday June 11, 1998 08:00-08:30 Arrival and introduction 08:30-10:00 System Level and IP-based Design 10:00-10:30 Coffee Break 10:30-12:00 A Methodology for Hardware/Software Co-design of Embedded Systems 12:00-13:30 Lunch 13:30-15:00 POLIS: Design Entry, Specification, and Representation** 15:00-15:30 Coffee Break 15:30-16:30 POLIS: Partitioning, Estimation, Implementation, and Validation** 16:30 END Friday June 12, 1998 08:00-08:30 Arrival and Introduction 08:30-10:00 POLIS: Hardware and Software Synthesis** 10:00-10:30 Coffee Break 10:30-12:00 POLIS: Scheduling, RTOS, and Rapid Prototyping** 12:00-13:30 Lunch 13:30-15:00 Future Directions. Open discussions. 15:00 END Reminders: * Attendance is restricted to employees of Semiconductor Research Corporation's participating member organizations. Current full members and science area members are: AMD, Digital, Eastman Kodak, Harris, HP, IBM, Intel, LSI Logic, Lucent Technologies, Motorola, National Semiconductor, Northrop Grumman, TI, Cadence, Eaton, ETEC Systems, Mentor Graphics, Novellus, and Shipley. Please refer to www.src.org/about/roster.dgw for a complete list of participating member organizations. * The course will take place on the campus of the University of California at Berkeley on June 11 & 12. For the convenience of attendees, it has been scheduled in between two other conferences in the San Francisco Area, namely the Design Automation Conference June 15-19 (see www.dac.com), and IWLS (see http://domino.watson.ibm.com/IWLS98/IWLS98.nsf) Jun 8-10. * For registration information, please contact: polis-tutorial@ic.eecs.berkeley.edu --------------6488773C6F59-- From codesign-request@ifi.unizh.ch Thu May 14 16:50:16 1998 Return-Path: Received: from clavin.cs.tamu.edu by josef.ifi.unizh.ch with SMTP (PP) id <03510-0@josef.ifi.unizh.ch>; Thu, 14 May 1998 16:49:53 +0200 Received: from jetson.cs.tamu.edu (233@jetson [128.194.135.203]) by cs.tamu.edu (8.8.8/8.8.8) with ESMTP id JAA23328 for ; Thu, 14 May 1998 09:48:50 -0500 (CDT) From: Fabrizio Lombardi Received: (from lombardi@localhost) by jetson.cs.tamu.edu (8.8.8/8.8.8) id JAA04407 for codesign@ifi.unizh.ch; Thu, 14 May 1998 09:49:49 -0500 (CDT) Date: Thu, 14 May 1998 09:49:49 -0500 (CDT) Message-Id: <199805141449.JAA04407@jetson.cs.tamu.edu> To: codesign@ifi.unizh.ch Subject: CFP: Theme Issue DRAM ARCHITECTURE AND TESTING Status: RO X-Status: X-Keywords: X-UID: 19 CALL FOR PAPERS IEEE Design and Test of Computers Theme Issue on DRAM ARCHITECTURE AND TESTING Web Page: http://www.ee.ualberta.ca/ce/cockburn.html Guest Editors Bruce Cockburn, University of Alberta, cockburn@ee.ualberta.edu Fabrizio Lombardi, Texas A&M University, lombardi@cs.tamu.edu Jackie Meyer, Texas A&M University, fjmeyer@computer.org IEEE Design and Test of Computers seeks original manuscripts for a theme issue on architectural and testing aspects of Dynamic Random Access Memories (DRAMs), scheduled to appear in the first issue of 1999. Articles concerning applied research and practical experience reports are solicited. The topics of interest include, but are not limited to: EMBEDDED MEMORIES impact/developments/experiences in embedded macrocells, reconciling DRAM and logic requirements in a single process, logic-enhanced DRAMs, processors-in-memories, DRAMs embedded in ASICs, application-specific DRAMs (graphics, multimedia, communications, ...) TECHNOLOGY AND STANDARDS trends in storage cell technology, DRAM-specific processes, circuit design methodology, fuse technology, packaging, reliability, failure analysis, high-performance architectures, RAMBUS versus SLDRAM, impact/developments/experiences in standards, cache-enhanced DRAMs DESIGN timing system design, timing calibration, synchronous versus self-timing operation, pipelined design, static and dynamic redundancy, noise control, error correcting codes, multilevel DRAM, future trends REPAIR AND TEST fault models, failure mechanisms, repair algorithms, built-in self-repair, DRAM test design, design-for-testability, built-in self-test, parallel test strategies, automatic test equipment Submitted articles must not have been previously published or currently submitted for publication elsewhere. Notification of acceptance will be sent September 15, 1998. Submit articles by July 15, 1998 to: Bruce Cockburn, D&T Guest Editor Electrical and Computer Engineering 238 Civil/Electrical Building University of Alberta Edmonton Alberta, Canada T6G 2G7 Phone: (403)-492-3827 Fax: (403)-492-1811 Send six (6) copies of the manuscript, in English. Manuscripts are not to exceed 35 double-spaced pages, inclusive of figures and tables, in A4 or 8.5 by 11 inches. Type size must be at least 12 point. Each copy must contain a cover page with author contact information and a 100-word abstract. Manuscripts must be cleared for publication. From codesign-request@ifi.unizh.ch Sun May 17 14:55:22 1998 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <16342-0@josef.ifi.unizh.ch>; Sun, 17 May 1998 14:55:10 +0200 Return-Path: X-Received: from pol88b.polito.it by josef.ifi.unizh.ch with SMTP (PP) id <16163-0@josef.ifi.unizh.ch>; Sun, 17 May 1998 14:17:39 +0200 X-Received: from chiusella.polito.it.polito.it (chiusella.polito.it) by polito.it (PMDF V4.2-15 #3020) id <01IX55I76R9S8WW5FS@polito.it>; Sun, 17 May 1998 14:11:09 GMT+1 X-Received: by chiusella.polito.it.polito.it (4.1/SMI-4.1) id AA05764; Sun, 17 May 98 14:11:09 +0200 Date: Sun, 17 May 1998 14:11:09 +0200 From: tttc@chiusella.polito.it (Paolo Prinetto) Subject: IEEE TTTC - Testing Embedded Core-based Systems. To: pilz@ifi.unizh.ch Message-id: <9805171211.AA05764@chiusella.polito.it.polito.it> X-Envelope-to: pilz@ifi.unizh.ch Content-transfer-encoding: 7BIT Apparently-To: PILZ Markus ReSent-Date: Sun, 17 May 1998 14:52:55 +0200 (MET DST) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 20 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % IEEE Computer Society % Test Technology Technical Committee % % % .... FOR YOUR INFORMATION.... % % A free service of the Technical Meeting Group % % % This message contains public information, only, and % the receiver is allowed, and invited, to copy it and % distribute it further. % % % For more information contact % or visit http://www.computer.org/tab/tttc/ % % If you would like to be removed from this mailing list, % please send an e-mail to % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% ********************************************************************* 2nd IEEE International Workshop on Testing Embedded Core-based Systems ********************************************************************* Marriott Wardman Park Hotel, Washington, D.C. October, 22-23, 1998 ********************************************************************* CALL FOR PAPERS Embedded cores, or pre-designed Intellectual Property (IP) blocks, are finding growing use in microelectronic system-chips. The increase in design reuse, that core-based systems make possible, adds to the complexity of testing the complete system-chips and even portions of it. TECS 98 is the workshop that dedicates its program to the state-of-the-art practices and emerging trends of testing embedded core-based system-chips. It brings together core creators, integrators and manufacturers while providing an informal forum for presenting and discussing the new developments in testing such systems. The topics of interest include, but are not limited to, the following: . Automatic Test Generation for System-Chips . BIST for System-Chips . Core-level BIST . Debug and diagnosis for IP Cores . Design-for-Testability for Embedded Cores . Fault Modeling and Simulation . Synthesis for Testability . Test Control and Access for Embedded Cores . Verification and Validation for embedded IPs To present at the Workshop, authors are invited to submit paper proposals. The proposals may be extended abstracts (1000 words) or full papers. Each submission should include: title, full name and affiliation of all authors, an abstract of 50 words, and keywords. Also, identify a contact author and include a complete correspondence address, phone number, fax number, and E-mail address. Submit 6 copies of your paper proposals by mail or Postscript version via E-mail. Proposals for panel discussions are also invited. Submissions are due no later than June 22nd, 1998. Submit your paper proposal to: Yervant Zorian, LogicVision, 101 Metro Dr, Third Floor, San Jose 95110, USA T: 408-453-0146, F: 408-573-0757, Email: zorian@lvision.com Authors will be notified of the disposition of their papers by Aug. 25th, 1998. Authors of accepted papers may submit an illustrated text Sept. 25th for inclusion in the Digest of Papers, which will be provided to the attendees. A selected set of papers from TECS 98 will be considered for inclusion in a forthcoming special issue on testing core-based system-chips. TECS 98 is sponsored by the IEEE Computer Society Test Technology Technical Committee (TTTC) and in cooperation with VSIA - The Virtual Socket Interface Alliance. It is produced in conjunction with Test Week 98 and the International Test Conference (for more information: www.itctestweek.org). IEEE TECS 1474 Freeman Dr. Amissville, VA 20106 Tel: +1-540-937-8280, Fax: +1-540-937-3739 Email: tttc@computer.org http://www.computer.org/tab/tttc/meetings/tecs/home.html ********************************************************************** GENERAL CHAIR Y. Zorian, LogicVision zorian@lvision.com FINANCE R. Chandramouli, Synopsys mouli@synopsys.com INDUSTRIAL LIAISON K. Wagner, S3 kwagner@s3.com ARRANGEMENTS E.J. Marinissen, Philips marinis@natlab.research.philips.com REGISTRATION R. Rajsuman, Advantest rrajsuman@advantest.com PUBLICITY B. Courtois, TIMA Bernard.Courtois@imag.fr A. Hales, Texas Instruments alanh@ti.com PUBLICATION S. Dey, NEC USA dey@ccrl.nj.nec.com PANELS J. Beausang, Synopsys jamesb@sysnopsys.com ********************************************************************** PROGRAM COMMITTEE (to include) R. Aitken, Hewlett-Packard J. Alt, Siemens T. Anderson, Phoenix S. Barbagallo, Italtel D. Bhavsar, DEC D. Burek, LogicVision G. Carlsson, Ericsson S. Chung, Cisco C.J. Clark, Intellitech S. Davidson, Sun T. Eberle, Mentor Graphics R. Garcia, Schlumberger G. Giles, Motorola D. Gizopoulos, NCSR Demokritos R. Gupta, Univ of Cal Irvine S. Hemmady, Guru Technologies J.P. Hayes, Univ. of Michigan I. Kim, Lucent Technologies B. Koenemann, LogicVision C. Mallipeddi, Cadence E.J. McCluskey, Stanford Univ J. Monzel, IBM S. Mukherjee, Fujitsu F. Muradali, Hewlett-Packard M. Nicolaidis, TIMA A. Orailoglu, Univ Cal San Diego C. Papachristou, Case Western Reserve I. Pomeranz, Univ of Iowa P. Prinetto, Politecnico di Torino J. Rajski, Mentor Graphics M. Renovell, LIRMM G. Robinson, Credence R. Roy, Intel R. Segers, Philips M. Spadari, LSI Logic E. de la Torre, Univ. Poli Madrid J. Udell, PalmChip P. Varma, DuetTechnologies L. Whetsel, Texas Instruments T. Williams, Synopsys ************************************************************************ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % Paolo PRINETTO % % IEEE Computer Society % Test Technology Technical Committee (Vice Chair) % % Politecnico di Torino % Dip. di Automatica e Informatica % Corso Duca degli Abruzzi 24 % I-10129 Torino TO % Italy % % Tel: + 39 11 564.7007 % Fax: + 39 11 564.7099 % % E-mail: Paolo.Prinetto@polito.it % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% From codesign-request@ifi.unizh.ch Fri May 22 10:42:25 1998 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <19054-0@josef.ifi.unizh.ch>; Fri, 22 May 1998 10:42:16 +0200 Return-Path: X-Received: from susie.EECS.Berkeley.EDU by josef.ifi.unizh.ch with SMTP (PP) id <13659-0@josef.ifi.unizh.ch>; Fri, 22 May 1998 02:30:40 +0200 X-Received: from susie.EECS.Berkeley.EDU (localhost [127.0.0.1]) by susie.EECS.Berkeley.EDU (8.8.8/8.8.3) with SMTP id RAA17313; Thu, 21 May 1998 17:30:24 -0700 (PDT) Sender: tbassam@ic.eecs.berkeley.edu Message-ID: <3564C70C.41C6@ic.eecs.berkeley.edu> Date: Thu, 21 May 1998 17:30:04 -0700 From: Bassam Tabbara Organization: UC Berkeley X-Mailer: Mozilla 3.01Gold (X11; I; OSF1 V4.0 alpha) MIME-Version: 1.0 Newsgroups: comp.arch.embedded,comp.cad.synthesis,comp.arch.fpga,comp.lsi.cad,sci.electronics.cad,comp.sys.m6809,comp.sys.m68k,comp.soft-sys.ptolemy CC: Bassam Tabbara , Harry Hsieh , codesign@ifi.unizh.ch, codesign@cadence.com, isss-people@ics.uci.edu, codesign@vhdl.org Subject: 2nd announcement, SRC TTC: Design of Embedded Systems Content-Type: multipart/mixed; boundary="------------167E2781446B" ReSent-Date: Fri, 22 May 1998 10:39:54 +0200 (MET DST) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 21 This is a multi-part message in MIME format. --------------167E2781446B Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Employees of Semiconductor Research Corporation's participating member organizations are invited to attend: SRC's Technology Transfer Course Please circulate within SRC member companies (see http://www.src.org/about/roster.dgw for list). Design of Embedded Systems: Models, Validation, and Synthesis Location: University of California at Berkeley Date: June 11 (8AM-4:30PM) & June 12 (8AM-3PM) Contact Information: polis-tutorial@ic.eecs.berkeley.edu For more details please check: http://www-cad.eecs.berkeley.edu/~polis/announce.html -- ____________________________________________________________________ Bassam Tabbara 211-150 Cory Hall EECS Department U.C. Berkeley Berkeley, CA 94720 Title: EECS Ph.D. Student Group: CAD (Hardware Software Co-design) Office: Cory Hall 550-B2 Phone: (510) 643-5187 Fax: (510) 643-5052 email: tbassam@ic.eecs.berkeley.edu tbassam@computer.org www: http://www.EECS.Berkeley.EDU/~tbassam ____________________________________________________________________ --------------167E2781446B Content-Type: text/html; charset=us-ascii; name="announce.html" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="announce.html" Content-Base: "http://www-cad.eecs.berkeley.edu/~poli s/announce.html" Course on Embedded System Design

    Announcing

    SRC's Technology Transfer Course

    Please circulate within SRC member companies (see http://www.src.org/about/roster.dgw  for list).

     

    Design of Embedded Systems: Models, Validation, and Synthesis

     
    Location:  University of California at Berkeley
    Date:  June 11 (8AM-4:30PM) & June 12 (8AM-3PM)
    Contact Information: polis-tutorial@ic.eecs.berkeley.edu

    Description

    This two-day tutorial covers several fundamental issues in the design of embedded real-time systems. Embedded real-time systems are ubiquitous in today's world, their numbers tend to increase exponentially. Yet the design methodology used is still based on older tools and practices designed with very different goals than those for embedded systems. The most important characteristic of these systems is the massive use of programmable components to achieve the design goals. Hence their design requires the use and optimization of both hardware and software.


    In this tutorial, we begin by outlining the revolution that is taking place in the electronic industry due to the advent of deep submicron and the continuing pressure on time-to-market. We present the notion of System Level Design, and IP-based design, and underline the challenges we will have to face. Then we focus on a top-down, constraint-driven design methodology that emphasizes the analysis and optimization of the top part of the design where all the important algorithmic and architectural decisions are taken, followed by design exploration, evaluation, iteration, and then final implementation.


    The framework for functional design, architecture selection, hardware-software co-design, software optimization, and real-time operating system design will be POLIS. We will use this environment developed at UC Berkeley to illustrate some of the key points of the design methodology. Participants will get a chance to see this methodology in action through hands-on lab sessions using the POLIS toolset.


    The course is aimed at two basic goals:


    1. providing system designers with a practical perspective on new methodologies for hardware/software co-design of embedded controllers
    2. exposing CAD engineers to the problems to be overcome in system design and presenting new algorithms and approaches to the solution of these problems

    It is preferable if attendees have some exposure to logic synthesis and simulation, but familiarity with digital design and basic CAD algorithms is sufficient.


    Tutorial material including lab handouts and solutions will be available to the attendees. The reference for this tutorial is the book written by the POLIS team:


      "Hardware-Software Co-Design of Embedded Systems: The POLIS Approach", by Felice Balarin, Massimiliano Chiodo, Paolo Giusto, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Claudio Passerone, Alberto Sangiovanni-Vincentelli, Ellen Sentovich, Kei Suzuki, and Bassam Tabbara, Kluwer Academic Publishers, MA, USA, May 1997.

    Course Plan

    Note: Lab sessions are marked with double asterix (**)

    Thursday June 11, 1998


    08:00-08:30 Arrival and introduction
    08:30-10:00 System Level and IP-based Design
    10:00-10:30 Coffee Break
    10:30-12:00 A Methodology for Hardware/Software Co-design of Embedded Systems
    12:00-13:30 Lunch
    13:30-15:00 POLIS: Design Entry, Specification, and Representation**
    15:00-15:30 Coffee Break
    15:30-16:30 POLIS: Partitioning, Estimation, Implementation, and Validation**
    16:30 END


    Friday June 12, 1998


    08:00-08:30 Arrival and Introduction
    08:30-10:00 POLIS: Hardware and Software Synthesis**
    10:00-10:30 Coffee Break
    10:30-12:00 POLIS: Scheduling, RTOS, and Rapid Prototyping**
    12:00-13:30 Lunch
    13:30-15:00 Future Directions. Open discussions.
    15:00 END
Reminders:
  • Attendance is restricted to employees of Semiconductor Research Corporation's participating member organizations. Current full members and science area members are: AMD, Digital, Eastman Kodak, Harris, HP, IBM, Intel, LSI Logic, Lucent Technologies, Motorola, National Semiconductor, Northrop Grumman, TI, Cadence, Eaton, ETEC Systems, Mentor Graphics, Novellus, and Shipley. Please refer to www.src.org/about/roster.dgw for a complete list of participating member organizations.
--------------167E2781446B-- From codesign-request@ifi.unizh.ch Thu Jun 4 12:13:30 1998 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <01434-0@josef.ifi.unizh.ch>; Thu, 4 Jun 1998 12:13:17 +0200 Return-Path: X-Received: from epsilon.ece.nwu.edu by josef.ifi.unizh.ch with SMTP (PP) id <15538-0@josef.ifi.unizh.ch>; Tue, 2 Jun 1998 21:56:24 +0200 X-Received: (from daemon@localhost) by epsilon.ece.nwu.edu (8.8.5/8.8.3) id JAA03618 for ; Tue, 2 Jun 1998 09:17:11 -0500 (CDT) X-Received: from seattle.ece.nwu.edu(129.105.5.174) by epsilon.ece.nwu.edu via smap (V2.0beta) id xma003612; Tue, 2 Jun 98 09:17:02 -0500 X-Received: (from hauck@localhost) by seattle.ece.nwu.edu (8.8.5/8.8.3) id JAA08821 for fpga97; Tue, 2 Jun 1998 09:17:01 -0500 (CDT) Date: Tue, 2 Jun 1998 09:17:01 -0500 (CDT) From: Scott Alan Hauck Message-Id: <199806021417.JAA08821@seattle.ece.nwu.edu> To: fpga97@seattle.ece.nwu.edu Subject: FPGA'99 Call for Participation ReSent-Date: Thu, 4 Jun 1998 12:10:40 +0200 (MET DST) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 22 FPGA `99: Call for Papers Seventh ACM International Symposium on Field-Programmable Gate Arrays DoubleTree Hotel, Monterey, California February 21-23, 1999 As we reach the end of the 1990s, rapidly increasing speed and capacity have made FPGAs a standard implementation target for digital logic. Advancements in FPGA architectures proceeds unabated, and larger, faster devices enable new, innovative applications that continue to stress designers and their tools. For FPGA `99, we are soliciting submissions describing novel research and development in the following (and related) areas of interest: FPGA Architecture: Logic block & routing architectures, I/O structures and circuits, new commercial architectures, Field-Programmable Interconnect Chips and Devices (FPIC/FPID), Field-Programmable Analog Arrays (FPAA). CAD for FPGAs: Placement, routing, logic optimization, technology mapping, system-level partitioning, logic generators, testing and verification. CAD for FPGA-based accelerators. Interactions: between CAD, architecture, applications, and programming technology. Applications: Innovative use of FPGAs, exploitation of FPGA features, novel circuits, high-performance and low-power/mission-critical applications, DSP techniques, uses of reconfiguration, FPGA-based cores. FPGA-based computing engines: Compiled accelerators, reconfigurable computing, adaptive computing devices, systems and software. Fast prototyping for system level design, Multi-Chip Modules (MCMs), logic emulation. Authors are invited to submit PDF (preferred) or postscript of their paper (12 pages maximum) by October 2, 1998 via E-mail to fpga99@xilinx.com. Alternatively, authors may submit a 3.5" floppy disk containing the pdf or postscript file or 22 copies of their paper to the program chair. Notification of acceptance will be sent by December 1, 1998. The authors of the accepted papers will be required to submit the final camera-ready copy by December 15, 1998. A proceedings of the accepted papers will be published by ACM, and included in the Annual ACM/SIGDA CD-ROM Compendium publication. Address questions to: Steve Trimberger Program Chair, FPGA `99 Xilinx, Inc. 2100 Logic Dr. San Jose, CA 95124-3450 USA phone: (408) 879-5061 fax: (408) 559-7114 fpga99@xilinx.com General Chair: Sinan Kaptanoglu, Actel Finance Chair: Jason Cong, UCLA Program Chair: Steve Trimberger, Xilinx Publicity Chair: Scott Hauck, Northwestern U. Program Committee Om Agrawal, Vantis Ray Andraka, Andraka Consulting Michael Butts, Quickturn Jason Cong, UCLA Eugene Ding, Lucent Carl Ebeling, U. of Washington Scott Hauck, Northwestern U. Brad Hutchings, BYU Sinan Kaptanoglu, Actel David Lewis, U. of Toronto Fabrizio Lombardi, Texas A&M Wayne Luk, Imperial College Margaret Marek-Sadowska, UCSB Peter Moceyunas, Synopsys Jonathan Rose, U. of Toronto Gabriele Saucier, INPG Martine Schlag, UCSC Herman Schmit, CMU Tim Southgate, Altera Steve Trimberger, Xilinx John Wawrzynek, UCB Martin Wong, UT at Austin Sponsored by ACM SIGDA, with support from Xilinx, Altera, Lucent and Actel. Please visit for more information. From codesign-request@ifi.unizh.ch Fri Jun 26 09:50:31 1998 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <27241-0@josef.ifi.unizh.ch>; Fri, 26 Jun 1998 09:50:15 +0200 Return-Path: X-Received: from babbage.ececs.uc.edu by josef.ifi.unizh.ch with SMTP (PP) id <23592-0@josef.ifi.unizh.ch>; Fri, 26 Jun 1998 05:23:56 +0200 X-Received: from ececs.uc.edu (ravel.ececs.uc.edu [129.137.9.16]) by babbage.ececs.uc.edu (8.8.7/8.8.7) with ESMTP id XAA17001 for ; Thu, 25 Jun 1998 23:23:48 -0400 (EDT) Message-ID: <359313F5.BB609010@ececs.uc.edu> Date: Thu, 25 Jun 1998 23:22:30 -0400 From: Eric Donkoh Organization: University of Cincinnati X-Mailer: Mozilla 4.04 [en] (WinNT; I) MIME-Version: 1.0 To: codesign-request@ifi.unizh.ch Subject: BENCHMARKS ON HW/SW PARTITION Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit ReSent-Date: Fri, 26 Jun 1998 09:47:29 +0200 (MET DST) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 23 Hi I'm looking for benchmarks on hw/sw partition for evaluation purpose. I will appreciate if anyone can help me thanks Eric -- From jbuck@Synopsys.COM Fri Jun 26 18:51:40 1998 Return-Path: Received: from hamachi.synopsys.com by josef.ifi.unizh.ch with SMTP (PP) id <12837-0@josef.ifi.unizh.ch>; Fri, 26 Jun 1998 18:51:38 +0200 Received: from marathon.synopsys.com (marathon.synopsys.com [146.225.100.41]) by hamachi.synopsys.com (8.8.8/8.8.5) with ESMTP id JAA19007; Fri, 26 Jun 1998 09:51:08 -0700 (PDT) Received: from atrus.synopsys.com (atrus.synopsys.com [146.225.121.23]) by marathon.synopsys.com (8.8.8/8.8.8) with SMTP id JAA17250; Fri, 26 Jun 1998 09:50:41 -0700 (PDT) From: Joe Buck Received: by atrus.synopsys.com (SMI-8.6/SNPS-Sol2) id JAA22132; Fri, 26 Jun 1998 09:50:41 -0700 Message-Id: <199806261650.JAA22132@atrus.synopsys.com> Subject: Re: BENCHMARKS ON HW/SW PARTITION To: edonkoh@ececs.uc.edu (Eric Donkoh) Date: Fri, 26 Jun 98 9:50:41 PDT Cc: codesign-request@ifi.unizh.ch In-Reply-To: <359313F5.BB609010@ececs.uc.edu>; from "Eric Donkoh" at Jun 25, 98 11:22 pm X-Mailer: ELM [version 2.3 PL11] Status: RO X-Status: X-Keywords: X-UID: 24 > Hi I'm looking for benchmarks on hw/sw partition for evaluation purpose. > I will appreciate if anyone can help me Thanks for giving me an opening for engaging in one of my favorite rants once more. The problem with such benchmarks is that they attempt to quantify something that is often not quantifiable, and even when there are measures, there are so many different characteristics that can be optimized that comparison is difficult. Yes, in some cases it is possible to map the problem into the heterogeneous multiprocessor scheduling problem -- given: a discrete set of tasks that communicate in CSP style, a set of possible mappings to hardware or software, a set of contraints and a set of costs, find the minimal cost that satisfies the constraints. If the cost function has the correct (unrealistic) structure, you have an integer linear programming problem. Researchers who want to try new algorithms for attacking this ILP problem may be making a useful contribution, but they should not delude themselves into thinking that they are doing hardware/software codesign. This formulation does have the virtue that standard cases can be published and researchers can compete to see who has the best algorithm. But I don't believe that it really solves the problems that systems designers are facing. The reason is that the *real* codesign problem is far more complex: * the constraints are often difficult to quantify and have more to do with stability of algorithms and future plans (e.g. put this in software because we expect to require late changes, etc) than just area and speed. * the true cost functions, especially for the hardware mapping, are often not linear unless the designer is willing to sacrifice optimization: sequential don't-care based optimization can often remove lots of logic and we can do it if we know what talks to what. Now, there are certain cases where this kind of approach (automatic partitioning to satisfy constraints and minimize cost) does make sense: if you really do have a fixed architecture that you are mapping to (processors, ASIPs, and hard cores with a bus structure) and you're willing to accept any mapping, the ILP formulation may be a completely reasonable approach. But this case is a small subset of hw/sw codesign. From codesign-request@ifi.unizh.ch Wed Jul 8 10:46:25 1998 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <05074-0@josef.ifi.unizh.ch>; Wed, 8 Jul 1998 10:46:12 +0200 Return-Path: X-Received: from mailserver1.hrz.tu-darmstadt.de by josef.ifi.unizh.ch with SMTP (PP) id <03719-0@josef.ifi.unizh.ch>; Wed, 8 Jul 1998 10:06:09 +0200 X-Received: from mes.tu-darmstadt.de (adonix.microelectronic.e-technik.tu-darmstadt.de [130.83.30.1]) by mailserver1.hrz.tu-darmstadt.de (8.6.12/8.6.12.1ms) with ESMTP id KAA08513 for ; Wed, 8 Jul 1998 10:05:14 +0200 X-Received: from gutemine.mes.th-darmstadt.de by mes.tu-darmstadt.de (SMI-8.6/SMI-SVR4) id KAA07363; Wed, 8 Jul 1998 10:05:13 +0200 X-Received: by gutemine.mes.th-darmstadt.de (SMI-8.6/SMI-SVR4) id KAA23708; Wed, 8 Jul 1998 10:05:13 +0200 Date: Wed, 8 Jul 1998 10:05:13 +0200 Message-Id: <199807080805.KAA23708@gutemine.mes.th-darmstadt.de> From: noreply@mes.tu-darmstadt.de Subject: Call for participation Content-Type: text Apparently-To: pilz@ifi.unizh.ch ReSent-Date: Wed, 8 Jul 1998 10:37:06 +0200 (MET DST) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 25 Please find enclosed call for papers and participation for your information, as well as for distribution among interested colleagues. Sorry for receiving multiple copies of this call. If you have any questions, don`t hesitate to contact me. (EMail: becker@mes.tu-darmstadt.de) Thanks and best regards, Juergen Becker --------------------------------------------------------------------------- PACT 98 WORKSHOP October 13th (Paris, France) ON RECONFIGURABLE COMPUTING Chair: Nader Bagherzadeh, UC, Irvine ECE Department Irvine, CA 92697 nader@ece.uci.edu Workshop Committee Members: Juergen Becker, Darmstadt University of Technology W. Bohm, Colorado State University Catherine Dezan, Universite de Bretagne Occidentale Gordon Brebner, University of Edinburgh J. L. Gaudiot, USC Reiner Hartenstein, University of Kaiserslautern Fadi Kurdahi, UC, Irvine Shahram Latifi, UNLV Fabrizio Lombardi, Texas A&M Wayne Luk, Imperial College Walid Najjar, Colorado State University In recent years there has been a growing interest in using Field Programmable Gate Arrays (FPGA) for the design of future computer systems. These systems utilize the flexibility of FPGA chips to optimize the hardware configuration available on the system for efficient utilization of resources on a given application. An important related issue to this trend is the use of FPGA circuit technology to enhance the design of future computer systems. In particular, researchers are seeking new architectural paradigms to integrate the notion of reconfigurable systems into the design of general-purpose microprocessors. Past research in this area has identified great potential for enhancing performance and reducing power for certain applications. The focus of this workshop is to identify the software and hardware techniques necessary for pursuing reconfigurable computing as a viable alternative to future models of computation. Topics of interest include, but not limited to: - Software support for reconfigurable computers - Algorithms for mapping applications onto reconfigurable platforms - Reconfigurable block architecture - HW/SW co-design approaches. - Circuit design technology - Experimental results and applications - Computation models supporting reconfigurable architectures - Reconfigurable computing versus general purpose computing - Reconfigurable computing versus ASIC design Submission Information: Electronic submission of an extended abstract (6 pages or less in .doc or .ps format) to the workshop Chair before August 25th, 1998. Acceptance notification will be mailed by Sep 10th, 1998. From pilz@ifi.unizh.ch Mon Jul 13 09:26:19 1998 +0200 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <01119-0@josef.ifi.unizh.ch>; Mon, 13 Jul 1998 09:26:06 +0200 Return-Path: X-Received: from pol88b.polito.it by josef.ifi.unizh.ch with SMTP (PP) id <27997-0@josef.ifi.unizh.ch>; Sun, 12 Jul 1998 21:00:28 +0200 X-Received: from chiusella.polito.it.polito.it (chiusella.polito.it) by polito.it (PMDF V4.2-15 #3020) id <01IZBRP07EJK8X2MOC@polito.it>; Sun, 12 Jul 1998 20:48:22 GMT+1 X-Received: by chiusella.polito.it.polito.it (4.1/SMI-4.1) id AA27193; Sun, 12 Jul 98 20:48:21 +0200 Date: Sun, 12 Jul 1998 20:48:21 +0200 From: tttc@chiusella.polito.it (Paolo Prinetto) Subject: IEEE TTTC - DATE'99: Design, Automation and Test in Europe To: pilz@ifi.unizh.ch Message-id: <9807121848.AA27193@chiusella.polito.it.polito.it> X-Envelope-to: pilz@ifi.unizh.ch Content-transfer-encoding: 7BIT Apparently-To: PILZ Markus ReSent-Date: Mon, 13 Jul 1998 09:23:07 +0200 (MET DST) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: IEEE TTTC - DATE'99: Design, Automation and Test in Europe ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 26 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % IEEE Computer Society % Test Technology Technical Committee % % % .... FOR YOUR INFORMATION.... % % A free service of the Technical Meeting Group % % % This message contains public information, only, and % the receiver is allowed, and invited, to copy it and % distribute it further. % % % For more information contact % or visit http://www.computer.org/tab/tttc/ % % If you would like to be removed from this mailing list, % please send an e-mail to % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% DATE'99: Design, Automation and Test in Europe ------------------------------------- Conference and Exhibition International Congress Center, Munich, Germany 9 - 12 March 1999 The Event --------- DATE is the single unified event bringing together researchers, users and vendors in the field of electronic systems design engineering in Europe. It results from the merger, in 1998, of ED&TC and Euro-DAC. Submission DEADLINE: September 19, 1998 --------------------------------------- Two categories of papers are distinguished: R Papers - Full-length papers intended for the IEEE Main Proceedings. S Papers - Extended summaries intended for the User's Proceedings Areas of Interest ----------------- * A Design Methodologies and Experience. Emphasis is on challenges and experiences in the design of advanced electronic components and systems, not only to obtain user feedback on existing design methods and tools but also to initiate discussions on requirements of future design flows and environments. * B CAD Languages, Algorithms and Tools. Design automation and design tools for electronic products. Emphasis is on methods and tools related to the use of computers in designing products. This includes fully automatic as well as computer assisted methods, data and design management techniques and user interfaces. * C Test & Testing of electronic products. This includes testing of digital, mixed digital/analogue and analogue circuits and systems, test program development, test systems and design for testability. Informations ------------ For detailed list of topics, submission procedure and up-to-date informations see: http://www.date-conference.com/ or write to: sue.menzies@ec.u-net.com %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % Paolo PRINETTO % % IEEE Computer Society % Test Technology Technical Committee (Vice Chair) % % Politecnico di Torino % Dip. di Automatica e Informatica % Corso Duca degli Abruzzi 24 % I-10129 Torino TO % Italy % % Tel: + 39 11 564.7007 % Fax: + 39 11 564.7099 % % E-mail: Paolo.Prinetto@polito.it % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% From pilz@ifi.unizh.ch Tue Jul 14 12:49:40 1998 +0200 Return-Path: Received: from bree.teisa.unican.es by josef.ifi.unizh.ch with SMTP (PP) id <15399-0@josef.ifi.unizh.ch>; Tue, 14 Jul 1998 12:49:09 +0200 Received: from villar.teisa.unican.es (villar [193.144.187.5]) by bree.teisa.unican.es (8.8.5/8.8.5) with SMTP id LAA02903; Tue, 14 Jul 1998 11:36:30 +0100 (WET DST) Message-Id: <2.2.32.19980714093607.006a65f8@bree.teisa.unican.es> X-Sender: villar@bree.teisa.unican.es X-Mailer: Windows Eudora Pro Version 2.2 (32) Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Date: Tue, 14 Jul 1998 11:36:07 +0200 To: sddl@vhdl.org, hdlcon@vhdl.org, vital@vhdl.org, codesign@vhdl.org, vhdlsynth@vhdl.org, ieee-dasc@vhdl.org, siwg@vhdl.org, 1076-1@epfl.ch, verilog@cds3075.Cadence.COM, verilog-a@cds3075.Cadence.COM, mhdl@nosc.mil, isss-people@ics.uci.edu, codesign@ifi.unizh.ch, sig-vhdl@cefriel.it, arch@ovi.org, dcwg@vhdl.org, vlog-synth@eda.org, 1364core@ovi.org, 1364@ovi.org, stds-dasc@eda.org, viuf-all@vhdl.org, cenelec-tc217wg2@epfl.ch, vhdlpli@vhdl.org From: villar@teisa.unican.es Subject: DATE'99 Call for papers Status: RO X-Status: X-Keywords: X-UID: 27 ________________________________________________________________ Sorry if you receive this message more than one. This is because you participate to several distribution lists. This message is to invite you to submit your last research results and design experiences on Standard Design Languages to Topic B8: ---------------------------------------------------------------- B8. Standard Design Languages VHDL/VHDL-AMS and Verilog/Verilog-A design techniques; practical use of VHDL-AMS and Verilog-A; application studies of standard design languages; analysis and effective use of new extensions and subsets of the VHDL and Verilog standards; VHDL and Verilog interoperability in design projects and design tools; standard design languages for IP-based design; standard system-level design languages and SLDL standardization. ---------------------------------------------------------------- of the Design, Automation & Test in Europe (DATE'99) Conference to be held in Munich, Germany, 9-12 of March, 1999. Deadline for paper submission is: September 19, 1998 For additional information about the conference and instructions to authors, have a look to http://www.date-conference.com *************************************************************** Eugenio Villar Microelectronics Engineering Group Tel. 34 42 201398 E.T.S.I.Industriales y Telecom. Fax. 34 42 201873 University of Cantabria email. villar@teisa.unican.es Avda. Los Castros s/n, 39005 Santander, Spain *************************************************************** From pilz@ifi.unizh.ch Wed Jul 15 14:42:49 1998 +0200 Return-Path: Received: from sicmail.epfl.ch by josef.ifi.unizh.ch with SMTP (PP) id <15561-0@josef.ifi.unizh.ch>; Wed, 15 Jul 1998 14:42:38 +0200 Received: from [128.178.19.189] (actually c3imac17.epfl.ch) by sicmail with SMTP (local); Wed, 15 Jul 1998 14:41:53 +0200 Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" X-Sender: vachoux@c3i9.epfl.ch Message-Id: Date: Wed, 15 Jul 1998 14:41:57 +0200 To: sddl@vhdl.org, hdlcon@vhdl.org, vital@vhdl.org, codesign@vhdl.org, vhdlsynth@vhdl.org, ieee-dasc@vhdl.org, siwg@vhdl.org, 1076-1@epfl.ch, verilog@cds3075.Cadence.COM, verilog-a@cds3075.Cadence.COM, mhdl@nosc.mil, isss-people@ics.uci.edu, codesign@ifi.unizh.ch, sig-vhdl@cefriel.it, arch@ovi.org, dcwg@vhdl.org, vlog-synth@eda.org, 1364core@ovi.org, 1364@ovi.org, stds-dasc@eda.org, viuf-all@vhdl.org, cenelec-tc217wg2@epfl.ch, vhdlpli@vhdl.org From: Alain Vachoux Subject: FDL'98 Invitation Status: RO X-Status: X-Keywords: X-UID: 28 ******************************************************************************* * We apologize, if you receive this message more than once. This is because * you participate to several distribution lists. * This message contains public information, and the receiver is allowed and * invited to copy it and distribute it further. ******************************************************************************* It is my pleasure to invite you to the: First International Forum on Design Languages (FDL'98) September 6-11, 1998 Swiss Federal Institute of Technology, Lausanne, Switzerland A complete information on FDL'98 is available at http://c3iwww.epfl.ch/fdl98/. FDL'98 is the first occurrence of a new international forum to exchange experiences and to learn on new efforts and trends in the application of languages (e.g., VHDL and Verilog HDL) in the design of electronic and non electronic systems. The following areas will be covered: - System design (including hardware-software co-design) - Design validation and test - Design synthesis - Component modeling - Design reuse - International standardization (IEEE, VSIA) - System level design languages In addition, several high-quality tutorials and practical hands-on labs on commercial and academic tools will be provided. To register, fill the registration form available from the web. For more information, please contact: Sophie Lazarevic FDL'98 Secretary EPFL-DE-C3i Phone: +41 21 693 6990 Fax : +41 21 693 4735 mailto:sophie.lazarevic@epfl.ch Alain Vachoux FDL'98 General Chair EPFL-DE-C3i Phone: +41 21 693 6984 Fax : +41 21 693 4663 mailto:alain.vachoux@epfl.ch Best regards, Alain Vachoux FDL'98 General Chair http://c3iwww.epfl.ch/fdl98/ From pilz@ifi.unizh.ch Fri Jul 24 18:48:41 1998 +0200 Return-Path: Received: from clavin.cs.tamu.edu by josef.ifi.unizh.ch with SMTP (PP) id <12677-0@josef.ifi.unizh.ch>; Fri, 24 Jul 1998 18:11:59 +0200 Received: from dilbert.cs.tamu.edu (IDENT:233@dilbert [128.194.133.100]) by cs.tamu.edu (8.9.0/8.9.0) with ESMTP id LAA02545 for ; Fri, 24 Jul 1998 11:10:07 -0500 (CDT) From: Fabrizio Lombardi Received: (from lombardi@localhost) by dilbert.cs.tamu.edu (8.9.0/8.9.0) id LAA29952 for codesign@ifi.unizh.ch; Fri, 24 Jul 1998 11:10:46 -0500 (CDT) Date: Fri, 24 Jul 1998 11:10:46 -0500 (CDT) Message-Id: <199807241610.LAA29952@dilbert.cs.tamu.edu> To: codesign@ifi.unizh.ch Status: RO X-Status: X-Keywords: X-UID: 29 Effective August 18, 1998, my address and other contact information will be as follows. Fabrizio Lombardi, Chair and ITC Professor Northeastern University Department of Electrical and Computer Engineering 110 Forsyth Street Building 309 Dana Boston, MA 02115 Phone: (617) 373-4159 (ECE Dept phone #) FAX: (617) 373-8970 Email: lombardi@ece.neu.edu Email to my present address (lombardi@cs.tamu.edu) will be forwarded to my new email address and can be used if the email address above does not work. Best Regards Fabrizio Lombardi From pilz@ifi.unizh.ch Wed Jul 29 07:43:08 1998 +0200 Return-Path: Received: from cs20.cs.nthu.edu.tw by josef.ifi.unizh.ch with SMTP (PP) id <17307-0@josef.ifi.unizh.ch>; Wed, 29 Jul 1998 07:42:46 +0200 Received: (from isss98@localhost) by cs.nthu.edu.tw (thcs.2/cs20) id NAA19032 for codesign@ifi.unizh.ch; Wed, 29 Jul 1998 13:38:34 +0800 (CST) From: isss98 Message-Id: <199807290538.NAA19032@cs.nthu.edu.tw> Subject: ISSS98: ADVANCE PROGRAM To: codesign@ifi.unizh.ch Date: Wed, 29 Jul 1998 13:38:34 +0800 (CST) X-Mailer: ELM [version 2.4ME+ PL34C (25)] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Status: RO X-Status: X-Keywords: X-UID: 30 ------------------------------------------------------ 11TH INTERNATIONAL SYMPOSIUM ON SYSTEM SYNTHESIS (ISSS) ------------------------------------------------------ Hsinchu, Taiwan, R.O.C., December 2-4, 1998 ADVANCE PROGRAM ------------------------------------------------------ Sponsored by the IEEE Computer Society DATC and the ACM SIGDA (http://www.cs.nthu.edu.tw/~isss98/) ***************** Important Dates ***************** Advance Registration Deadline : October 25, 1998 Hotel Reservation Deadline : October 25, 1998 On-Site Registration : December 1-4, 1998 ********** About ISSS ********** ISSS is a major international forum presenting emerging techniques for the system-level design and synthesis of computing systems. Having begun as the International Workshop on High-Level Synthesis in the mid-80's, it attracts leading design automation professionals from around the world. The growing acceptance of commercial synthesis tools, and the unified view of both hardware and software that such tools enable, have led to the symposium expanding to now cover system-level synthesis, hardware/software codesign, programmable (multi-)processor-based design, architectural and high-level synthesis, system-design experience and methodologies, embedded and real-time system software, synthesis for low power and testability and verifiability ISSS'98 is the 11th in this very successful series of symposia. It features 5 invited talks by leading industrial and academic experts on very timely and interesting topics related but not overlapping with the other ISSS activities. In addition, 1 panel session is organized on topics of active interest for the future of our community. ISSS'98 also features 24 high-quality regular and poster papers selected from over 60 submissions. Paper presentations will consist of 20 minute talks followed by poster sessions, allowing ample time for discussion and interaction. ****************** Technical Program ****************** ----------------------------- Tuesday, December 1, 1998 ----------------------------- 18:00 - 20:00 On-site Registration 19:00 - 21:00 Reception ----------------------------- Wednesday, December 2, 1998 ----------------------------- 08:30 - 9:00 Open statement 0 9:00 - 10:00 Invite talk (TBA) 10:00 - 10:30 Coffee break 10:30 - 11:30 Session 1: Code Generation and Optimization Issues 1.1 A Uniform Optimization Technique for Offset Assignment Problems Rainer Leupers, Fabian David 1.2 Code Generation for Compiled Bit-True Simulation of DSP Applications L. De Coster, M. Ade, R. Lauwereins, J.A. Peperstraete 1.3 Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture Wei-Kai Cheng, Youn-Long Lin 11:30 - 12:00 Poster discussion 12:00 - 13:30 Lunch 13:30 - 14:30 Invite talk (TBA) 14:30 - 15:30 Session 2: IP Reuse and Language 2.1 A Processor Description Language Supporting Retargetable Multi-Pipeline DSP Program Development Tools Chuck Siska 2.2 Intellectual Property Re-use in Embedded System Co-design: an Indutrial Case Study Enrica Filippi, Luciano Lavagno, Luigi Licciardi, Achille Montanaro, Maurizio Paolini, Roberto Passerone, Alberto Sangiovanni-Vincentelli, Marco Sgroi 2.3 Incorporating Cores into System-Level Specification Frank Vahid and Tony Givargis 15:30 - 16:00 Poster discussion and coffee break 16:00 - 16:30 Poster presentation P1 HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation Rainer Leupers P2 False Path Analysis based on a Hierarchical Control Representation Apostolos A. Kountouris and Christophe Wolinski P3 Resource constrained Modulo Scheduling with Global Resource Sharing Christoph Jaschke, Rainer Laur P4 Statistical Performance-Driven Module Binding in High-Level Synthesis Hiroyuki Tomiyama, Akihiko Inoue, and Hiroto Yasuura P5 Concurrent Error Detection at Architectural Level Cristina Bolchini, William Fornaciari, Fabio Salice, Donatella Sciuto, P6 Communication and Interface Synthesis on a Rapid Prototyping Hardware/Software Codesign System Yin-Tsung Hwang, Yuan-Hung Wang 16:30 - 17:30 Poster discussion 18:30 - 20:00 Dinner 20:00 - 22:00 Panel and Beer (TBA) ----------------------------- Thursday, December 3, 1998 ----------------------------- 9:00 - 10:00 Invite talk (TBA) 10:00 - 10:30 Coffee break 10:30 - 11:30 Session 3: Application-Specific Synthesis Techniques 3.1 Application-Specific Heterogenous Multiprocessor Synthesis Using Differential-Evolution Allan Rae, Sridevan Parameswaran 3.2 Proposal for unified system design meta flow in task-level and instruction-level design technology research for multi-media applications Francky Catthoor, Diederik Verkest, Erik Brockmeyer 3.3 Data-path Synthesis of VLIW Video Signal Processors Zhao Wu, Wayne Wolf 11:30 - 12:00 Poster discussion 12:00 - 13:30 Lunch 13:30 - 14:30 Invite talk (TBA) 14:30 - 15:30 Session 4: Synchronization and Interface Issues 4.1 Synchronization Detection for Multi-Process Hierarchical Synthesis Oliver Bringmann, Wolfgang Rosenstiel, Dirk Reichardt 4.2 Integrating Communication Protocol Selection with Partitioning in Hardware/Software Codesign Peter Voigt Knudsen and Jan Madsen 4.3 Interface Exploration for Reduced Power in Core-Based Systems Tony Givargis, Frank Vahid 15:30 - 16:00 Poster discussion and coffee break 16:00 - 17:00 Session 5: Instruction Encoding and Software Synthesis Techniques 5.1 Instruction Encoding Techniques for Area Minimization of Instruction ROM Takanori Okuma, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar, Hiroto Yasuura 5.2 Application of Instruction Analysis/Synthesis Tools to x86's Functional Unit Alloation Ing-Jer Huang, Ping-Huei Xie 5.3 Memory Efficient Software Synthesis from Dataflow Graph Wonyong Sung, Junedong Kim, Soonhoi Ha 17:00 - 17:30 Poster discussion 17:30 - 18:30 General discussion session 19:00 - 21:00 Banquet ----------------------------- Friday, December 4, 1998 ----------------------------- 9:00 - 10:00 Invite talk (TBA) 10:00 - 10:30 Coffee break 10:30 - 11:30 Session 6: Partitioning and Scheduling Techniques 6.1 A Tool Partitioning and Pipelined Scheduling of Hardware-Software Systems Karam S. Chatha and Ranga Vemuri 6.2 A Three-Step Approach to the Functional Partitioning of Large Behavioral Processes Frank Vahid 6.3 Fine-Grain, Incremental Rescheduling Via Architectural Retiming Soha Hassoun 11:30 - 12:00 Poster discussion 12:00 - 13:30 Lunch 13:30 - 16:30 Science-Based Industry Park tour ----------------------------- Saturday, December 5, 1998 ----------------------------- Taipei City Tour ----------------------------- Sunday, December 6, 1998 ----------------------------- Tarako National Park Tour *************************** Registration Information *************************** Advance registration due : October 25, 1998 ------------------------------------------- Conference pre-registration is strongly advised. Participants are therefore requested to fill in and e-mail (payment by credit card only) or mail the enclosed registration form together with the appropriate fee to: ISSS'98 Program Chair Allen C.-H. Wu Department of Computer Science National Tsing Hua University Hsinchu, Taiwan E-mail:chunghaw@cs.nthu.edu.tw Fax: 886-3-5723694 Registration will be confirmed only upon receipt of the registration fee. Registration Fees: The Symposium registration fees include admission to all technical sessions, lunchs, coffee breaks, receiption, banquet (except students), and a copy of the symposium proceedings. Before Oct. 25, 1998 After Oct. 25, 1998 ACM/IEEE Member US$320 NT$11,000 US$380 NT$13,000 Non-member US$400 NT$13,500 US$450 NT$15,500 Full-time Student US$150 NT$ 5,000 US$200 NT$6,500 Payment: Payment can be made by credit card, cash, traveler's check, 1. bank draft or bank transfer to: Allen C.-H. Wu Account No. 036-16-0060160, Chiao Tung Bank, Hsinchu Branch, Hsinchu, Taiwan. 2. Credit Card Credit Card is available for pre-registration and on-site registration. Please fill out the appropriate section on the registration form. On-site registration: On-site registration desk: 15 F., Chinatrust Hotel Registration desk will be opened during the following hours: Tuesday, December 1, 1998 18:00 - 20:00 Wednesday, December 2, 1998 08:00 - 16:30 Thursday, December 3, 1998 08:30 - 16:30 Friday, December 4, 1998 08:30 - 10:00 ------------------------- cut here -------------------------------- *************************** ISSS'98 Registration Form *************************** (Print or Type, one form for each registrant) Please enter your session/paper number _________________ for authors. Advance Registration Deadline: October 25, 1998 Any registration after Oct. 25, 1998 (postmark cut-off) will be charged the at-symposium rate. Please complete the information below. Payment with registration must be made in US or NT dollars and made payable to: Allen C.-H. Wu Title : __Prof. __Dr. __Mr. __Ms. __Miss. __Mrs. Name : _______________________________________ Last First Mid Affiliation : _______________________________________ Address : _______________________________________ _______________________________________ _______________________________________ Phone : ______________________ Fax : ______________________ E-mail : ______________________ Special needs : ______________________ Before Oct. 25, 1998 After Oct. 25, 1998 __ ACM/IEEE Member __US$320 __NT$11,000 __US$380 __NT$13,000 __ Non-member __US$400 __NT$13,500 __US$450 __NT$15,500 __ Full-time Student __US$150 __NT$ 5,000 __US$200 __NT$6,500 Total Amount Enclosed : US$ __________ NT$ ___________ (or transferred to the above mentioned account) ACM/IEEE Membership # : _________________ (reqd. if registering at ACM/IEEE rates) I __enclose __Traver's check __ Money order I __use Credit card : __Visa __Master Card (Do not accept American Express). Card No. __________ - __________ - __________ - __________ Expiry date: ______________________________________________ Name as it appears on card: _______________________________ Passport no./ROC citizen ID no.: __________________________ Signature: ________________________________________________ Date: _____________________________________________________ Cancellation Policy: No refunds will be made on cancellations received after Nov. 20, 1998. Cancellations received before Nov. 20 are subject to a 20% processing fee. --------------------------cut here---------------------------------- ************************ Hotel Reservation Form ************************ Please type or print. Title : __Prof. __Dr. __Mr. __Ms. __Miss. __Mrs. Name : _______________________________________ Last First Mid Affiliation : _______________________________________ Address : _______________________________________ _______________________________________ _______________________________________ Phone : _______________________________________ Fax : _______________________________________ E-mail : _______________________________________ Member of IEEE/ACM Member No.: __________________________ HOTEL RESERVATION Hotel Single Twin __Chinatrust Hotel __NT$2,970 __NT$3,330 __Shin Yuan Park Hotel __NT$2,430 __NT$3,120 (include service charge and tax.) Check-in date: ___________ Check-in time: _________ Check-out date: ___________ Number of nights: _____ TRANSPORTATION One way, between the CKS Airport and Hotel: NT$1,300 Flight Number: ___________ Arrival Time: ____________ METHOD OF PAYMENT Pay to the hotel when you check out with cash, traveler's check, or credit card. No personal check, please. NOTE: The room rates and availability are guaranteed for the period of Nov. 29 - Dec. 6, 1998, only if your reservation form is received before Oct. 25, 1998. Please send this form to the hotel you choose: Chinatrust Hotel: 106 Chung Yang Rd., Hsinchu, Taiwan 300 Fax: +886-3-5269244; Tel: +886-3-5263181 Shin Yuan Park Hotel: 11 Ta Tung Rd., Hsinchu, Taiwan 300 Fax: +886-3-5260522; Tel: +886-3-5226868 ---------------------------cut here-------------------------------------------- ********************* Tour Reservation Form ********************* Tour 1.: Taipei City Tour Date: Dec. 5, 1998 (Sat.) Fare: NT$1,750(Includes: 1 lunch) 1. National Palace Museum 2. Martyr's Shrine 3. Chinese Temple 4. Chiang Kai-Shek Memorial Hall 5. Dr. Sun Y. S. Memorial Hall 6. Presidential Office (Pass by) 7. Handicraft Center Tour 2.: Tarako National Park (Hualien) Date: Dec. 6, 1998 (Sun.) Fare: NT$4,200 (Including: Round-trip air ticket and lunch) (Passport needed for enplaning) Itinerary: Pick-up from hotel -> Transfer to Taipei Airport -> Arrive at Hualien -> Enbus for Tarako Groge Gateway -> Eternal-Spring Shrine -> Swallow Caves -> Tunnel of Nine Turns -> TienhsiangLodge -> Marble factory -> Enplane for Taipei -> Transfer to hotel Please type or print. Sex: __F __M Name : _______________________________________ Last First Mid Passprot No.: _______________________________________ Birth Date: _______________________________________ Nationality: _______________________________________ Signature: _______________________________________ Tour Selection: please indicate your choice(s) ___ Taipei City Tour ____Tarako National Park (Hualien) Total amount: NT$______________________ Payment: By cash or traverler's check in NTD to the travel agent at the conference site. Please send this form to (before Oct. 25, 1998) Trans Continental Travel Service Co., Ltd. 4F, No. 21, Lane 45, Sec. 2, Chung-San N. Rd., Taipei, Taiwan. Fax: +886-2-25230002; +886-2-26946057 Tel: +886-2-25233131 ------------------------- cut here -------------------------------- **************** Visa Information **************** A visa is required for foreign passport holders. However, if your passort and the length of your visit to Taiwan satisfy the following terms, then no visa is required: (1) You are holding a passort from USA, Japan, France,Germany, Canada, Australia, Austria, Belgium, Costa Rica, Greece, Italy, Luxembourg, New Zealand, the Netherlands(Holland), Portugal, Spain, Sweden, and U.K. (Please reconfirm with your travel agent!!!) (2) Your passport is valid for longer than 6 months. (3) The length of your visit is less than 14 days. (4) a confirmed return air (steamer) ticket or an air(steamer) ticket and a visa for the next destination, and a confirmed air (steamer) seat reservation for his (her) departure. Visa can be obtained from Taiwans embassies, consulates, or designated representative offices. Please check with your travel agent concerning necessary procedures. ********************** Symposium Proceedings ********************** The symposium proceedings will be published by IEEE CS Press but will also be available from ACM. Extra copies of the proceedings can be ordered from: Customer Service Department IEEE Computer Society Press 10662 Los Vaqueros Circle P.O. Box 3014 Los Alamitos, California 90720 Tel: (714) 821-8380 Fax: (714) 821-4641 Email: cs.books@computer.org *********************** Organizing Committee *********************** General Chair: Francky Catthoor, IMEC Honorary Chair: C. L. Liu, Tsing Hua U. Program Chair: Allen C.-H. Wu, Tsing Hua U. Publications Chair: L.-G. Chen. Taiwan U. Panels Chair: Nikil Dutt, U. C. Irvine Publicity Co-Chairs: J.-M. Shyu, ITRI I.-J. Huang, Sun Yat-Sen U. Finance Chair: W.-Z. Shen, Chiao Tung U. Local Arrangement Chair: Y.-L. Lin, Tsing Hua U. Past Chair: Frank Vahid, U. C. Riverside ****************************** Technical Program Committee ****************************** Marleen Ade, K.U. Leuven Gaetano Borriello, Univ. Washington Raul Camposano, Synopsys Nikil Dutt, U.C. Irvine Rolf Ernst, Tech. Univ. Braunschweig Masahiro Fujita, Fujitsu Daniel Gajski, U.C. Irvine Cathy Gebotys, Univ. Waterloo Yu-Chin Hsu, Avant! Ahmed A. Jerraya, TIMA Kayhan Kucukcakar, Escalade Corp. Fadi Kurdahi, U.C. Irvine Steve Y.L. Lin, Tsing Hua Univ. Paul Lippens, Philips Jan Madsen, Tech. Univ. Denmark Lev Markov, Mentor Graphics Peter Marwedel, Univ. Dortmund Vijay Nagasamy, VSIS Inc. Yukihiro Nakamura, Kyoto Univ. Sanjiv Narayan, Ambit Design Systems Kevin O'brien, Leda B. Ramakrishna(Bob)Rau, HP Labs. Wolfgang Rosenstiel, Univ. Tubingen, FZI Edwin Sha, Univ. Notre Dame Leon Stok, IBM Donald Thomas, CMU Diederik Verkest, IMEC Kazutoshi Wakabayashi, NEC Robert Walker, Kent State Univ. Wayne Wolf, Princeton Hiroto Yasuura, Kyushu Univ. ************* Information: ************* For more information, please contact ISSS'98 secretariat: Ms. Shu-Jane Lee Department of Computer Science National Tsing Hua University Hsinchu, Taiwan Fax: +886-3-5731149 Tel: +886-3-5715131 ext.4146 E-mail: sjlee@slugger.ee.nthu.edu.tw WWW: http://www.cs.nthu.edu.tw/~isss98 ------------------------------------------------------------------------------- ** Sponsored by the IEEE Computer Society (DATC) and the ACM SIGDA ** ------------------------------------------------------------------------------- From pilz@ifi.unizh.ch Thu Aug 6 09:04:15 1998 +0200 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <18744-0@josef.ifi.unizh.ch>; Thu, 6 Aug 1998 09:04:06 +0200 Return-Path: X-Received: from epsilon.ece.nwu.edu by josef.ifi.unizh.ch with SMTP (PP) id <11581-0@josef.ifi.unizh.ch>; Thu, 6 Aug 1998 00:45:00 +0200 X-Received: (from daemon@localhost) by epsilon.ece.nwu.edu (8.8.5/8.8.3) id OAA27701 for ; Wed, 5 Aug 1998 14:01:50 -0500 (CDT) X-Received: from seattle.ece.nwu.edu(129.105.5.174) by epsilon.ece.nwu.edu via smap (V2.1-NU-ECE-norelay) id xma027678; Wed, 5 Aug 98 14:01:34 -0500 X-Received: (from hauck@localhost) by seattle.ece.nwu.edu (8.8.5/8.8.3) id OAA04466 for fpga97; Wed, 5 Aug 1998 14:01:33 -0500 (CDT) Date: Wed, 5 Aug 1998 14:01:33 -0500 (CDT) From: Scott Alan Hauck Message-Id: <199808051901.OAA04466@seattle.ece.nwu.edu> To: fpga97@seattle.ece.nwu.edu Subject: FPGA '99 Call For Papers ReSent-Date: Thu, 6 Aug 1998 09:00:53 +0200 (MET DST) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: FPGA '99 Call For Papers ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 31 FPGA `99: Call for Papers Seventh ACM International Symposium on Field-Programmable Gate Arrays DoubleTree Hotel, Monterey, California February 21-23, 1999 As we reach the end of the 1990s, rapidly increasing speed and capacity have made FPGAs a standard implementation target for digital logic. Advancements in FPGA architectures proceeds unabated, and larger, faster devices enable new, innovative applications that continue to stress designers and their tools. For FPGA `99, we are soliciting submissions describing novel research and development in the following (and related) areas of interest: FPGA Architecture: Logic block & routing architectures, I/O structures and circuits, new commercial architectures, Field-Programmable Interconnect Chips and Devices (FPIC/FPID), Field-Programmable Analog Arrays (FPAA). CAD for FPGAs: Placement, routing, logic optimization, technology mapping, system-level partitioning, logic generators, testing and verification. CAD for FPGA-based accelerators. Interactions: between CAD, architecture, applications, and programming technology. Applications: Innovative use of FPGAs, exploitation of FPGA features, novel circuits, high-performance and low-power/mission-critical applications, DSP techniques, uses of reconfiguration, FPGA-based cores. FPGA-based computing engines: Compiled accelerators, reconfigurable computing, adaptive computing devices, systems and software. Fast prototyping for system level design, Multi-Chip Modules (MCMs), logic emulation. Authors are invited to submit PDF (preferred) or postscript of their paper (12 pages maximum) by October 2, 1998 via E-mail to fpga99@xilinx.com. Alternatively, authors may submit a 3.5" floppy disk containing the pdf or postscript file or 22 copies of their paper to the program chair. Notification of acceptance will be sent by December 1, 1998. The authors of the accepted papers will be required to submit the final camera-ready copy by December 15, 1998. A proceedings of the accepted papers will be published by ACM, and included in the Annual ACM/SIGDA CD-ROM Compendium publication. Address questions to: Steve Trimberger Program Chair, FPGA `99 Xilinx, Inc. 2100 Logic Dr. San Jose, CA 95124-3450 USA phone: (408) 879-5061 fax: (408) 559-7114 fpga99@xilinx.com General Chair: Sinan Kaptanoglu, Actel Finance Chair: Jason Cong, UCLA Program Chair: Steve Trimberger, Xilinx Publicity Chair: Scott Hauck, Northwestern U. Program Committee Om Agrawal, Vantis Ray Andraka, Andraka Consulting Michael Butts, Quickturn Jason Cong, UCLA Eugene Ding, Lucent Carl Ebeling, U. of Washington Scott Hauck, Northwestern U. Brad Hutchings, BYU Sinan Kaptanoglu, Actel David Lewis, U. of Toronto Fabrizio Lombardi, Texas A&M Wayne Luk, Imperial College Margaret Marek-Sadowska, UCSB Peter Moceyunas, Synopsys Jonathan Rose, U. of Toronto Gabriele Saucier, INPG Martine Schlag, UCSC Herman Schmit, CMU Tim Southgate, Altera Steve Trimberger, Xilinx John Wawrzynek, UCB Martin Wong, UT at Austin Sponsored by ACM SIGDA, with support from Xilinx, Altera, Lucent and Actel. Please visit for more information. From pilz@ifi.unizh.ch Thu Aug 20 12:07:38 1998 +0200 Return-Path: Received: from fw-cam.cambridge.arm.com by josef.ifi.unizh.ch with SMTP (PP) id <17472-0@josef.ifi.unizh.ch>; Thu, 20 Aug 1998 12:07:14 +0200 Received: by fw-cam.cambridge.arm.com; id LAA23612; Thu, 20 Aug 1998 11:07:03 +0100 Received: from sun1.cambridge.arm.com(172.16.1.1) by fw-cam.cambridge.arm.com via smap (3.2) id xma023574; Thu, 20 Aug 98 11:06:47 +0100 Received: from cam-mail1.cambridge.arm.com (node800064b5) by arm.com (4.1/SMI-4.1) id AA01533; Thu, 20 Aug 98 11:06:46 BST Received: from arm.com by cam-mail1.cambridge.arm.com (SMI-8.6/SMI-SVR4) id LAA23718; Thu, 20 Aug 1998 11:06:45 +0100 Message-Id: <35DBF533.1D522FA2@arm.com> Date: Thu, 20 Aug 1998 11:06:43 +0100 From: Jon Connell Organization: ARM Ltd. X-Mailer: Mozilla 4.05 [en] (Win95; U) Mime-Version: 1.0 To: codesign@ifi.unizh.ch, codesign@vhdl.org Subject: Commercial codesign and C-simulation tools Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Status: RO X-Status: X-Keywords: X-UID: 32 Can anyone point me in the direction of any commercial codesign and C-simulation tools? Such products should have the facility to import IP. Jon. -- ARM Ltd, Fulbourn Rd, Cherry Hinton, Cambridge CB1 4JN, U.K. Tel: +44 1223 400540 Fax: +44 1223 400410 mailto:jon.connell@arm.com http://www.arm.com/DevSupp/EDA/ Spelling mistakes brought to you by the Microsoft Natural Keyboard. From pilz@ifi.unizh.ch Thu Aug 20 13:00:29 1998 +0200 Return-Path: Received: from zwei.siemens.at by josef.ifi.unizh.ch with SMTP (PP) id <18879-0@josef.ifi.unizh.ch>; Thu, 20 Aug 1998 13:00:20 +0200 Received: from scesie04.sie.siemens.at (root@[10.1.140.1]) by zwei.siemens.at with ESMTP id NAA13821 for ; Thu, 20 Aug 1998 13:00:09 +0200 (MET DST) Received: from sceerd01.erd.siemens.at (sceerd01.erd.siemens.at [195.2.52.1]) by scesie04.sie.siemens.at () with ESMTP id NAA17881 for ; Thu, 20 Aug 1998 13:00:09 +0200 (METDST) Received: from lappi.erd.siemens.at (lappi.erd.siemens.at [195.2.3.188]) by sceerd01.erd.siemens.at (8.8.7/8.8.5) with SMTP id NAA25638 for ; Thu, 20 Aug 1998 13:00:08 +0200 (METDST) Received: from agi.erd.siemens.at by lappi.erd.siemens.at (4.1/SMI-4.1) id AA01779; Thu, 20 Aug 98 13:00:06 +0200 Received: by agi.erd.siemens.at (SMI-8.6/SMI-SVR4) id NAA16135; Thu, 20 Aug 1998 13:00:05 +0200 Date: Thu, 20 Aug 1998 13:00:05 +0200 From: mbd_oef@agi.erd.siemens.at (Fredrik :Ostman) Message-Id: <199808201100.NAA16135@agi.erd.siemens.at> To: codesign@ifi.unizh.ch Subject: Re: Commercial codesign and C-simulation tools X-Sun-Charset: US-ASCII Status: RO X-Status: X-Keywords: X-UID: 33 +-----< Jon Connell > | Can anyone point me in the direction of any commercial | codesign and C-simulation tools? Such products should | have the facility to import IP. +- Can you give more details? IP as in micro-processor cores, compiled programmes, operating systems or chip processes? And C simulation? Why not compile and run? In any case, I think you'll find what you need on the homepages of Mentor and Synopsys. ______ _~ (_/_ _ _ _/) _ . /) / ) , _/) _ __/ _/(_(/_(/__/(_/_/Z_ (_/_/)_/__/))_(I_/)_ Fredrik :Ostman Siemens AG :Osterreich EZE TNA5 Erdberger L:ande 26, A-1031 WIEN, Austria +43 (1) 1707 35235, fax +43 (1) 1707 55670, Fredrik.Oestman@siemens.at From pilz@ifi.unizh.ch Fri Aug 21 10:44:01 1998 +0200 Return-Path: Received: from yalta.NL.net by josef.ifi.unizh.ch with SMTP (PP) id <12905-0@josef.ifi.unizh.ch>; Fri, 21 Aug 1998 10:43:46 +0200 Received: from kun99-28.Nijmegen.NL.net ([193.67.237.253]:54788 "HELO antiloop.viewlogic.com") by yalta.NL.net with SMTP id <17045-5953>; Fri, 21 Aug 1998 10:43:11 +0200 From: Mark Hofstede To: Jon Connell , codesign , codesign Subject: RE: Commercial codesign and C-simulation tools Date: Fri, 21 Aug 1998 10:41:32 +0200 Message-ID: <000301bdccdf$7faf2540$463557c0@antiloop.viewlogic.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit X-Priority: 3 (Normal) X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook 8.5, Build 4.71.2173.0 Importance: Normal X-MimeOLE: Produced By Microsoft MimeOLE V4.72.2106.4 In-Reply-To: <35DBF533.1D522FA2@arm.com> Status: RO X-Status: X-Keywords: X-UID: 34 Beside Mentor, Synopsys, Summit Design offers you also the possibility for Co-Design using V-CPU. Specially the Motorola family microprocessors are supported well. Perhaps the products of www.topdown.com can help you with your C-sim and IP issue. Best Regards, Mark Hofstede EASEurope BV Goorseweg 5 The Netherlands tel: +31 547 367 347 fax: +31 547 367 340 > -----Original Message----- > From: Jon Connell [mailto:jon.connell@arm.com] > Sent: Thursday, August 20, 1998 12:07 PM > To: codesign@ifi.unizh.ch; codesign@vhdl.org > Subject: Commercial codesign and C-simulation tools > > > Can anyone point me in the direction of any commercial > codesign and C-simulation tools? Such products should > have the facility to import IP. > > Jon. > -- > ARM Ltd, Fulbourn Rd, Cherry Hinton, Cambridge CB1 4JN, U.K. > Tel: +44 1223 400540 Fax: +44 1223 400410 > mailto:jon.connell@arm.com http://www.arm.com/DevSupp/EDA/ > > Spelling mistakes brought to you by the Microsoft Natural Keyboard. > From pilz@ifi.unizh.ch Fri Aug 21 17:38:20 1998 +0200 Return-Path: Received: from Morgane.OLEANE.Net by josef.ifi.unizh.ch with SMTP (PP) id <24316-0@josef.ifi.unizh.ch>; Fri, 21 Aug 1998 17:38:02 +0200 Received: from leda2.leda.fr (leda2.leda.fr [195.25.177.161]) by morgane.oleane.net with ESMTP id RAA23049; Fri, 21 Aug 1998 17:37:35 +0200 Received: from [195.25.177.181] (mac2.leda.fr [195.25.177.181]) by leda2.leda.fr (8.7.4/8.7.3) with SMTP id RAA11660; Fri, 21 Aug 1998 17:33:55 +0100 (WET DST) X-Sender: kevin@leda2.leda.fr Message-Id: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Date: Fri, 21 Aug 1998 17:49:31 +0100 To: Jon Connell From: kevin@leda.fr (Kevin O'Brien) Subject: Re: Commercial codesign and C-simulation tools Cc: codesign@ifi.unizh.ch, codesign@vhdl.org Status: RO X-Status: X-Keywords: X-UID: 35 >Can anyone point me in the direction of any commercial >codesign and C-simulation tools? Such products should >have the facility to import IP. > >Jon. >-- >ARM Ltd, Fulbourn Rd, Cherry Hinton, Cambridge CB1 4JN, U.K. >Tel: +44 1223 400540 Fax: +44 1223 400410 >mailto:jon.connell@arm.com http://www.arm.com/DevSupp/EDA/ > Check out http://www.arexsys.com They have what you're looking for. Kevin O'Brien ------------------------------------------------------------ -- -- -- Kevin O'Brien, -- -- End-user product manager, -- -- LEDA s.a., -- -- 35 Avenue du Granier, 38240 Meylan, France. -- -- -- -- Tel : (+33) (0)4 76 41 92 43 -- -- Fax : (+33) (0)4 76 41 92 44 -- -- -- -- E-mail: obrien@leda.fr or kevin@leda.fr -- -- Web : http://www.leda.fr -- -- -- ------------------------------------------------------------ From pilz@ifi.unizh.ch Thu Aug 27 09:43:25 1998 +0200 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <28378-0@josef.ifi.unizh.ch>; Thu, 27 Aug 1998 09:43:02 +0200 Return-Path: X-Received: from pol88b.polito.it by josef.ifi.unizh.ch with SMTP (PP) id <20326-0@josef.ifi.unizh.ch>; Wed, 26 Aug 1998 22:30:45 +0200 X-Received: from chiusella.polito.it.polito.it (chiusella.polito.it) by polito.it (PMDF V4.2-15 #3020) id <01J12NRDAKGW8WX4LR@polito.it>; Wed, 26 Aug 1998 21:15:38 GMT+1 X-Received: by chiusella.polito.it.polito.it (4.1/SMI-4.1) id AA10475; Wed, 26 Aug 98 21:15:35 +0200 Date: Wed, 26 Aug 1998 21:15:35 +0200 From: tttc@chiusella.polito.it (Paolo Prinetto) Subject: IEEE TTTC - VTS 99: 17TH IEEE VLSI TEST SYMPOSIUM To: pilz@ifi.unizh.ch Message-id: <9808261915.AA10475@chiusella.polito.it.polito.it> X-Envelope-to: pilz@ifi.unizh.ch Content-transfer-encoding: 7BIT Apparently-To: PILZ Markus ReSent-Date: Thu, 27 Aug 1998 09:39:22 +0200 (MET DST) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: IEEE TTTC - VTS 99: 17TH IEEE VLSI TEST SYMPOSIUM ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 36 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % IEEE Computer Society % Test Technology Technical Committee % % % .... FOR YOUR INFORMATION.... % % A free service of the Technical Meeting Group % % % This message contains public information, only, and % the receiver is allowed, and invited, to copy it and % distribute it further. % % % For more information contact % or visit http://www.computer.org/tab/tttc/ % % If you would like to be removed from this mailing list, % please send an e-mail to % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% CALL FOR PAPERS 17TH IEEE VLSI TEST SYMPOSIUM Marriott Laguna Cliffs Resort, Dana Point, California April 25 - April 29, 1999 WWW site: http://www.computer.org/tab/tttc/meetings/vts/home.html ********************************************************************** IEEE VLSI Test Symposium explores emerging trends and novel concepts in testing of circuits and systems. The theme of the seventeenth symposium is "Scaling Deeper to Submicron: Test Technology Challenges". The major topics include, but are not limited to, the following: . Analog and RF Testing . IDDQ Testing . Automatic Test Generation . MEMS Testing . Built-In Self-Test (BIST) . Multi-Chip Module Test . Delay Testing . On-Line Testing . Design for Testability . Quality and Reliability . Design Verification/Validation . Self-Checking Circuits . Diagnosis and Debugging . Synthesis for Testability . Embedded Core Testing . System Test . Fault Modeling & Simulation . System-on-Chip Test . Fault Tolerant Architectures . Thermal Testing The Program Committee invites original, unpublished paper proposals (complete manuscripts or extended summaries) and proposals for panel sessions. Authors should clearly explain the significance of the work, highlight novel features, and describe its current status. On the title page, please include: name, affiliation, mailing address, phone number, fax number, and E-mail address of the contact author. A 50 word abstract, and 5 key words identifying the topic area are also required. Electronic submission in Postscript is encouraged, although hard copy submissions to the Program Chair (10 copies) will also be accepted. Detailed directions for submitting papers are available at: http://www.computer.org/tab/tttc/meetings/vts/home.html Submissions are due no later than October 30, 1998. For additional information, contact: Michael Nicolaidis, General Chair Adit Singh, Program Chair TIMA Dept. of Electrical Engineering 46 Avenue Felix VIALLET Auburn University 38031 Grenoble Cedex, FRANCE Auburn, AL 36849 T: +33-476-57-4619, F: +33-476-47-3814 T: +1-334 844-1847 F:+1-334-844 -1809 E: Michael.Nicolaidis@imag.fr E: adsingh@eng.auburn.edu Authors will be notified of the disposition of their papers by January 8, 1999. The submission of a proposal will be considered evidence that upon acceptance the author(s) will present the paper at the symposium and will submit a final paper for inclusion in the proceedings no later than February 11, 1999. VTS'99 will present a Best Paper Award and a Best Panel Award, based on the evaluations of reviewers, attendees, and an invited panel of judges. VTS 99 convenes in Marriot's Laguna Cliffs Resort at Dana Point overlooking the Pacific Ocean and the Southern California coast line! Midway between Los Angeles and San Diego. A site that preserves the special reputation of combining dramatic towering cliffs, white sand beaches, coastal majestic bluffs and sensational ocean sunsets! Conveniently located near Orange County John Wayne Airport. VLSI Test Symposium is sponsored by the IEEE Computer Society Test Technology Technical Committee (TTTC). ********************************************************************** GENERAL CHAIR M. Nicolaidis - TIMA PROGRAM CHAIR A. Singh - Auburn U PAST CHAIR R. Roy - Intel VICE GENERAL CHAIR S. Dey - UCSD VICE PROGRAM CHAIRS J. Figueras - U Poli Catalunya S. Chakravarty - Intel PUBLICITY A. Raghunathan - NEC USA FINANCE A. Ivanov - U of Brit. Columbia PANELS H-J. Wunderlich - U of Stuttgart PUBLICATIONS F. J. Ferguson - UC Santa Cruz LOCAL ARRANGEMENTS J. Monzel - IBM EX OFFICIO Y. Zorian - LogicVision PROGRAM COMMITTEE : M. Abadir - Motorola J.A. Abraham - U of Texas M. Abramovici - Lucent Bell Labs S. Adham - Nortel V.D. Agrawal - Lucent Bell Labs J. Aylor - U of Virginia B. Becker - U of Freiburg S. Blanton - Carnegie-Mellon U M. Breuer - U of Southern Cal. G. Carlsson - Ericsson A. Chatterjee - Georgia Tech. K.T. Cheng - UC Santa Barbara B. Courtois - TIMA M. d'Abreu - Level One Comm. W.K. Fuchs - Purdue U H. Fujiwara - NAIST M. Goessel - U of Potsdam J.P. Hayes - U of Michigan N. Jha - Princeton U B. Kaminska - OPMAXX K. Kinoshita - Osaka U A. Kuchukian - Armenian NAS C. Landrault - U Montpellier II A. Majumdar - Synopsys W. Maly - Carnegie-Mellon U P. Maxwell - Hewlett Packard E.J. McCluskey - Stanford U B. Nadeau-Dostie - LogicVision V. Nelson - Auburn U A. Orailoglu - UC San Diego C. Papachristou - Case West. Res. U A. Paschalis - NCSR Demokritos J.H. Patel - U of Illinois I. Pomeranz - U of Iowa T. Powell - Texas Instruments D. Pradhan - Texas A&M U P. Prinetto - Politecnico di Torino J. Rajski - Mentor Graphics E. Rudnick - U of Illinois R. Segers - Philips E. Sogomonyan - Russian NAS S. Sunter - LogicVision M. Soma - U of Washington S. Tragoudas - Southern Illinois U A.J. van de Goor - Delft U T.W. Williams - Synopsys STEERING COMMITTEE: D. Graham - inTest N. Kornfield - Widener U M. Modi - Naval Air War. Cnt R. Roy - Intel P. Varma - Veritable Y. Zorian - LogicVision ********************************************************************** IEEE VLSI Test Symposium 1474 Freeman Drive, Amissville, VA 20106, USA Tel: +1 (540) 937-8280, Fax: +1 (540) 937-3739 Email: tttc@computer.org WWW Site: http://www.computer.org/tab/tttc/meetings/vts/home.html ********************************************************************** %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % Paolo PRINETTO % % IEEE Computer Society % Test Technology Technical Committee (Vice Chair) % % Politecnico di Torino % Dip. di Automatica e Informatica % Corso Duca degli Abruzzi 24 % I-10129 Torino TO % Italy % % Tel: + 39 011 564.7007 % Fax: + 39 011 564.7099 % % E-mail: Paolo.Prinetto@polito.it % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% From pilz@ifi.unizh.ch Thu Aug 27 09:46:27 1998 +0200 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <28484-0@josef.ifi.unizh.ch>; Thu, 27 Aug 1998 09:46:05 +0200 Return-Path: X-Received: from news.uni-kl.de by josef.ifi.unizh.ch with SMTP (PP) id <19739-0@josef.ifi.unizh.ch>; Wed, 26 Aug 1998 21:57:12 +0200 X-Received: from informatik.uni-kl.de ( uklirb.informatik.uni-kl.de [131.246.161.11] ) by news.uni-kl.de id bh06910 for ; 26 Aug 98 21:58 MESZ X-Received: from irz1.informatik.uni-kl.de by uklirb.informatik.uni-kl.de id aa27369; 26 Aug 98 21:47 MET DST X-Received: by irz1.informatik.uni-kl.de (SMI-8.6/SMI-SVR4) id VAA05986; Wed, 26 Aug 1998 21:47:51 +0200 From: AG Hartenstein-UNI KL-FRG Message-Id: <199808261947.VAA05986@irz1.informatik.uni-kl.de> Subject: Final call for Participants: FPL'98 To: pilz@ifi.unizh.ch Date: Wed, 26 Aug 1998 21:47:51 +0200 (MET DST) X-Mailer: ELM [version 2.4 PL24] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit ReSent-Date: Thu, 27 Aug 1998 09:42:28 +0200 (MET DST) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: Final call for Participants: FPL'98 ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 37 ******************************************************************************* * We apologize, if you receive this message more than once. * This message contains public information, and the receiver is allowed and * invited to copy it and distribute it further. * For information about the contents of this message, pleas contact * abakus@informatik.uni-kl.de * If you would like to be removed from this mailing list, please send a * message to: abakus@informatik.uni-kl.de and specify the address to be removed ******************************************************************************* ---------- LAST CALL FOR PARTICIPANTS --------- I I I I Chamada final I I I I_______________________________I I I I I I I I >>> FPL'98 <<< I I -------I_______________________________I------- I I I Eighth International Workshop on I I Field-Programmable Logic and Applications I I I I August 31 - September 3, 1998 I I Tallinn - Estonia I ----------------------------------------------- The International Workshop on Field-Programmable Logic and Applications provides a high-quality forum for the exchange of ideas and results in all areas related to the development and use of field-programmable logic. The Call for papers has been very successful: 39 regular papers and 29 posters will be presented at the conference. Please find the FINAL PROGRAM on the FPL'98 web site: http://xputers.informatik.uni-kl.de/FPL/FPL98/fpl98.html The registration form can be found at: http://xputers.informatik.uni-kl.de/FPL/FPL98/AdvPrg/fpl98advprg1_6.pdf For local details, you may also visit: http://www.ttu.ee/fpl98 Prof. Reiner W. Hartenstein, Program Chair From pilz@ifi.unizh.ch Fri Sep 11 10:24:22 1998 +0200 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <21608-0@josef.ifi.unizh.ch>; Thu, 10 Sep 1998 20:37:58 +0200 Return-Path: X-Received: from ic.EECS.Berkeley.EDU by josef.ifi.unizh.ch with SMTP (PP) id <20127-0@josef.ifi.unizh.ch>; Thu, 10 Sep 1998 19:28:56 +0200 X-Received: (from kuehl@localhost) by ic.EECS.Berkeley.EDU (8.8.8/8.8.8) id KAA04284 for pilz@ifi.unizh.ch; Thu, 10 Sep 1998 10:28:56 -0700 (PDT) Date: Thu, 10 Sep 1998 10:28:56 -0700 (PDT) From: Andreas Kuehlmann Message-Id: <199809101728.KAA04284@ic.EECS.Berkeley.EDU> To: pilz@ifi.unizh.ch Subject: September 11: ICCD Early Registration Deadline ReSent-Date: Thu, 10 Sep 1998 20:34:04 +0200 (MET DST) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: September 11: ICCD Early Registration Deadline ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 38 (Apologies for multiple copies of the email) --------------------------------------------------------------------- International Conference on Computer Design ICCD'98 October 5 - 7, 1998 Marriott Hotel at the Capital, Austin, Texas Sponsored by: IEEE Computer Society and IEEE Circuits and Systems Society In Cooperation with: IEEE Electron Devices Society http://domino.watson.ibm.com/iccd98/iccd98.nsf --------------------------------------------------------------------- ICCD '98 Call for Participation The International Conference on Computer Design encompasses a wide range of topics in the design and implementation of computer systems and their components. ICCD's multi disciplinary emphasis provides an ideal environment for developers and researchers to discuss practical and theoretical work covering system and computer architecture, verification and test, design and technology, and tools and methodologies This year's program includes three invited sessions on the latest processor developments, two embedded tutorials, two panel discussions, two advance technology forums, and 21 technical sessions with 69 scheduled paper presentations. The Monday and Tuesday lunch are being provided to registrants by sponsoring companies. Details of the technical program can be found at: http://domino.watson.ibm.com/iccd98/iccd98.nsf/Program.html The DEADLINE for EARLY CONFERENCE REGISTRATION is tomorrow, September 11, 1998!! You can register online at: https://secure.computer.org/ConferenceReg/Conference/ICCD98/register.htm or get the offline registration form from: http://domino.watson.ibm.com/iccd98/iccd98.nsf/confreg.html In past years hotel rooms in the Austin area have been filled quickly. It is recommended to make your HOTEL RESERVATION as soon as possible. The reservation deadline for getting the special ICCD rate at the conference hotel is also tomorrow, September 11, 1998. The reservation form can be found at: http://domino.watson.ibm.com/iccd98/iccd98.nsf/hotelreg.html I am looking forward to seeing you in Austin. Best regards, Andreas Kuehlmann (TPC ICCD'98) From pilz@ifi.unizh.ch Mon Sep 21 23:01:38 1998 +0200 Return-Path: Received: from mail.cs.ucr.edu by josef.ifi.unizh.ch with SMTP (PP) id <23201-0@josef.ifi.unizh.ch>; Mon, 21 Sep 1998 23:01:17 +0200 Received: from paix.ucr.edu (paix.ucr.edu [138.23.169.90]) by barrichello.ucr.edu (8.8.8/8.8.8) with ESMTP id OAA05421 for ; Mon, 21 Sep 1998 14:01:15 -0700 Received: (from givargis@localhost) by paix.ucr.edu (8.8.8/8.8.8) id OAA07748; Mon, 21 Sep 1998 14:00:12 -0700 Message-ID: <19980921140011.01763@paix.ucr.edu> Date: Mon, 21 Sep 1998 14:00:11 -0700 From: Tony Givargis To: codesign@ifi.unizh.ch Subject: 7th International Workshop on H/S Co-Design - CALL FOR PAPERS Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Mailer: Mutt 0.88 Status: RO X-Status: X-Keywords: X-UID: 39 7th International Workshop on Hardware/Software Co-Design CODES'99 Rome, Italy - May 3-5, 1999 http://www.cs.ucr.edu/codes99/ The CODES workshop is the major international forum for the presentation and exchange of ideas in the hardware/software co-design of embedded computing systems that include functionality mapped to both hardware and software processing components. Presentations and discussions address theoretical aspects, design methods, tools, and case studies. Areas of interest include, but are not limited to: * Computer-aided techniques for co-design: specification and modeling, design representation, simulation, synthesis, partitioning, estimation, formal verification, testing, design space exploration. * Software for co-design: software development environments, real-time operating systems, process scheduling, software synthesis, system integration, testbenches and testing, retargetable compilation. * Co-design architectures: distributed and multiprocessor architectures, hardware/software interfaces, prototyping approaches, emulation and debugging techniques, testing methods. * System development process: design methodology, concurrent engineering, design reuse, process management, intellectual property, system integration, case studies. The workshop's structure promotes active discussion among all participants in an informal setting, including short oral presentations of accepted papers followed by poster sessions for in-depth discussions. Paper submissions are due only a few months before the workshop, so that submissions may focus on the latest research. Publication of each accepted paper in the published workshop proceedings (by ACM SIGDA, in hardcopy, publicly-accessible web page, and CD-ROM compendium) is optional. Submission instructions: Submit one email message to codes99@cs.ucr.edu by January 8, 1999 with the following format: * Subject: CODES99 submission, Include-in-proceedings: {YES or NO}, Phone number of main contact, email addresses of all authors, URL of related work, number of pages in the paper, three key words describing the work, and then the paper itself in pdf (preferred) or postscript format (either attached or included in the email body itself). * The paper must be 5 pages or less, including figures and references, with a minimum font size of 9 pt, two-column format, as close as possible to camera ready. Please note that 5 pages is a hard limit. Submissions exceeding this limit will not be reviewed. It should be formatted for 8 inch by 11 inch paper (not A4 paper). Please note that larger-sized paper formats like A4 can cause significant printing difficulties in the U.S. * By submitting a paper, the author(s) agree that if the paper is accepted, to present the paper in person at the workshop, and if the paper is to be included in the proceedings, to prepare a final camera-ready version. * Proposals for group discussions may also be submitted. These should be 2 pages or less. * Notification of acceptance will be by February 24. Organizers: General Co-chairs Ahmed Amine Jerraya Luciano Lavagno System Level Synthesis Group Dipartimento di Elettronica TIMA Laboratory Politecnico di Torino 46 Avenue Felix Viallet Corso Duca degli Abruzzi 24 F-38031 Grenoble Cedex, FRANCE I-10129, Torino, ITALY Tel: +33 476 574 759 Tel: +39 11 564-4150 Fax: +33 476 473 814 Fax: +39 11 564-4099 Email: ahmed.jerraya@imag.fr Email: lavagno@polito.it Program Chair Frank Vahid Department of Computer Science University of California Riverside, CA 92521, USA Tel: +1 909 787-4710 Fax: +1 909 787-4643 Email: vahid@cs.ucr.edu Technical Program Committee Brian Bailey, Mentor Graphics, USA Tarek Ben-Ismail, HP Labs, Bristol, UK Gaetano Borriello, University of Washington, USA Joseph Buck, Synopsys, USA Raul Camposano, Synopsys, USA Giovanni De Micheli, Stanford University, USA Rolf Ernst, University of Braunschweig, D Daniel Gajski, University of California at Irvine, USA Rajesh Gupta, University of California at Irvine, USA Joerg Henkel, NEC, USA Ahmed Jerraya, TIMA, F Kayhan Kucukcakar, Escalade, USA Sanjaya Kumar, Honeywell, USA Luciano Lavagno, Politecnico di Torino, I Jan Madsen, Technical University of Denmark, DK Franz Rammig, C-Lab, Univ. of Paderborn, D Wolfgang Rosenstiel, University of Tubingen, D James Rowson, Cadence, USA Alberto Sangiovanni-Vincentelli, UC Berkeley, USA Miguel Santana, STMicroelectronics, F Don Thomas, Carnegie-Mellon University, USA Kees Vissers, Philips, NL Wayne Wolf, Princeton University, USA Hiroto Yasuura, Kyushu University, Japan Sponsored by: IEEE Computer Society, IEEE CAS, IFIP 10.5, ACM/SIGDA, ACM/SIGSOFT. From pilz@ifi.unizh.ch Thu Oct 1 09:17:04 1998 +0200 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <05562-0@josef.ifi.unizh.ch>; Thu, 1 Oct 1998 09:16:41 +0100 Return-Path: X-Received: from cs20.cs.nthu.edu.tw by josef.ifi.unizh.ch with SMTP (PP) id <29021-0@josef.ifi.unizh.ch>; Wed, 30 Sep 1998 07:12:40 +0100 X-Received: (from isss98@localhost) by cs.nthu.edu.tw (thcs.2/cs20) id NAA25136 for codesign@ifi.unizh.ch; Wed, 30 Sep 1998 13:37:59 +0800 (CST) From: isss98 Message-Id: <199809300537.NAA25136@cs.nthu.edu.tw> Subject: ISSS98: Final Program To: codesign@ifi.unizh.ch Date: Wed, 30 Sep 1998 13:37:59 +0800 (CST) X-Mailer: ELM [version 2.4ME+ PL34C (25)] MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit ReSent-Date: Thu, 1 Oct 1998 10:20:20 +0200 (MET DST) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: ISSS98: Final Program ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 40 11TH INTERNATIONAL SYMPOSIUM ON SYSTEM SYNTHESIS (ISSS) Hsinchu, Taiwan, R.O.C., December 2-4, 1998 Sponsored by the IEEE Computer Society DATC and the ACM SIGDA (http://www.cs.nthu.edu.tw/~isss98/) FINAL PROGRAM Tuesday, December 1, 1998 18:00 - 20:00 On-site Registration 19:00 - 21:00 Reception Wednesday, December 2, 1998 08:30 - 09:00 Open statement 09:00 - 10:00 Invite talk: Is IP Business Hype or Reality? Prof. D. D. Gajski, U. of California, Irvine, USA 10:00 - 10:30 Coffee break 10:30 - 11:30 Session 1: Code Generation and Optimization Issues 1.1 A Uniform Optimization Technique for Offset Assignment Problems Rainer Leupers, Fabian David; Dept. of Computer Science, Univ. of Dortmund 1.2 Code Generation for Compiled Bit-True Simulation of DSP Applications L. De Coster, M. Ade, R. Lauwereins, J.A. Peperstraete; Katholieke Univ. Leuven, Dept. ESAT, Belgium 1.3 Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture W.-K. Cheng, Y.-L. Lin; Dept. of CS, NTHU, Taiwan, R.O.C 11:30 - 12:00 Poster discussion 12:00 - 13:30 Lunch 13:30 - 14:30 Invite talk: Issues in Embedded DRAM Development and Applications; Dr. K.-S. Doris; Siemens Research and Devel, Germany 14:30 - 15:30 Session 2: IP Reuse and Language 2.1 A Processor Description Language Supporting Retargetable Multi-Pipeline DSP Program Development Tools C. Siska; Rockwell Semiconductor Systems, Inc. 2.2 Intellectual Property Re-use in Embedded System Co-design: an Indutrial Case Study E. Filippi, L. Lavagno, L. Licciardi, A. Montanaro, M. Paolini, R. Passerone, A. Sangiovanni-Vincentelli, M. Sgroi; CSELT, Italy. Dipartimento di Elettronica, Politecnico di Torino, Italy. Univ. of CA. at Berkeley, USA. 2.3 Incorporating Cores into System-Level Specification F. Vahid and T. Givargis; Dept. of Computer Science, Univ. of California, USA 15:30 - 16:00 Poster discussion and coffee break 16:00 - 16:30 Poster presentation P1 HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation R. Leupers; Dept. of Computer Science, Univ. of Dortmund P2 False Path Analysis based on a Hierarchical Control Representation A. A. Kountouris and C. Wolinski; IRISA - Institut de Recherche en Informatique et Systemes Aleatoires P3 Resource constrained Modulo Scheduling with Global Resource Sharing C. Jaeschke, R. Laur; Univ. of Bremen, Dept. 1, Institute of Electromagnetic Theory and Micro., Bremen/Germany. P4 Statistical Performance-Driven Module Binding in High-Level Synthesis H. Tomiyama, A. Inoue, and H. Yasuura; Dept. of Computer Science and Communication Eng., Graduate School of Information Science and Electrical Eng., Kyushu Univ., Japan P5 Concurrent Error Detection at Architectural Level C. Bolchini, W. Fornaciari, F. Salice, D. Sciuto; Cristiana Bolchini: Politecnico di Milano-Dipartimento di Elettronica e Informazione, Italy. P6 Communication and Interface Synthesis on a Rapid Prototyping Hardware/Software Codesign System Y.-T. Hwang, Y.-H. Wang; Dept. of Electronic Eng. NYU of Science & Technology Taiwan, R.O.C 16:30 - 17:30 Poster discussion 18:30 - 20:00 Dinner 20:00 - 22:00 Panel: ˇyIP-Based design: VIP (Very Important Process) or RIP(Rest in Peace)ˇz Thursday, December 3, 1998 09:00 - 10:00 Invite talk: Compiler Technology for Application-Specific Processors/Systems on Chips Prof. Monica Lam, Standford Univ., USA 10:00 - 10:30 Coffee break 10:30 - 11:30 Session 3: Application-Specific Synthesis Techniques 3.1 Application-Specific Heterogenous Multiprocessor Synthesis Using Differential-Evolution A. Rae, S. Parameswaran; Dept. of Computer Science and Electrical Eng. Univ. of Qu`ensland, Australia. 3.2 Proposal for unified system design meta flow in task- level and instruction-level design technology research for multi-media applications F. Catthoor, D. Verkest, E. Brockmeyer; IMEC, VSDM Division, Katholieke Univ. Leuven 3.3 Data-path Synthesis of VLIW Video Signal Processors Z. Wu, W. Wolf; Dept. of Electrical Eng., Princeton Univ., U.S.A. 11:30 - 12:00 Poster discussion 12:00 - 13:30 Lunch 13:30 - 14:30 Group Discussion 14:30 - 15:30 Session 4: Synchronization and Interface Issues 4.1 Synchronization Detection for Multi-Process Hierarchical Synthesis O Bringmann, W. Rosenstiel, D. Reichardt; FZI and Univ. of Tubingen, Germany 4.2 Integrating Communication Protocol Selection with Partitioning in Hardware/Software Codesign P. V. Knudsen and J. Madsen; Dept. of Information Technology, Technical Univ. of Denmark, Denmark 4.3 Interface Exploration for Reduced Power in Core-Based Systems T. Givargis, F. Vahid; Dept. of Computer Science, University of California, U.S.A. 15:30 - 16:00 Poster discussion and coffee break 16:00 - 17:00 Session 5: Instruction Encoding and Software Synthesis Techniques 5.1 Instruction Encoding Techniques for Area Minimization of Instruction ROM T. Okuma, H. Tomiyama, A. Inoue, E. Fajar, H. Yasuura Dept. of Computer Science and Communication Eng., Kyushu University, Japan 5.2 Application of Instruction Analysis/Synthesis Tools to x86's Functional Unit Alloation I.-J. Huang, P.-H. Xie; Institute of Computer and Information Eng., NSYSU Kaohsiung, Taiwan, R.O.C. 5.3 Memory Efficient Software Synthesis from Dataflow Graph W. Sung, Junedong Kim, Soonhoi Ha; Dept. of Computer Eng., Seoul National University, Korea 17:00 - 17:30 Poster discussion 17:30 - 18:30 General discussion session 19:00 - 21:00 Banquet Friday, December 4, 1998 09:00 - 10:00 Invite talk (TBA) 10:00 - 10:30 Coffee break 10:30 - 11:30 Session 6: Partitioning and Scheduling Techniques 6.1 A Tool Partitioning and Pipelined Scheduling of Hardware- Software Systems Karam S. Chatha and Ranga Vemuri; Laboratory for Digital Design Environments, Department of ECECS, University of Cincinnati 6.2 A Three-Step Approach to the Functional Partitioning of Large Behavioral Processes F. Vahid; Dept. of Computer Science, Univ. of California, U.S.A. 6.3 Fine-Grain, Incremental Rescheduling Via Architectural Retiming; S. Hassoun; Dept. of Electrical Eng. and Computer Science, Tufts University 11:30 - 12:00 Poster discussion 12:00 - 13:30 Lunch 13:30 - 16:30 Science-Based Industry Park Tour Saturday, December 5, 1998 Taipei City Tour Sunday, December 6, 1998 Tarako National Park Tour ISSS'98 Registration Form (Print or Type, one form for each registrant.) (If your payment is by credit card, please FAX the form to us. Thank you.) Please enter your session/paper number _________________ for authors. Advance Registration Deadline: October 25, 1998 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Any registration after Oct. 25, 1998 (postmark cut-off) will be charged the at-symposium rate. Please complete the information below. Payment with registration must be made in US or NT dollars and made payable to: Allen C.-H. Wu ^^^^^^^^^^^^^^ Account No. 036-16-0060160, ^^^^^^^^^^^^^^^^^^^^^^^^^^^ Chiao Tung Bank, Hsinchu Branch, Hsinchu, Taiwan. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Title : __Prof. __Dr. __Mr. __Ms. __Miss. __Mrs. Name : ____________________________________________ Last First Mid Affiliation : ____________________________________________ Address : ____________________________________________ ____________________________________________ ____________________________________________ Phone : ____________________________________________ Fax : ____________________________________________ E-mail : ____________________________________________ Special needs [ ] Vegetarian [ ] Other ________________ Before Oct. 25, 1998 | After Oct. 25, 1998 [ ]ACM/IEEE Member | [ ]US$320 [ ]NT$11,000 | [ ]US$380 [ ]NT$13,000 [ ]Non-member | [ ]US$400 [ ]NT$13,500 | [ ]US$400 [ ]NT$13,500 [ ]Full-time Student | [ ]US$150 [ ]NT$ 5,000 | [ ]US$200 [ ]NT$6,500 Total Amount Enclosed : US$ __________ NT$ ___________ (or transferred to the above mentioned account) ACM/IEEE Membership # : _________________ (reqd. if registering at ACM/IEEE rates) I __enclose __Traver's check __ Money order I __use Credit card : __Visa __Master Card (Do not accept American Express). Card No. ___________ - ___________ - ___________ - ___________ Expiry date: __________________________________________________ Name as it appears on card: ___________________________________ Passport no./ROC citizen ID no.:_______________________________ Signature: ___________________________________________________ Date: ________________________________________________________ Cancellation Policy: No refunds will be made on cancellations received after Nov. 20, 1998. Cancellations received before Nov. 20 are subject to a 20% processing fee. Hotel Reservation Form Please type or print. Title : __Prof. __Dr. __Mr. __Ms. __Miss. __Mrs. Name : _______________________________________ Last First Mid Affiliation: _______________________________________ Address : _______________________________________ _______________________________________ _______________________________________ Phone : _______________________________________ Fax : _______________________________________ E-mail : _______________________________________ Member of IEEE/ACM Member No.:____________________ HOTEL RESERVATION Hotel Single Twin __Chinatrust Hotel __NT$2,970 __NT$3,330 __Shin Yuan Park Hotel __NT$2,430 __NT$3,120 (include service charge and tax.) Check-in date: ___________ Check-in time: _________ Check-out date: ___________ Number of nights: _____ TRANSPORTATION One way, between the CKS Airport and Hotel: NT$1,300 Flight Number: ___________ Arrival Time: ____________ METHOD OF PAYMENT Pay to the hotel when you check out with cash, traveler's check, or credit card. No personal check, please. NOTE: The room rates and availability are guaranteed for the period of Nov. 29 - Dec. 6, 1998, only if your reservation form is received before Oct. 25, 1998. Please send this form to the hotel you choose: Chinatrust Hotel: 106 Chung Yang Rd., Hsinchu, Taiwan 300 Fax: +886-3-5269244; Tel: +886-3-5263181 Shin Yuan Park Hotel: 11 Ta Tung Rd., Hsinchu, Taiwan 300 Fax: +886-3-5260522; Tel: +886-3-5226868 Tour Reservation Form Tour 1.: Taipei City Tour Date: Dec. 5, 1998 (Sat.) Fare: NT$1,750(Includes: 1 lunch) 1. National Palace Museum 2. Martyr's Shrine 3. Chinese Temple 4. Chiang Kai-Shek Memorial Hall 5. Dr. Sun Y. S. Memorial Hall 6. Presidential Office (Pass by) 7. Handicraft Center Tour 2.: Tarako National Park (Hualien) Date: Dec. 6, 1998 (Sun.) Fare: NT$4,200 (Including: Round-trip air ticket and lunch) (Passport needed for enplaning) Itinerary: Pick-up from hotel -> Transfer to Taipei Airport -> Arrive at Hualien -> Enbus for Tarako Groge Gateway ->Eternal-Spring Shrine -> Swallow Caves -> Tunnel of Nine Turns -> TienhsiangLodge -> Marble factory -> Enplane for Taipei -> Transfer to hotel Please type or print. Sex: __F __M Name : _______________________________________________ Last First Mid Passprot No.: ____________________________________ Birth Date : ____________________________________ Nationality : ____________________________________ Signature : ____________________________________ Tour Selection: please indicate your choice(s) ___ Taipei City Tour ____Tarako National Park (Hualien) Total amount: NT$______________________ Payment: By cash or traverler's check in NTD to the travel agent at the conference site. Please send this form to (before Oct. 25, 1998) Trans Continental Travel Service Co., Ltd. 4F, No. 21, Lane 45, Sec. 2, Chung-San N. Rd., Taipei, Taiwan. Fax: +886-2-25230002; +886-2-26946057 Tel: +886-2-25233131 From pilz@ifi.unizh.ch Tue Oct 6 15:41:33 1998 +0200 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <00757-0@josef.ifi.unizh.ch>; Tue, 6 Oct 1998 15:41:24 +0100 Return-Path: X-Received: from pol88b.polito.it by josef.ifi.unizh.ch with SMTP (PP) id <13163-0@josef.ifi.unizh.ch>; Tue, 6 Oct 1998 08:38:46 +0100 X-Received: from chiusella.polito.it.polito.it (chiusella.polito.it) by polito.it (PMDF V4.2-15 #3020) id <01J2N5TV6SC08XBAZF@polito.it>; Tue, 6 Oct 1998 07:57:24 GMT+1 X-Received: by chiusella.polito.it.polito.it (4.1/SMI-4.1) id AA06324; Tue, 6 Oct 98 06:57:24 +0100 Date: Tue, 06 Oct 1998 06:57:24 +0100 From: tttc@chiusella.polito.it (Paolo Prinetto) Subject: IEEE TTTC - ETW'99 : IEEE European Test Workshop To: pilz@ifi.unizh.ch Message-id: <9810060557.AA06324@chiusella.polito.it.polito.it> X-Envelope-to: pilz@ifi.unizh.ch Content-transfer-encoding: 7BIT Apparently-To: PILZ Markus ReSent-Date: Tue, 6 Oct 1998 15:36:33 +0200 (MET DST) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: IEEE TTTC - ETW'99 : IEEE European Test Workshop ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 41 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % IEEE Computer Society % Test Technology Technical Committee % % % .... FOR YOUR INFORMATION.... % % A free service of the Technical Meeting Group % % % This message contains public information, only, and % the receiver is allowed, and invited, to copy it and % distribute it further. % % % For more information contact % or visit http://www.computer.org/tab/tttc/ % % If you would like to be removed from this mailing list, % please send an e-mail to % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% IEEE European Test Workshop Steigenberger Inselhotel Constance, Germany May 25th - 28th University of Stuttgart Call for Contributions The IEEE European Test Workshop is a well recognized forum for presenting and discussing trends and hot topics in the area of circuit and system testing. In 1999, the workshop will take place on an island in the Lake of Constance, nearby the Blackwood Forest in Germany and the Alps of Switzerland and Austria. The Workshop provides the ideal environment for cross-fertilizing industrial and academic experiences and needs. You are all invited to submit your contributions to ETW99. The topics include but are not limited to: Mixed-Signal and Analog Testing Automatic Test Equipment (ATE) Test Quality and Test Economics Application-Driven System Test Thermal and Low Power Testing ATPG and Fault Simulation Test Automation Synthesis for Testability DFT and BIST Online Test Defect Analysis IDDQ Testing The program committee invites original presentations which should include a list of keywords and contain at least 1000 and at most 5000 words. Submit preferably a postscript file to the e-mail address below or five copies of the paper. If you do not receive an email acknowledgement within one week you should contact the General Chair again. Also identify a contact author and include a complete mailing address, phone number, fax number and E-mail address. For the first time, ETW will publish formal proceedings of selected papers after the workshop event. Based on the presentations, the program committee will encourage some authors to provide a full version of their contribution to be included in workshop proceedings. Important deadlines: Submission deadline: February 12th, 1999 Notification of acceptance: March 20th, 1999 General information and paper submission: Hans-Joachim Wunderlich University of Stuttgart Computer Architecture Lab Breitwiesenstra?e 20--22 70565 Stuttgart Tel.: ++49-711-7816391 Fax: ++49-711-7816288 Email: etw99@informatik.uni-stuttgart.de For further information, please visit the ETW99 web page at http://www.ra.informatik.uni-stuttgart.de/ETW99/ The ETW99 is co-sponsored by the IEEE Computer Society Test Technology Technical Committee and the University of Stuttgart. General Chair H.-J. Wunderlich - U of Stuttgart (D) General Vice-Chair J. P. Teixeira - INESC (P) Program Chair C. Landrault - LIRMM (F) Program Vice-Chair H. Manhaeve - KHBO (B) Publicity Chair B. Becker - U of Freiburg (D) Panel Chair P. Prinetto - Politecnico di Torino (I) Industrial Relations Chair B. Bennetts - Bennetts Assoc. (UK) Local Arrangement Chair C. Honikel - U of Stuttgart (D) Finance Chair R. Dorsch - U of Stuttgart (D) Program Committee: E.J. Aas - NTNU Trondheim (N) K.J. Antreich - TU Munchen (D) K. Baker - Philips (NL) B. Becker - U of Freiburg (D) B. Bennetts - Bennetts Assoc. (UK) G. Carlsson - Ericsson (S) B. Courtois - TIMA CMP (F) M. Croft - Mentor Graphics (UK) W. Daehn - SICAN GmbH (D) C. Ellingham - Synopsys (USA) J. Figueras - U of Catalunya (SP) H. Fujiwara - NAIST (J) S. Hellebrand - U of Stuttgart (D) M. Hirech - Synopsys (USA) J. Hlavicka - Czech Technical U (Cz) A. Hlawiczka - U of Gliwice (PL) J.L. Huertas - U of Sevilla (SP) H. Kerkhoff - U of Twente (NL) C. Landrault, LIRMM (F) M. Lubaszewski - UFRGS (Br) H. Manhaeve - KHBO (B) J. Mucha - U of Hannover (D) M. Nicolaidis - TIMA CMP (F) M. Ohletz - Alcatel (B) P. Olivo - U di Ferrara (I) A. Paschalis - NCSR (GR) Z. Peng - U of Linkoping (S) P. Prinetto - Politecnico di Torino (I) M. Renovell - LIRMM (F) C. Robach - ESISAR (F) A. Rubio - U of Catalunya (SP) M. Sachdev - Philips (NL) R. Segers - Philips Semicond. (NL) M. Sonza Reorda, Polit. di Torino (I) J.P. Teixeira - INESC (P) R. Ubar - U of Tallinn (EE) R. Wagner - Bosch GmbH (D) T.W. Williams - Synopsys (USA) H.-J. Wunderlich, U of Stuttgart (D) V. Yarmolik - U of Minsk (BY) Y. Zorian - LogicVision (USA) %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % Paolo PRINETTO % % IEEE Computer Society % Test Technology Technical Committee (Vice Chair) % % Politecnico di Torino % Dip. di Automatica e Informatica % Corso Duca degli Abruzzi 24 % I-10129 Torino TO % Italy % % Tel: + 39 11 564.7007 % Fax: + 39 11 564.7099 % % E-mail: Paolo.Prinetto@polito.it % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% From pilz@ifi.unizh.ch Tue Oct 6 20:34:32 1998 +0200 Date: Tue, 6 Oct 1998 20:34:31 +0200 (MET DST) From: Markus Pilz To: codesign@ifi.unizh.ch Subject: Job Opportunity at the University of Paderborn, Germany Message-ID: MIME-Version: 1.0 Content-Type: MULTIPART/MIXED; BOUNDARY="-559023410-342241519-907698871=:361" Status: RO X-Status: X-Keywords: X-UID: 42 ---559023410-342241519-907698871=:361 Content-Type: TEXT/PLAIN; charset=US-ASCII Job Opportunity at the University of Paderborn, Germany, in Computer Engineering, Dept. of EE Academic Research Position ========================== The Computer Engineering Laboratory associated with the Department of Electrical Engineering of the University of Paderborn has its research focus in modeling, simulation, design and rapid prototyping of electronic systems comprising as well hardware as software: The corresponding research topics are related to Hardware/Software-Codesign, Embedded Real-Time Systems, and Massively Parallel Computing, see http://www-date.uni-paderborn.de We are currently seeking several candidates for research in projects related to the above research fields. Applications are welcome but not restricted to be submitted within 6 weeks after this posting. The candidate which should have a degree in either Electrical Engineering or Computer Science will be given the possibility to pursue a PhD program (or a postdoc program for a candidate having already a PhD degree) for further qualification (e.g. Habilitation). Contract and payment is regulated by BAT. In case you are interested in joining our young research laboratory while enjoying the great infrastructure in electrical engineering and computer science in Paderborn and the challenging field of research, please send your questions or ready application (resume including cv, photo, diploma, grades, list of publications, recommendations, etc.) to Prof. Dr.-Ing. J. Teich Computer Engineering, Univ. of Paderborn Warburgerstr. 100 D-33100 Paderborn, Germany Tel: +49 (0)5251 60 3002 Fax: +49 (0)5251 60 3424 e-mail: teich@date.uni-paderborn.de WWW: Content-Description: job description (postscript) Content-Disposition: attachment; filename="job.ps" [deleted] ---559023410-342241519-907698871=:361-- From pilz@ifi.unizh.ch Wed Oct 7 20:30:46 1998 +0200 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <18033-0@josef.ifi.unizh.ch>; Wed, 7 Oct 1998 20:30:37 +0100 Return-Path: X-Received: from pol88b.polito.it by josef.ifi.unizh.ch with SMTP (PP) id <17885-0@josef.ifi.unizh.ch>; Wed, 7 Oct 1998 20:26:38 +0100 X-Received: from chiusella.polito.it.polito.it (chiusella.polito.it) by polito.it (PMDF V4.2-15 #3020) id <01J2P9OUDSRK8XE3QC@polito.it>; Wed, 7 Oct 1998 20:09:29 GMT+1 X-Received: by chiusella.polito.it.polito.it (4.1/SMI-4.1) id AA19253; Wed, 7 Oct 98 19:09:24 +0100 Date: Wed, 07 Oct 1998 19:09:24 +0100 From: tttc@chiusella.polito.it (Paolo Prinetto) Subject: IEEE TTTC - MTDT'99: Int'l Workshop on Memory Technology, Design, and Testing To: pilz@ifi.unizh.ch Message-id: <9810071809.AA19253@chiusella.polito.it.polito.it> X-Envelope-to: pilz@ifi.unizh.ch Content-transfer-encoding: 7BIT Apparently-To: PILZ Markus ReSent-Date: Wed, 7 Oct 1998 20:26:27 +0200 (MET DST) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: IEEE TTTC - MTDT'99: Int'l Workshop on Memory Technology, Design, and Testing ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 43 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % IEEE Computer Society % Test Technology Technical Committee % % % .... FOR YOUR INFORMATION.... % % A free service of the Technical Meeting Group % % % This message contains public information, only, and % the receiver is allowed, and invited, to copy it and % distribute it further. % % % For more information contact % or visit http://www.computer.org/tab/tttc/ % % If you would like to be removed from this mailing list, % please send an e-mail to % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% CALL FOR PAPERS 1999 IEEE International Workshop on Memory Technology, Design, and Testing August 9-10, 1999, Fairmont Hotel, San Jose, California, U.S.A. Sponsored by the IEEE Computer Society, the Technical Committee on Test Technology, and the Technical Committee on VLSI. Also held in cooperation with the IEEE Solid-State Circuits Society. --------------------------- The workshop will include all aspects of memory design, process technologies, and testability related topics. Memory circuit designs, cell structures, fabrication processes, design architectures and related testing and verification methods for SRAM, DRAM, Flash and non-volatile memories, EPROM, EEPROM, embedded memories, logic-enhanced and FIFO memories, 3-D memories, and content addressable memories. Representative topics are: o High-speed, innovative memory designs o System-on-a-chip designs with large memories o Embedded memories, memory cores, merged memory-logic systems o Multimegabit commodity SRAMs and DRAMs o Multiported and multibuffered memories o Logic-enhanced and programmable memories o Application-specific memories o CMOS, BiCMOS, and bipolar designs o Memory fault modeling and test generation o Built-in self-test and testable designs for memories o Concurrent checking and transparent testing o Memory failure and yield analysis o Fault isolation, reconfiguration, and repair o Quality and reliability issues o Space applications and radiation hardening issues o Low-power memory design For consideration for the regular technical program, please submit five (5) copies of an *extended abstract* of about one thousand words or a *full paper* describing original work on any aspect of memory technology, design, and testing to the *Program Chair*. Submissions should include the full names and affiliations of all authors and contact information, and should indicate the intended presenter. Submissions are due February 1, 1999. Acceptance notification will be on March 15, 1999. Final papers will be due May 21, 1999. Presentation time slots will average 30 minutes. Proposals for *tutorials* within the regular program should be submitted to the Vice Chair as soon as possible. --------------------------- GENERAL CHAIR Rochit Rajsuman Advantest America R&D Center 3201 Scott Blvd. Santa Clara, CA 95054, USA +1-408-727-2222; fax 727-5764 r.rajsuman@advantest.com VICE CHAIR Bruce Cockburn Elec. and Comp. Engg. MS 238-CEB University of Alberta Edmonton, AB T6G 2G7, Canada +1-403-492-3827; fax 492-1811 cockburn@ee.ualberta.ca PROGRAM CHAIR Thomas Wik LSI Logic, MS E-191 1501 McCarthy Blvd. Milpitas, CA 95035, USA +1-408-954-4471; fax: 433-7353 trw@lsil.com LOCAL ARRANGEMENTS Craig Soldat Hewlett-Packard Co. 351 East Evelyn Ave. San Jose, CA 95035, USA +1-415-694-3499 craig_soldat@hp.com PUBLICITY CHAIR Xiaoling Sun Elec. and Comp. Engg. MS 238-CEB University of Alberta Edmonton, AB T6G 2G7, Canada +1-613-763-4459; fax: 763-7241 xsun@ee.ualberta.ca STEERING COMMITTEE Rochit Rajsuman, Chair Advantest America R&D Center Bernard Courtois, TIMA Grenoble, France Ad van de Goor, Delft University of Technology, Delft, The Netherlands Yervant Zorian, LogicVision San Jose CA, USA PROGRAM COMMITTEE R. Dean Adams, IBM Richard Chrusciel, Advantest America Duncan Elliott, University of Alberta Robert Evans, MOSAID Gary Fleeman, Advantest America Robert Gibbins, Nortel Ad van de Goor, Delft University of Techology Adam Kablanian, Virage Logic David Lepejian, HPL Jim Lewandowski, Bell Labs Fabrizio Lombardi, Northeastern University Marc Loranger, Credence Systems Sharon Murray, Medtronic Micro-Rel Betty Prince, Memory Strategies International Shiva Ramesh, LSI Logic Manoj Sachdev, University of Waterloo Konrad Schoenemann, Siemens AG %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % Paolo PRINETTO % % IEEE Computer Society % Test Technology Technical Committee (Vice Chair) % % Politecnico di Torino % Dip. di Automatica e Informatica % Corso Duca degli Abruzzi 24 % I-10129 Torino TO % Italy % % Tel: + 39 11 564.7007 % Fax: + 39 11 564.7099 % % E-mail: Paolo.Prinetto@polito.it % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% From pilz@ifi.unizh.ch Thu Oct 8 18:40:52 1998 +0200 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <21024-0@josef.ifi.unizh.ch>; Thu, 8 Oct 1998 18:40:31 +0100 Return-Path: X-Received: from viper.ics.ele.tue.nl by josef.ifi.unizh.ch with SMTP (PP) id <20561-0@josef.ifi.unizh.ch>; Thu, 8 Oct 1998 18:32:31 +0100 X-Received: from akebono.ics.ele.tue.nl (akebono.ics.ele.tue.nl 131.155.40.19) by viper.ics.ele.tue.nl (8.8.7/1.57) id SAA24986; Thu, 8 Oct 1998 18:32:28 +0200 (METDST) X-Received: by akebono.ics.ele.tue.nl (VMailer, from userid 8003) id 8B5142085; Thu, 8 Oct 1998 18:29:49 +0200 (METDST) From: lech@ics.ele.tue.nl Sender: lech@ics.ele.tue.nl Subject: EUROMICRO'99 DSD Workshop, Call for Papers Reply-To: lech@ics.ele.tue.nl Message-Id: <19981008162949.8B5142085@akebono.ics.ele.tue.nl> Date: Thu, 8 Oct 1998 18:29:49 +0200 (METDST) ReSent-Date: Thu, 8 Oct 1998 18:36:20 +0200 (MET DST) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: EUROMICRO'99 DSD Workshop, Call for Papers ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 44 _________________________________________________________________ We apologize if you receive multiple copies of this message. Please, feel free to distribute it to interested persons. _________________________________________________________________ ***************************************************************** * EUROMICRO'99 * * 25th Anniversary EUROMICRO Conference * * Workshop on Digital System Design * * Milan, Italy, September 8th-10th, 1999 * ***************************************************************** Dear Colleague, On behalf of both the EUROMICRO Association and the Organizing Committee of the EUROMICRO'99 Conference, I cordially invite you to submit papers and attend the 25th Anniversary EUROMICRO Conference, taking place in Milan, Italy, September 8th-10th, 1999. Building on a more than twenty-year lasting successful history of the EUROMICRO Association and EUROMICRO Conferences, we have introduced a new multiple workshop structure of the Conferences. After a great success of the EUROMICRO'98 Conference, we are continuing with this multiple workshop structure. The 25th Anniversary EUROMICRO'99 Conference solicits the submission of papers for the following workshops: · Digital System Design: Architectures Methods and Tools · Dependable Computing Systems · Software Process and Product Improvement · Multimedia and Telecommunication · Music Technology and Audio Processing There will be many special events during this Silver Anniversary Conference. Two of them of a particular interest are perhaps the following: · "Back to the Future: Microprocessors for the 21st Century" - five keynote speakers from the top microprocessor companies will reveal their plans for future architectures, and · "Music Technology: Live and Loud" - a number of concerts will be given with use of the recent music technology and a conference CD will be produced. The EUROMICRO Workshop on Digital System Design: Architectures Methods and Tools was the largest and a very successful workshop of the EUROMICRO'98 Conference. The mission of the Digital System Design Workshop is to be the superior-quality discussion forum of the state-of-the-art research, development and applications for the computer system architecture and design automation communities. The Workshop addresses both architectures and implementations of (embedded) computer systems as well as efficient design methods and tools. Please, find below the call for papers of the Digital System Design Workshop and the http links to the additional up-to-date information on the Workshop and EUROMICRO'99 Conference. I am looking forward to see you at the EUROMICRO'99 Conference, Lech Jozwiak, Member of the Board of Directors of the EUROMICRO Association Program Chair of the EUROMICRO Workshop on Digital System Design _______________________________________________________________________________ EUROMICRO'99 EUROMICRO WORKSHOP on DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS Milan, Italy, September 8 - 10, 1999 _______________________________________________________________________________ CALL FOR PAPERS The workshop on Digital System Design addresses both architectures and implementations of (embedded) computer systems as well as efficient design methods and tools. It is a discussion forum of the state-of-the-art research, development and applications for the computer system architecture and design automation communities. TOPICS OF INTEREST include but are not limited to: CPU and memory architectures: arithmetic and logic units, co-processors, pipelining, superscalarity, cache, MMU. Special architectures: DSP, ASIPs, graphic and image processors, custom computing machines, processing arrays and FPGAs, reconfigurable structures, dependable structures. Specification and modeling: (hardware/software) system specification and modeling, system and hardware description languages, component modeling. Validation: simulation, emulation, prototyping and testing at the system, RT and logic level; multilevel- and co-simulation; formal verification. Synthesis: system on chip design; system, hardware-software, high-level, RT-level and logic synthesis; intellectual property and design reuse; synthesis for low-power, speed and testability; system, hardware/software and logic partitioning. SUBMISSION OF PAPERS Prospective authors are encouraged to submit by Internet or to e-mail PostScript version of their full paper to the program chairman. If electronic submission is not possible, four copies of the full paper should be sent by post. The paper should not exceed 4000 words and include an abstract of up to 150 words. The title page should clearly show the name, mailing address, the e-mail address and the fax number of the author to contact as well as the topic areas of the submitted paper. The following signed statement should be included on the title page: All necessary clearances have been obtained for the publication of this paper. If accepted, the author(s) will prepare the final camera-ready manuscript in time for inclusion in the proceedings, and will personally present the paper at the workshop. The program committee will decide for each accepted paper if it will be presented in a long (30 min.) or short (15 min.) presentation or as a poster. The long and short presentation papers 8 pages will be assigned and the poster papers 4 pages will be assigned in the proceedings. Papers exceeding 8 pages will be charged NLG 100 per page in excess. The proceedings will be published by the IEEE Computer Society. IMPORTANT DATES * Deadline for submission: February 28, 1999 * Notification of acceptance: April 30, 1999 * Deadline for final version: June 15, 1999 SPECIAL SESSIONS, PANELS AND TUTORIALS Proposals of special sessions, panels and tutorials are welcome. Please send suggestions to the program chairman before the paper submission deadline. GENERAL INFORMATION Milan is located in North Italy close to Alps. It has convenient direct flight connections with many European and other airports. It has also train connections with many European towns. ADDITIONAL UP-TO-DATE INFORMATION http://www.ics.ele.tue.nl/DSD-99 GENERAL INFORMATION ON EUROMICRO'99 CONFERENCE http://www.amp.york.ac.uk/external/milan/web/welcome/front.htm _______________________________________________________________________________ REFERENCE ADDRESSES Program Chair: Lech Józwiak Eindhoven University of Technology, Faculty of Electrical Engineering P.O. Box 513, EH 10.25 5600 MB Eindhoven, The Netherlands Tel: +31.40.2473645 Fax: +31.40.2433066 e-mail: LECH@ics.ele.tue.nl Steering Committee: L. Józwiak Program Chair, Eindhoven U. of Tech. (NL) K. Kuchcinski Past Program Chair, Linköping U. (S) A. Nunez Deputy Program Chair, U. of Las Palmas (E) Organizing Chair: Mariagiovanna Sami Department of Electronics and Inform. Politecnico di Milano Piazza Leonardo da Vinci 32, I-20133 Milano, Italy Tel: +39 2 2399 3516 Fax: +39 2 2399 3411 e-mail: sami@elet.polimi.it Deputy Organizing Chair: N. Scarabottolo, Pol. di Milano (I) _______________________________________________________________________________ Program Committee M. Anido, U. of Rio de Janeiro (BR) S. Baranov, Ben-Gurion U. (IL) R. Drechsler, A-L U. Freiburg (D) N. Dutt, U. of Calif., Irvine (USA) P. Eles, U. of Timisoara (RO) M. Fernandez, U. Complutense (E) M. Glesner, Darmstadt U. of Tech. (D) A. Gonzalez, U. Pol. De Catalunya (E) E. Gramatová, Slovak Ac. of Sci. (SLO) L. Józwiak, Eindhoven U. of Tech. (NL) K. Judmann, U. of Vienna (A) K. Kuchcinski, Linköping U. (S) L. Lindh, Mälardalen U. (S) T. Luba, Warsaw U. of Tech. (PL) J. Madsen Tech. Univ. of Denmark (DK) A. Nunez, U. of Las Palmas (E) A. Paschalis, Inst. of Inf. & Telec.(Gr) A. Pawlak, IRESTE, Nantes (F) M. Perkowski, Portland St. U. (USA) A. Postula, U. of Queensland (AU) B. Rouzeyre, U. Montpellier II (F) M. Sami, Pol. di Milano (I) T. Sasao, Kyushu Ins. of Techn. (J) G. Saucier, INPG/CSI (F) N. Scarabottolo, Pol. di Milano (I) H. Selvaraj, Monash U. (AU) J. Sosnowski, Warsaw U. of Tech. (PL) M. Stevens, Eindhoven U. (NL) D. Tabak, George Mason U. (USA) F. Vajda, KFKI-MSZKI (H) M. Valero, U. Pol. de Catalunya (E) K. Waldschmidt, J. W. Goethe U. (D) H. Yasuura, Kyushu U. (J) From pilz@ifi.unizh.ch Wed Oct 14 18:05:46 1998 +0200 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <22732-0@josef.ifi.unizh.ch>; Wed, 14 Oct 1998 18:05:35 +0100 Return-Path: X-Received: from cs20.cs.nthu.edu.tw by josef.ifi.unizh.ch with SMTP (PP) id <26099-0@josef.ifi.unizh.ch>; Tue, 13 Oct 1998 10:27:44 +0100 X-Received: (from isss98@localhost) by cs.nthu.edu.tw (thcs.2/cs20) id QAA25173 for codesign@ifi.unizh.ch; Tue, 13 Oct 1998 16:22:52 +0800 (CST) From: isss98 Message-Id: <199810130822.QAA25173@cs.nthu.edu.tw> Subject: NEWs: ISSS98: Final Program To: codesign@ifi.unizh.ch Date: Tue, 13 Oct 1998 16:22:52 +0800 (CST) X-Mailer: ELM [version 2.4ME+ PL34C (25)] MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit ReSent-Date: Wed, 14 Oct 1998 18:05:26 +0200 (MET DST) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: NEWs: ISSS98: Final Program ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 45 11TH INTERNATIONAL SYMPOSIUM ON SYSTEM SYNTHESIS (ISSS) Hsinchu, Taiwan, R.O.C., December 2-4, 1998 Sponsored by the IEEE Computer Society DATC and the ACM SIGDA (http://www.cs.nthu.edu.tw/~isss98/) FINAL PROGRAM Tuesday, December 1, 1998 18:00 - 20:00 On-site Registration 19:00 - 21:00 Reception Wednesday, December 2, 1998 08:30 - 09:00 Open statement 09:00 - 10:00 Invite talk: Is IP Business Hype or Reality? D. D. Gajski, U. of California, Irvine, USA 10:00 - 10:30 Coffee break 10:30 - 11:30 Session 1: Code Generation and Optimization Issues 1.1 A Uniform Optimization Technique for Offset Assignment Problems Rainer Leupers, Fabian David; Dept. of Computer Science, Univ. of Dortmund 1.2 Code Generation for Compiled Bit-True Simulation of DSP Applications L. De Coster, M. Ade, R. Lauwereins, J.A. Peperstraete; Katholieke Univ. Leuven, Dept. ESAT, Belgium 1.3 Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture W.-K. Cheng, Y.-L. Lin; Dept. of CS, NTHU, Taiwan, R.O.C 11:30 - 12:00 Poster discussion 12:00 - 13:30 Lunch 13:30 - 14:30 Invite talk: Issues in Embedded DRAM Development and Applications; K.-S. Doris; Siemens Research and Devel, Germany 14:30 - 15:30 Session 2: IP Reuse and Language 2.1 A Processor Description Language Supporting Retargetable Multi-Pipeline DSP Program Development Tools C. Siska; Rockwell Semiconductor Systems, Inc. 2.2 Intellectual Property Re-use in Embedded System Co-design: an Indutrial Case Study E. Filippi, L. Lavagno, L. Licciardi, A. Montanaro, M. Paolini, R. Passerone, A. Sangiovanni-Vincentelli, M. Sgroi; CSELT, Italy. Dipartimento di Elettronica, Politecnico di Torino, Italy. Univ. of CA. at Berkeley, USA. 2.3 Incorporating Cores into System-Level Specification F. Vahid and T. Givargis; Dept. of Computer Science, Univ. of California, USA 15:30 - 16:00 Poster discussion and coffee break 16:00 - 16:30 Poster presentation P1 HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation R. Leupers; Dept. of Computer Science, Univ. of Dortmund P2 False Path Analysis based on a Hierarchical Control Representation A. A. Kountouris and C. Wolinski; IRISA - Institut de Recherche en Informatique et Systemes Aleatoires P3 Resource constrained Modulo Scheduling with Global Resource Sharing C. Jaeschke, R. Laur; Univ. of Bremen, Dept. 1, Institute of Electromagnetic Theory and Micro., Bremen/Germany. P4 Statistical Performance-Driven Module Binding in High-Level Synthesis H. Tomiyama, A. Inoue, and H. Yasuura; Dept. of Computer Science and Communication Eng., Graduate School of Information Science and Electrical Eng., Kyushu Univ., Japan P5 Concurrent Error Detection at Architectural Level C. Bolchini, W. Fornaciari, F. Salice, D. Sciuto; Cristiana Bolchini: Politecnico di Milano-Dipartimento di Elettronica e Informazione, Italy. P6 Communication and Interface Synthesis on a Rapid Prototyping Hardware/Software Codesign System Y.-T. Hwang, Y.-H. Wang; Dept. of Electronic Eng. NYU of Science & Technology Taiwan, R.O.C 16:30 - 17:30 Poster discussion 18:30 - 20:00 Dinner 20:00 - 22:00 Panel: ˇyIP-Based design: VIP (Very Important Process) or RIP(Rest in Peace)ˇz Thursday, December 3, 1998 09:00 - 10:00 Invite talk: Compiler Technology for Application-Specific Processors/Systems on Chips Monica Lam, Standford Univ., USA 10:00 - 10:30 Coffee break 10:30 - 11:30 Session 3: Application-Specific Synthesis Techniques 3.1 Application-Specific Heterogenous Multiprocessor Synthesis Using Differential-Evolution A. Rae, S. Parameswaran; Dept. of Computer Science and Electrical Eng. Univ. of Qu`ensland, Australia. 3.2 Proposal for unified system design meta flow in task- level and instruction-level design technology research for multi-media applications F. Catthoor, D. Verkest, E. Brockmeyer; IMEC, VSDM Division, Katholieke Univ. Leuven 3.3 Data-path Synthesis of VLIW Video Signal Processors Z. Wu, W. Wolf; Dept. of Electrical Eng., Princeton Univ., U.S.A. 11:30 - 12:00 Poster discussion 12:00 - 13:30 Lunch 13:30 - 14:30 Group Discussion 14:30 - 15:30 Session 4: Synchronization and Interface Issues 4.1 Synchronization Detection for Multi-Process Hierarchical Synthesis O Bringmann, W. Rosenstiel, D. Reichardt; FZI and Univ. of Tubingen, Germany 4.2 Integrating Communication Protocol Selection with Partitioning in Hardware/Software Codesign P. V. Knudsen and J. Madsen; Dept. of Information Technology, Technical Univ. of Denmark, Denmark 4.3 Interface Exploration for Reduced Power in Core-Based Systems T. Givargis, F. Vahid; Dept. of Computer Science, University of California, U.S.A. 15:30 - 16:00 Poster discussion and coffee break 16:00 - 17:00 Session 5: Instruction Encoding and Software Synthesis Techniques 5.1 Instruction Encoding Techniques for Area Minimization of Instruction ROM T. Okuma, H. Tomiyama, A. Inoue, E. Fajar, H. Yasuura Dept. of Computer Science and Communication Eng., Kyushu University, Japan 5.2 Application of Instruction Analysis/Synthesis Tools to x86's Functional Unit Alloation I.-J. Huang, P.-H. Xie; Institute of Computer and Information Eng., NSYSU Kaohsiung, Taiwan, R.O.C. 5.3 Memory Efficient Software Synthesis from Dataflow Graph W. Sung, Junedong Kim, Soonhoi Ha; Dept. of Computer Eng., Seoul National University, Korea 17:00 - 17:30 Poster discussion 17:30 - 18:30 General discussion session 19:00 - 21:00 Banquet Friday, December 4, 1998 09:00 - 10:00 Invite talk: (Subject: TBA) Min Wu, Maronix International. Co. Ltd. 10:00 - 10:30 Coffee break 10:30 - 11:30 Session 6: Partitioning and Scheduling Techniques 6.1 A Tool Partitioning and Pipelined Scheduling of Hardware- Software Systems Karam S. Chatha and Ranga Vemuri; Laboratory for Digital Design Environments, Department of ECECS, University of Cincinnati 6.2 A Three-Step Approach to the Functional Partitioning of Large Behavioral Processes F. Vahid; Dept. of Computer Science, Univ. of California, U.S.A. 6.3 Fine-Grain, Incremental Rescheduling Via Architectural Retiming; S. Hassoun; Dept. of Electrical Eng. and Computer Science, Tufts University 11:30 - 12:00 Poster discussion 12:00 - 13:30 Lunch 13:30 - 16:30 Science-Based Industry Park Tour Saturday, December 5, 1998 Taipei City Tour Sunday, December 6, 1998 Tarako National Park Tour ISSS'98 Registration Form (Print or Type, one form for each registrant.) (If your payment is by credit card, please FAX the form to us. Thank you.) Please enter your session/paper number _________________ for authors. Advance Registration Deadline: October 25, 1998 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Any registration after Oct. 25, 1998 (postmark cut-off) will be charged the at-symposium rate. Please complete the information below. Payment with registration must be made in US or NT dollars and made payable to: Allen C.-H. Wu ^^^^^^^^^^^^^^ Account No. 036-16-0060160, ^^^^^^^^^^^^^^^^^^^^^^^^^^^ Chiao Tung Bank, Hsinchu Branch, Hsinchu, Taiwan. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Title : __Prof. __Dr. __Mr. __Ms. __Miss. __Mrs. Name : ____________________________________________ Last First Mid Affiliation : ____________________________________________ Address : ____________________________________________ ____________________________________________ ____________________________________________ Phone : ____________________________________________ Fax : ____________________________________________ E-mail : ____________________________________________ Special needs [ ] Vegetarian [ ] Other ________________ Before Oct. 25, 1998 | After Oct. 25, 1998 [ ]ACM/IEEE Member | [ ]US$320 [ ]NT$11,000 | [ ]US$380 [ ]NT$13,000 [ ]Non-member | [ ]US$400 [ ]NT$13,500 | [ ]US$400 [ ]NT$13,500 [ ]Full-time Student | [ ]US$150 [ ]NT$ 5,000 | [ ]US$200 [ ]NT$6,500 Total Amount Enclosed : US$ __________ NT$ ___________ (or transferred to the above mentioned account) ACM/IEEE Membership # : _________________ (reqd. if registering at ACM/IEEE rates) I __enclose __Traver's check __ Money order I __use Credit card : __Visa __Master Card (Do not accept American Express). Card No. ___________ - ___________ - ___________ - ___________ Expiry date: __________________________________________________ Name as it appears on card: ___________________________________ Passport no./ROC citizen ID no.:_______________________________ Signature: ___________________________________________________ Date: ________________________________________________________ Cancellation Policy: No refunds will be made on cancellations received after Nov. 20, 1998. Cancellations received before Nov. 20 are subject to a 20% processing fee. Hotel Reservation Form Please type or print. Title : __Prof. __Dr. __Mr. __Ms. __Miss. __Mrs. Name : _______________________________________ Last First Mid Affiliation: _______________________________________ Address : _______________________________________ _______________________________________ _______________________________________ Phone : _______________________________________ Fax : _______________________________________ E-mail : _______________________________________ Member of IEEE/ACM Member No.:____________________ HOTEL RESERVATION Hotel Single Twin __Chinatrust Hotel __NT$2,970 __NT$3,330 __Shin Yuan Park Hotel __NT$2,430 __NT$3,120 (include service charge and tax.) Check-in date: ___________ Check-in time: _________ Check-out date: ___________ Number of nights: _____ TRANSPORTATION One way, between the CKS Airport and Hotel: NT$1,300 Flight Number: ___________ Arrival Time: ____________ METHOD OF PAYMENT Pay to the hotel when you check out with cash, traveler's check, or credit card. No personal check, please. NOTE: The room rates and availability are guaranteed for the period of Nov. 29 - Dec. 6, 1998, only if your reservation form is received before Oct. 25, 1998. Please send this form to the hotel you choose: Chinatrust Hotel: 106 Chung Yang Rd., Hsinchu, Taiwan 300 Fax: +886-3-5269244; Tel: +886-3-5263181 Shin Yuan Park Hotel: 11 Ta Tung Rd., Hsinchu, Taiwan 300 Fax: +886-3-5260522; Tel: +886-3-5226868 Tour Reservation Form Tour 1.: Taipei City Tour Date: Dec. 5, 1998 (Sat.) Fare: NT$1,750(Includes: 1 lunch) 1. National Palace Museum 2. Martyr's Shrine 3. Chinese Temple 4. Chiang Kai-Shek Memorial Hall 5. Dr. Sun Y. S. Memorial Hall 6. Presidential Office (Pass by) 7. Handicraft Center Tour 2.: Tarako National Park (Hualien) Date: Dec. 6, 1998 (Sun.) Fare: NT$4,200 (Including: Round-trip air ticket and lunch) (Passport needed for enplaning) Itinerary: Pick-up from hotel -> Transfer to Taipei Airport -> Arrive at Hualien -> Enbus for Tarako Groge Gateway ->Eternal-Spring Shrine -> Swallow Caves -> Tunnel of Nine Turns -> TienhsiangLodge -> Marble factory -> Enplane for Taipei -> Transfer to hotel Please type or print. Sex: __F __M Name : _______________________________________________ Last First Mid Passprot No.: ____________________________________ Birth Date : ____________________________________ Nationality : ____________________________________ Signature : ____________________________________ Tour Selection: please indicate your choice(s) ___ Taipei City Tour ____Tarako National Park (Hualien) Total amount: NT$______________________ Payment: By cash or traverler's check in NTD to the travel agent at the conference site. Please send this form to (before Oct. 25, 1998) Trans Continental Travel Service Co., Ltd. 4F, No. 21, Lane 45, Sec. 2, Chung-San N. Rd., Taipei, Taiwan. Fax: +886-2-25230002; +886-2-26946057 Tel: +886-2-25233131 From pilz@ifi.unizh.ch Thu Oct 15 19:54:09 1998 +0200 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <02729-0@josef.ifi.unizh.ch>; Thu, 15 Oct 1998 19:54:01 +0100 Return-Path: X-Received: from pol88b.polito.it by josef.ifi.unizh.ch with SMTP (PP) id <02646-0@josef.ifi.unizh.ch>; Thu, 15 Oct 1998 19:52:07 +0100 X-Received: from chiusella.polito.it.polito.it (chiusella.polito.it) by polito.it (PMDF V4.2-15 #3020) id <01J30F6WT70WHSLNHO@polito.it>; Thu, 15 Oct 1998 19:45:32 GMT+1 X-Received: by chiusella.polito.it.polito.it (4.1/SMI-4.1) id AA05997; Thu, 15 Oct 98 18:45:31 +0100 Date: Thu, 15 Oct 1998 18:45:31 +0100 From: tttc@chiusella.polito.it (Paolo Prinetto) Subject: IEEE TTTC - MTV'98: Int'l Workshop of Microprocessor Test and Verification To: pilz@ifi.unizh.ch Message-id: <9810151745.AA05997@chiusella.polito.it.polito.it> X-Envelope-to: pilz@ifi.unizh.ch Content-transfer-encoding: 7BIT Apparently-To: PILZ Markus ReSent-Date: Thu, 15 Oct 1998 19:53:55 +0200 (MET DST) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: IEEE TTTC - MTV'98: Int'l Workshop of Microprocessor Test and Verification ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 46 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % IEEE Computer Society % Test Technology Technical Committee % % % .... FOR YOUR INFORMATION.... % % A free service of the Technical Meeting Group % % % This message contains public information, only, and % the receiver is allowed, and invited, to copy it and % distribute it further. % % % For more information contact % or visit http://www.computer.org/tab/tttc/ % % If you would like to be removed from this mailing list, % please send an e-mail to % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% ****************************************************************************** F I N A L P R O G R A M ***************************************************************************** IEEE International Workshop of Microprocessor Test and Verification MTV 98 Marriott Wardman Park Hotel, Washington,D.C. USA October 22-23, 1998 ****************************************************************************** Sponsored by - TTTC - The IEEE Computer Society Test Technology Technical Committee In Conjunction with - ITC 98 - The International Test Conference and the Test Week ****************************************************************************** SCOPE: ****** THE PURPOSE of this workshop is to bring researchers and practitioners from the fields of verification and test together to exchange innovative ideas and to develop new methodologies to solve the difficult challenges facing us today in various processor design environments. In the past few years, some work has been done on exploiting techniques from test to solve problems in verification and vice versa. This workshop should provide the ideal environment for cross fertilizing test and verification experiences and innovative solutions. ************************************************************************** W O R K S H O P A T A G L A N C E ************************************* Thursday October 22, 1998 *************************** 2pm - 7pm Registration 4pm - 5pm Welcome and Keynote Presentation 5pm - 6:30 pm Paper Session 1 7pm - 9pm Workshop Reception Friday, October 23, 1998 ************************** 7am - 8am Breakfast 8am - 10am Paper Session 2 10am - 10:30am Coffee Break 10:30am - 12:30pm PANEL - "Will formal verification be the simulation of tomorrow?" 12:30pm - 1:30pm Lunch 1:30pm - 3pm Paper Session 4 ****************************************************************************** W O R K S H O P C O M M I T T E E *************************************** General Chair: Magdy S. Abadir, Motorola Publication Chair: Li-Chung Wang, Motorola **************************** Program Committee **************************** Jacob Abraham, UT-Austin Tony Ambler, UT-Austin Dilip Bhavsar, DEC Shawn Blanton, CMU Pradip Bose, IBM Melvin Breuer, USC Tim (K-T) Cheng, UCSB Sujit Dey, UCSD John P. Hayes, U. Michigan Sandip Kundu, Intel M. Ray Mercer, Texas A&M U Carl Pixley, Motorola Paolo Prinetto, Poli di Torino Elizabeth M Rudnick, U. Illinois Susanna Stoica, Ford Motor Company Li-C. Wang, Motorola T. W. Williams, Synopsis Yervant Zorian, LogicVision **************************************************************************** Proceedings *********** Informal Proceedings will be made available to all attendees. This will include extended abstracts, summaries or papers provided by authors based on their presentations. WORKSHOP LOCATION ***************** MTV 98 will be held at the Marriott Wardman Park Hotel, Washington, D.C, USA, Oct. 22-23, 1998, immediately following ITC 98. The Marriott Wardman Park Hotel, headquarters hotel of ITC TestWeek 98, is located at Connecticut Ave. and Woodley Road in NW Washington. Adjacent to the hotel is the WoodleyPark station on Washington's Metro (subway system). The Woodley Park station is on the Metro's Red Line. Washinton is served by Ronald Reagon National Airport, Dulles International Airport and Baltimore-Washington International Airport. Washinton is on the Amtrak eastern coridor railroad with direct service to major east coast cities. REGISTRATION ************ All Workshop participants require registration. Either register at the ITC Registration counter at the Marriott Wardman Park Hotel, or use ITC 98 Registration Forms (www.itctestweek.org). Registration rates are: IEEE/CS Member $260, IEEE Student Member $110 and Non-Member $320. Registration includes welcome address, workshop technical sessions, workshop informal proceedings, evening reception, break refreshments, breakfast and lunch. Separate registration is required for all other ITC Test Week events. HOTEL RESERVATION ***************** Make hotel reservations at special ITC Test Week rates by completing the ITC Hotel Reservation Form found (www.itctestweek.org) or by calling JBM Services +1-408-741-2900, fax: +1-408-741-9055. ************************************************************************ W O R K S H O P P R O G R A M ******************************** THURSDAY, October 22 ************************ Registration: 2m - 7pm _________________________________________ OPENING SESSION: 4pm - 5pm Welcome Address - M. Abadir, General Chair Invited Presentation - Pradip Bose, IBM T.J. Watson Research Center Testing for function AND performance: towards an integrated processor validation methodology _________________________________________ 5:00-6:30pm: SESSION 1 Session Chair: Elizabeth Rudnick, University of Illinois 1. Exploiting the Logic of Positive Equality for Formal Verification of Pipelined Microprocessors Miroslav N. Velev* and Randal E. Bryant, Carnegie Mellon University. 2. SimGen: A Tool for Automatically Generating Simulation Environments from Constraints Jun Yuan, Kurt Shultz, Carl Pixley*, and Hillel Miller Motorola, Inc. 3. Test Model Generation and Verification for the IBM S/390 500 MHz Microprocessor Bryan J. Robbins*, IBM _________________________________________ 7-9pm: Workshop Reception _________________________________________ Friday, October 23 ****************** _________________________________________ 7:00-8:00am: CONTINENTAL BREAKFAST _________________________________________ 8:00-10:00am: SESSION 2 Session Chair: Carl Pixley, Motorola 1. Simulation-Based Design Verification for Pipelined Microprocessors Ta-Chung Chang* and Elizabeth M. Rudnick, University of Illinois 2. Validation of Speculative and Out-of-order Execution Microarchitectures Noppanunt Utamaphethai*, R.D. Blanton and John P. Shen Carnegie Mellon University 3. Experience in Validation of PowerPC Microprocessors Li-C. Wang and Magdy Abadir*, Motorola 4. Evaluation of Design Error Models for Verification Testing of Microprocessors David Van Campenhout*, Trevor Mudge and John P. Hayes University of Michigan ___________________________________ 10:00-10:30 Cofee Break ___________________________________ 10:30-12:30: Session 3: PANEL - Will Formal Verification be the Simulation of Tomorrow? Organizer: Elizabeth Rudnick, University of Illinois, Urbana-Champaign Moderator: Jacob Abraham, Univ. of Texas at Austin Panelists: (to include) Doug Josephson, Hewlett-Packard Co. Victor Konrad, Intel Ishwar Parulkar, Sun Microsystems Carl Pixley, Motorola Scott Taylor, Compaq Computer Corp. ______________________________________ Lunch: 12:30pm - 1:30pm ______________________________________ 1:30-3:00pm: SESSION 4 Session Chair: Magdy Abadir, Motorola 1. An Efficient Logic Equivalence Checker for Industrial Circuits Jaehong Park*, IBM and Carl Pixley, Motorola, Inc. 2. Code-Perturbation Approach for Verification Simulation Byeong Min* and Gwan Choi, Texas A&M University 3. Oscillation Ring Delay Test for High Performance Microprocessors Wen Ching Wu*, Chung Len Lee, Jwu E. Chen, Hsin Chu Taiwan and Magdy Abadir, Motorola _________________________________________ 3:00pm CLOSE _________________________________________ Information *********** For more information on the Workshop, please check: or contact: Magdy Abadir, Phone: +1-512-424-8192, Email:abadir@ibmoto.com or the TTTC Office: IEEE TTTC, 1474 Freeman Dr, Amissville, VA 20106 Tel: +1-540-937-8280, Fax: +1-540-937-3739, Email: tttc@computer.org *************************************************************************** %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % Paolo PRINETTO % % IEEE Computer Society % Test Technology Technical Committee (Vice Chair) % % Politecnico di Torino % Dip. di Automatica e Informatica % Corso Duca degli Abruzzi 24 % I-10129 Torino TO % Italy % % Tel: + 39 011 564.7007 % Fax: + 39 011 564.7099 % % E-mail: Paolo.Prinetto@polito.it % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% From pilz@ifi.unizh.ch Thu Oct 15 21:32:26 1998 +0200 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <04367-0@josef.ifi.unizh.ch>; Thu, 15 Oct 1998 20:59:06 +0100 Return-Path: X-Received: from pol88b.polito.it by josef.ifi.unizh.ch with SMTP (PP) id <04273-0@josef.ifi.unizh.ch>; Thu, 15 Oct 1998 20:56:12 +0100 X-Received: from chiusella.polito.it.polito.it (chiusella.polito.it) by polito.it (PMDF V4.2-15 #3020) id <01J30H3GUTXCHSLLPF@polito.it>; Thu, 15 Oct 1998 20:40:01 GMT+1 X-Received: by chiusella.polito.it.polito.it (4.1/SMI-4.1) id AA13522; Thu, 15 Oct 98 19:40:00 +0100 Date: Thu, 15 Oct 1998 19:40:00 +0100 From: tttc@chiusella.polito.it (Paolo Prinetto) Subject: IEEE TTTC - VTS'99 : 17TH IEEE VLSI TEST SYMPOSIUM To: pilz@ifi.unizh.ch Message-id: <9810151840.AA13522@chiusella.polito.it.polito.it> X-Envelope-to: pilz@ifi.unizh.ch Content-transfer-encoding: 7BIT Apparently-To: PILZ Markus ReSent-Date: Thu, 15 Oct 1998 20:58:59 +0200 (MET DST) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: IEEE TTTC - VTS'99 : 17TH IEEE VLSI TEST SYMPOSIUM ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 47 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % IEEE Computer Society % Test Technology Technical Committee % % % .... FOR YOUR INFORMATION.... % % A free service of the Technical Meeting Group % % % This message contains public information, only, and % the receiver is allowed, and invited, to copy it and % distribute it further. % % % For more information contact % or visit http://www.computer.org/tab/tttc/ % % If you would like to be removed from this mailing list, % please send an e-mail to % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% ********************************************************************** CALL FOR PAPERS 17TH IEEE VLSI TEST SYMPOSIUM Marriott Laguna Cliffs Resort, Dana Point, California April 25 - April 29, 1999 WWW site: http://www.computer.org/tab/tttc/meetings/vts/home.html ********************************************************************** IEEE VLSI Test Symposium explores emerging trends and novel concepts in testing of circuits and systems. The theme of the seventeenth symposium is "Scaling Deeper to Submicron: Test Technology Challenges". The major topics include, but are not limited to, the following: . Analog and RF Testing . IDDQ Testing . Automatic Test Generation . MEMS Testing . Built-In Self-Test (BIST) . Multi-Chip Module Test . Delay Testing . On-Line Testing . Design for Testability . Quality and Reliability . Design Verification/Validation . Self-Checking Circuits . Diagnosis and Debugging . Synthesis for Testability . Embedded Core Testing . System Test . Fault Modeling & Simulation . System-on-Chip Test . Fault Tolerant Architectures . Thermal Testing The Program Committee invites original, unpublished paper proposals (complete manuscripts or extended summaries) and proposals for panel sessions. Authors should clearly explain the significance of the work, highlight novel features, and describe its current status. On the title page, please include: name, affiliation, mailing address, phone number, fax number, and E-mail address of the contact author. A 50 word abstract, and 5 key words identifying the topic area are also required. Electronic submission in Postscript is encouraged, although hard copy submissions to the Program Chair (10 copies) will also be accepted. Detailed directions for submitting papers are available at: http://www.computer.org/tab/tttc/meetings/vts/home.html Submissions are due no later than October 30, 1998. For additional information, contact: Michael Nicolaidis, General Chair Adit Singh, Program Chair TIMA Dept. of Electrical Engineering 46 Avenue Felix VIALLET Auburn University 38031 Grenoble Cedex, FRANCE Auburn, AL 36849 T: +33-476-57-4619, F: +33-476-47-3814 T: +1-334 844-1847 F:+1-334-844 -1809 E: Michael.Nicolaidis@imag.fr E: adsingh@eng.auburn.edu Authors will be notified of the disposition of their papers by January 8, 1999. The submission of a proposal will be considered evidence that upon acceptance the author(s) will present the paper at the symposium and will submit a final paper for inclusion in the proceedings no later than February 11, 1999. VTS'99 will present a Best Paper Award and a Best Panel Award, based on the evaluations of reviewers, attendees, and an invited panel of judges. VTS 99 convenes in Marriot's Laguna Cliffs Resort at Dana Point overlooking the Pacific Ocean and the Southern California coast line! Midway between Los Angeles and San Diego. A site that preserves the special reputation of combining dramatic towering cliffs, white sand beaches, coastal majestic bluffs and sensational ocean sunsets! Conveniently located near Orange County John Wayne Airport. VLSI Test Symposium is sponsored by the IEEE Computer Society Test Technology Technical Committee (TTTC). ********************************************************************** GENERAL CHAIR M. Nicolaidis - TIMA PROGRAM CHAIR A. Singh - Auburn U PAST CHAIR R. Roy - Intel VICE GENERAL CHAIR S. Dey - UCSD VICE PROGRAM CHAIRS J. Figueras - U Poli Catalunya S. Chakravarty - Intel PUBLICITY A. Raghunathan - NEC USA FINANCE A. Ivanov - U of Brit. Columbia PANELS H-J. Wunderlich - U of Stuttgart PUBLICATIONS F. J. Ferguson - UC Santa Cruz LOCAL ARRANGEMENTS J. Monzel - IBM EX OFFICIO Y. Zorian - LogicVision PROGRAM COMMITTEE : M. Abadir - Motorola J.A. Abraham - U of Texas M. Abramovici - Lucent Bell Labs S. Adham - Nortel V.D. Agrawal - Lucent Bell Labs J. Aylor - U of Virginia B. Becker - U of Freiburg S. Blanton - Carnegie-Mellon U M. Breuer - U of Southern Cal. G. Carlsson - Ericsson A. Chatterjee - Georgia Tech. K.T. Cheng - UC Santa Barbara V. Chickermane - IBM B. Courtois - TIMA M. d'Abreu - Level One Comm. W.K. Fuchs - Purdue U H. Fujiwara - NAIST M. Goessel - U of Potsdam J.P. Hayes - U of Michigan N. Jha - Princeton U B. Kaminska - OPMAXX K. Kinoshita - Osaka U A. Kuchukian - Armenian NAS C. Landrault - U Montpellier II A. Majumdar - Synopsys W. Maly - Carnegie-Mellon U P. Maxwell - Hewlett Packard E.J. McCluskey - Stanford U B. Nadeau-Dostie - LogicVision V. Nelson - Auburn U A. Orailoglu - UC San Diego C. Papachristou - Case West. Res. U A. Paschalis - NCSR Demokritos J.H. Patel - U of Illinois I. Pomeranz - U of Iowa T. Powell - Texas Instruments D. Pradhan - Texas A&M U P. Prinetto - Poli di Torino J. Rajski - Mentor Graphics E. Rudnick - U of Illinois R. Segers - Philips E. Sogomonyan - Russian NAS S. Sunter - LogicVision M. Soma - U of Washington S. Tragoudas - Southern Illinois U A.J. van de Goor - Delft U T.W. Williams - Synopsys STEERING COMMITTEE: D. Graham - inTest N. Kornfield - Widener U M. Modi - Naval Air War. Cnt R. Roy - Intel P. Varma - Veritable Y. Zorian - LogicVision ********************************************************************** IEEE VLSI Test Symposium 1474 Freeman Drive, Amissville, VA 20106, USA Tel: +1 (540) 937-8280, Fax: +1 (540) 937-3739 Email: tttc@computer.org WWW Site: http://www.computer.org/tab/tttc/meetings/vts/home.html ********************************************************************** %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % Paolo PRINETTO % % IEEE Computer Society % Test Technology Technical Committee (Vice Chair) % % Politecnico di Torino % Dip. di Automatica e Informatica % Corso Duca degli Abruzzi 24 % I-10129 Torino TO % Italy % % Tel: + 39 011 564.7007 % Fax: + 39 011 564.7099 % % E-mail: Paolo.Prinetto@polito.it % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% From pilz@ifi.unizh.ch Tue Oct 27 17:22:55 1998 +0100 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <05012-0@josef.ifi.unizh.ch>; Tue, 27 Oct 1998 17:22:46 +0100 Return-Path: X-Received: from cs20.cs.nthu.edu.tw by josef.ifi.unizh.ch with SMTP (PP) id <29863-0@josef.ifi.unizh.ch>; Tue, 27 Oct 1998 15:19:28 +0100 X-Received: (from isss98@localhost) by cs.nthu.edu.tw (thcs.2/cs20) id WAA17868 for codesign@ifi.unizh.ch; Tue, 27 Oct 1998 22:15:13 +0800 (CST) From: isss98 Message-Id: <199810271415.WAA17868@cs.nthu.edu.tw> Subject: Gentle reminder: ISSS'98 Advance Registration Extention To: codesign@ifi.unizh.ch Date: Tue, 27 Oct 1998 22:15:12 +0800 (CST) X-Mailer: ELM [version 2.4ME+ PL34C (25)] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit ReSent-Date: Tue, 27 Oct 1998 17:22:33 +0100 (MET) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: Gentle reminder: ISSS'98 Advance Registration Extention ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 48 ============================================= RE: Advance Registration Extention to Nov. 6. ============================================= 11TH INTERNATIONAL SYMPOSIUM ON SYSTEM SYNTHESIS (ISSS) Hsinchu, Taiwan, R.O.C., December 2-4, 1998 Sponsored by the IEEE Computer Society DATC and the ACM SIGDA (http://www.cs.nthu.edu.tw/~isss98/) FINAL PROGRAM Tuesday, December 1, 1998 18:00 - 20:00 On-site Registration 19:00 - 21:00 Reception Wednesday, December 2, 1998 08:30 - 09:00 Open statement 09:00 - 10:00 Invite talk: Is IP Business Hype or Reality? D. D. Gajski, U. of California, Irvine, USA 10:00 - 10:30 Coffee break 10:30 - 11:30 Session 1: Code Generation and Optimization Issues 1.1 A Uniform Optimization Technique for Offset Assignment Problems Rainer Leupers, Fabian David; Dept. of Computer Science, Univ. of Dortmund 1.2 Code Generation for Compiled Bit-True Simulation of DSP Applications L. De Coster, M. Ade, R. Lauwereins, J.A. Peperstraete; Katholieke Univ. Leuven, Dept. ESAT, Belgium 1.3 Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture W.-K. Cheng, Y.-L. Lin; Dept. of CS, NTHU, Taiwan, R.O.C 11:30 - 12:00 Poster discussion 12:00 - 13:30 Lunch 13:30 - 14:30 Invite talk: Issues in Embedded DRAM Development and Applications; K.-S. Doris; Siemens Research and Devel, Germany 14:30 - 15:30 Session 2: IP Reuse and Language 2.1 A Processor Description Language Supporting Retargetable Multi-Pipeline DSP Program Development Tools C. Siska; Rockwell Semiconductor Systems, Inc. 2.2 Intellectual Property Re-use in Embedded System Co-design: an Indutrial Case Study E. Filippi, L. Lavagno, L. Licciardi, A. Montanaro, M. Paolini, R. Passerone, A. Sangiovanni-Vincentelli, M. Sgroi; CSELT, Italy. Dipartimento di Elettronica, Politecnico di Torino, Italy. Univ. of CA. at Berkeley, USA. 2.3 Incorporating Cores into System-Level Specification F. Vahid and T. Givargis; Dept. of Computer Science, Univ. of California, USA 15:30 - 16:00 Poster discussion and coffee break 16:00 - 16:30 Poster presentation P1 HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation R. Leupers; Dept. of Computer Science, Univ. of Dortmund P2 False Path Analysis based on a Hierarchical Control Representation A. A. Kountouris and C. Wolinski; IRISA - Institut de Recherche en Informatique et Systemes Aleatoires P3 Resource constrained Modulo Scheduling with Global Resource Sharing C. Jaeschke, R. Laur; Univ. of Bremen, Dept. 1, Institute of Electromagnetic Theory and Micro., Bremen/Germany. P4 Statistical Performance-Driven Module Binding in High-Level Synthesis H. Tomiyama, A. Inoue, and H. Yasuura; Dept. of Computer Science and Communication Eng., Graduate School of Information Science and Electrical Eng., Kyushu Univ., Japan P5 Concurrent Error Detection at Architectural Level C. Bolchini, W. Fornaciari, F. Salice, D. Sciuto; Cristiana Bolchini: Politecnico di Milano-Dipartimento di Elettronica e Informazione, Italy. P6 Communication and Interface Synthesis on a Rapid Prototyping Hardware/Software Codesign System Y.-T. Hwang, Y.-H. Wang; Dept. of Electronic Eng. NYU of Science & Technology Taiwan, R.O.C 16:30 - 17:30 Poster discussion 18:30 - 20:00 Dinner 20:00 - 22:00 Panel: IP-Based design: VIP (Very Important Process) or RIP(Rest in Peace) Thursday, December 3, 1998 09:00 - 10:00 Invite talk: Compiler Technology for Application-Specific Processors/Systems on Chips Monica Lam, Stanford Univ., USA 10:00 - 10:30 Coffee break 10:30 - 11:30 Session 3: Application-Specific Synthesis Techniques 3.1 Application-Specific Heterogenous Multiprocessor Synthesis Using Differential-Evolution A. Rae, S. Parameswaran; Dept. of Computer Science and Electrical Eng. Univ. of Qu`ensland, Australia. 3.2 Proposal for unified system design meta flow in task- level and instruction-level design technology research for multi-media applications F. Catthoor, D. Verkest, E. Brockmeyer; IMEC, VSDM Division, Katholieke Univ. Leuven 3.3 Data-path Synthesis of VLIW Video Signal Processors Z. Wu, W. Wolf; Dept. of Electrical Eng., Princeton Univ., U.S.A. 11:30 - 12:00 Poster discussion 12:00 - 13:30 Lunch 13:30 - 14:30 Group Discussion 14:30 - 15:30 Session 4: Synchronization and Interface Issues 4.1 Synchronization Detection for Multi-Process Hierarchical Synthesis O Bringmann, W. Rosenstiel, D. Reichardt; FZI and Univ. of Tubingen, Germany 4.2 Integrating Communication Protocol Selection with Partitioning in Hardware/Software Codesign P. V. Knudsen and J. Madsen; Dept. of Information Technology, Technical Univ. of Denmark, Denmark 4.3 Interface Exploration for Reduced Power in Core-Based Systems T. Givargis, F. Vahid; Dept. of Computer Science, University of California, U.S.A. 15:30 - 16:00 Poster discussion and coffee break 16:00 - 17:00 Session 5: Instruction Encoding and Software Synthesis Techniques 5.1 Instruction Encoding Techniques for Area Minimization of Instruction ROM T. Okuma, H. Tomiyama, A. Inoue, E. Fajar, H. Yasuura Dept. of Computer Science and Communication Eng., Kyushu University, Japan 5.2 Application of Instruction Analysis/Synthesis Tools to x86's Functional Unit Alloation I.-J. Huang, P.-H. Xie; Institute of Computer and Information Eng., NSYSU Kaohsiung, Taiwan, R.O.C. 5.3 Memory Efficient Software Synthesis from Dataflow Graph W. Sung, Junedong Kim, Soonhoi Ha; Dept. of Computer Eng., Seoul National University, Korea 17:00 - 17:30 Poster discussion 17:30 - 18:30 General discussion session 19:00 - 21:00 Banquet Friday, December 4, 1998 09:00 - 10:00 Invite talk: (Subject: TBA) Min Wu, Maronix International. Co. Ltd. 10:00 - 10:30 Coffee break 10:30 - 11:30 Session 6: Partitioning and Scheduling Techniques 6.1 A Tool Partitioning and Pipelined Scheduling of Hardware- Software Systems Karam S. Chatha and Ranga Vemuri; Laboratory for Digital Design Environments, Department of ECECS, University of Cincinnati 6.2 A Three-Step Approach to the Functional Partitioning of Large Behavioral Processes F. Vahid; Dept. of Computer Science, Univ. of California, U.S.A. 6.3 Fine-Grain, Incremental Rescheduling Via Architectural Retiming; S. Hassoun; Dept. of Electrical Eng. and Computer Science, Tufts University 11:30 - 12:00 Poster discussion 12:00 - 13:30 Lunch 13:30 - 16:30 Science-Based Industry Park Tour Saturday, December 5, 1998 Taipei City Tour Sunday, December 6, 1998 Tarako National Park Tour ISSS'98 Registration Form (Print or Type, one form for each registrant.) (If your payment is by credit card, please FAX the form to us. Thank you.) Please enter your session/paper number _________________ for authors. Advance Registration Deadline: October 25, 1998 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Any registration after Oct. 25, 1998 (postmark cut-off) will be charged the at-symposium rate. Please complete the information below. Payment with registration must be made in US or NT dollars and made payable to: Allen C.-H. Wu ^^^^^^^^^^^^^^ Account No. 036-16-0060160, ^^^^^^^^^^^^^^^^^^^^^^^^^^^ Chiao Tung Bank, Hsinchu Branch, Hsinchu, Taiwan. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Title : __Prof. __Dr. __Mr. __Ms. __Miss. __Mrs. Name : ____________________________________________ Last First Mid Affiliation : ____________________________________________ Address : ____________________________________________ ____________________________________________ ____________________________________________ Phone : ____________________________________________ Fax : ____________________________________________ E-mail : ____________________________________________ Special needs [ ] Vegetarian [ ] Other ________________ Before Nov. 6, 1998 | After Nov. 6, 1998 [ ]ACM/IEEE Member | [ ]US$320 [ ]NT$11,000 | [ ]US$380 [ ]NT$13,000 [ ]Non-member | [ ]US$400 [ ]NT$13,500 | [ ]US$400 [ ]NT$13,500 [ ]Full-time Student | [ ]US$150 [ ]NT$ 5,000 | [ ]US$200 [ ]NT$6,500 Total Amount Enclosed : US$ __________ NT$ ___________ (or transferred to the above mentioned account) ACM/IEEE Membership # : _________________ (reqd. if registering at ACM/IEEE rates) I __enclose __Traver's check __ Money order I __use Credit card : __Visa __Master Card (Do not accept American Express). Card No. ___________ - ___________ - ___________ - ___________ Expiry date: __________________________________________________ Name as it appears on card: ___________________________________ Passport no./ROC citizen ID no.:_______________________________ Signature: ___________________________________________________ Date: ________________________________________________________ Cancellation Policy: No refunds will be made on cancellations received after Nov. 20, 1998. Cancellations received before Nov. 20 are subject to a 20% processing fee. Hotel Reservation Form Please type or print. Title : __Prof. __Dr. __Mr. __Ms. __Miss. __Mrs. Name : _______________________________________ Last First Mid Affiliation: _______________________________________ Address : _______________________________________ _______________________________________ _______________________________________ Phone : _______________________________________ Fax : _______________________________________ E-mail : _______________________________________ Member of IEEE/ACM Member No.:____________________ HOTEL RESERVATION Hotel Single Twin __Chinatrust Hotel __NT$2,970 __NT$3,330 __Shin Yuan Park Hotel __NT$2,430 __NT$3,120 (include service charge and tax.) Check-in date: ___________ Check-in time: _________ Check-out date: ___________ Number of nights: _____ TRANSPORTATION One way, between the CKS Airport and Hotel: NT$1,300 Flight Number: ___________ Arrival Time: ____________ METHOD OF PAYMENT Pay to the hotel when you check out with cash, traveler's check, or credit card. No personal check, please. NOTE: The room rates and availability are guaranteed for the period of Nov. 29 - Dec. 6, 1998, only if your reservation form is received before Oct. 25, 1998. Please send this form to the hotel you choose: Chinatrust Hotel: 106 Chung Yang Rd., Hsinchu, Taiwan 300 Fax: +886-3-5269244; Tel: +886-3-5263181 Shin Yuan Park Hotel: 11 Ta Tung Rd., Hsinchu, Taiwan 300 Fax: +886-3-5260522; Tel: +886-3-5226868 Tour Reservation Form Tour 1.: Taipei City Tour Date: Dec. 5, 1998 (Sat.) Fare: NT$1,750(Includes: 1 lunch) 1. National Palace Museum 2. Martyr's Shrine 3. Chinese Temple 4. Chiang Kai-Shek Memorial Hall 5. Dr. Sun Y. S. Memorial Hall 6. Presidential Office (Pass by) 7. Handicraft Center Tour 2.: Tarako National Park (Hualien) Date: Dec. 6, 1998 (Sun.) Fare: NT$4,200 (Including: Round-trip air ticket and lunch) (Passport needed for enplaning) Itinerary: Pick-up from hotel -> Transfer to Taipei Airport -> Arrive at Hualien -> Enbus for Tarako Groge Gateway ->Eternal-Spring Shrine -> Swallow Caves -> Tunnel of Nine Turns -> TienhsiangLodge -> Marble factory -> Enplane for Taipei -> Transfer to hotel Please type or print. Sex: __F __M Name : _______________________________________________ Last First Mid Passprot No.: ____________________________________ Birth Date : ____________________________________ Nationality : ____________________________________ Signature : ____________________________________ Tour Selection: please indicate your choice(s) ___ Taipei City Tour ____Tarako National Park (Hualien) Total amount: NT$______________________ Payment: By cash or traverler's check in NTD to the travel agent at the conference site. Please send this form to (before Oct. 25, 1998) Trans Continental Travel Service Co., Ltd. 4F, No. 21, Lane 45, Sec. 2, Chung-San N. Rd., Taipei, Taiwan. Fax: +886-2-25230002; +886-2-26946057 Tel: +886-2-25233131 From pilz@ifi.unizh.ch Mon Nov 2 09:59:50 1998 +0100 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <05031-0@josef.ifi.unizh.ch>; Mon, 2 Nov 1998 09:59:41 +0100 Return-Path: X-Received: from pol88b.polito.it by josef.ifi.unizh.ch with SMTP (PP) id <03602-0@josef.ifi.unizh.ch>; Mon, 2 Nov 1998 08:55:59 +0100 X-Received: from chiusella.polito.it.polito.it (chiusella.polito.it) by polito.it (PMDF V4.2-15 #3020) id <01J3OXGA1UV48X08S0@polito.it>; Mon, 2 Nov 1998 08:47:30 GMT+1 X-Received: by chiusella.polito.it.polito.it (4.1/SMI-4.1) id AA00407; Mon, 2 Nov 98 08:47:29 +0100 Date: Mon, 02 Nov 1998 08:47:29 +0100 From: tttc@chiusella.polito.it (Paolo Prinetto) Subject: IEEE TTTC - ITSW'99 : CfP To: pilz@ifi.unizh.ch Message-id: <9811020747.AA00407@chiusella.polito.it.polito.it> X-Envelope-to: pilz@ifi.unizh.ch Content-transfer-encoding: 7BIT Apparently-To: PILZ Markus ReSent-Date: Mon, 2 Nov 1998 09:59:29 +0100 (MET) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: IEEE TTTC - ITSW'99 : CfP ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 49 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % IEEE Computer Society % Test Technology Technical Committee % % % .... FOR YOUR INFORMATION.... % % A free service of the Technical Meeting Group % % % This message contains public information, only, and % the receiver is allowed, and invited, to copy it and % distribute it further. % % % For more information contact % or visit http://www.computer.org/tab/tttc/ % % If you would like to be removed from this mailing list, % please send an e-mail to % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% Sixth International Test Synthesis Workshop Call for Participation March 22-24, 1999 Fess Parker's Doubletree Resort Santa Barbara, CA, USA Scope ===== With the increasing complexity of VLSI systems, hardware testability structures are becoming more commonplace. Advances in technology have enabled systems on chips, and Design for Testability (DFT) is necessary to handle such complex designs. Design reuse is an important issue for many designers, and ensuring testability of designs that use IP cores is essential. While ad-hoc DFT techniques have been used in the past, automatic synthesis of DFT hardware has become necessary in many design environments. This workshop discusses all aspects of Test Synthesis, loosely defined as the enabling technology of Design for Test. The topics include, but are not limited to, the following: Register Transfer Level DFT High-Level/Behavioral Test Synthesis System on Chip Design for Test Synthesis of BIST Hardware Synthesis of Test Access Structures Test Synthesis for Mixed Signal Circuits Test Synthesis for Programmable Structures Synthesis of Testable Cores Embedded Core Testing Economics of Test Synthesis DFT Rule Checking Diagnostic Test Synthesis Synthesis for Testability DFT/ATPG Interaction Presentation To present recent research results at the workshop, please submit an extended abstract, one to three pages long, to the Program Chair by December 1, 1998. Send either a hard copy by regular mail or a Postscript version through email. The abstract should clearly describe the nature of the contribution, the method, results, originality, significance, and superiority over other methods. The name, address, phone number, fax number, and e-mail address of the presenter should also be included. Submitters will be notified of the disposition of abstracts by January 18, 1999. To maintain a free flow of information, no proceedings of the workshop will be published. For Technical Program Information and Submissions: Elizabeth M. Rudnick, Program Chair Coordinated Science Laboratory University of Illinois at Urbana Champaign 1308 West Main Street Urbana, IL 61801 Phone: 217-244-4659 Fax: 217-244-5685 E-mail: liz@uiuc.edu For General Information: Rob Aitken, General Chair Hewlett Packard M/S 6U-K 1501 Page Mill Road Palo Alto, CA 94304 Tel: 650-857-2146 Fax: 650-852-8312 E-mail: aitken@dtc.hp.com Sponsored by IEEE Computer Society - Test Technology Technical Committee %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % Paolo PRINETTO % % IEEE Computer Society % Test Technology Technical Committee (Vice Chair) % % Politecnico di Torino % Dip. di Automatica e Informatica % Corso Duca degli Abruzzi 24 % I-10129 Torino TO % Italy % % Tel: + 39 011 564.7007 % Fax: + 39 011 564.7099 % % E-mail: Paolo.Prinetto@polito.it % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% From pilz@ifi.unizh.ch Mon Nov 2 11:05:04 1998 +0100 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <08155-0@josef.ifi.unizh.ch>; Mon, 2 Nov 1998 11:04:55 +0100 Return-Path: X-Received: from pol88b.polito.it by josef.ifi.unizh.ch with SMTP (PP) id <05639-0@josef.ifi.unizh.ch>; Mon, 2 Nov 1998 10:16:45 +0100 X-Received: from chiusella.polito.it.polito.it (chiusella.polito.it) by polito.it (PMDF V4.2-15 #3020) id <01J3P0AUFMLS8WZ5IH@polito.it>; Mon, 2 Nov 1998 10:08:37 GMT+1 X-Received: by chiusella.polito.it.polito.it (4.1/SMI-4.1) id AA07510; Mon, 2 Nov 98 10:08:36 +0100 Date: Mon, 02 Nov 1998 10:08:36 +0100 From: tttc@chiusella.polito.it (Paolo Prinetto) Subject: IEEE TTTC - ATS'99 : C.f.Part. To: pilz@ifi.unizh.ch Message-id: <9811020908.AA07510@chiusella.polito.it.polito.it> X-Envelope-to: pilz@ifi.unizh.ch Content-transfer-encoding: 7BIT Apparently-To: PILZ Markus ReSent-Date: Mon, 2 Nov 1998 11:04:47 +0100 (MET) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: IEEE TTTC - ATS'99 : C.f.Part. ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 50 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % IEEE Computer Society % Test Technology Technical Committee % % % .... FOR YOUR INFORMATION.... % % A free service of the Technical Meeting Group % % % This message contains public information, only, and % the receiver is allowed, and invited, to copy it and % distribute it further. % % % For more information contact % or visit http://www.computer.org/tab/tttc/ % % If you would like to be removed from this mailing list, % please send an e-mail to % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% Call for Participation - 7th Asian Test Symposium 1998 The Electronics & Communication Engineering Dept of Singapore Polytechnic would like to invite you to participate in the 7th Asian Test Symposium on 2-4 Dec 1998 at the Hilton International Singapore Hotel. ATS'98 is sponsored by IEEE Computer Society Test Technology Technical Committee, Computer Chapter of IEEE Singapore and Singapore Polytechnic. The Asian Test Symposium is the biggest test technology event in Asia. It provides an annual international forum for specialists from all over the world, especially from Asia, to present and discuss various aspects of system, board, and component test with design, manufacturing and field considerations in mind. A total of 88 papers were accepted and will be presented in 18 technical sessions covering the most important topics in modern test technology. In addition, two panel sessions on the controversially provocative topics - "Microsystem Testing: Challenge or Common Knowledge?" and "Testing Embedded Memories: Is BIST the Ultimate Solution?" have been included. There will also be four tutorials and a small exhibition. Dr. T. W. Williams, Director of Research and Development, Test Technology, Synopsys, Inc. will deliver the keynote address "The New Frontier for Testing: Nanometer Technologies". Additional information can be obtained from the symposium web site at: http://www.sp.edu.sg/ec1/ats98.htm Please help to forward this email to all interested parties. Thank you. Lee-Yee Lau General Co-Chair, ATS'98 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % Paolo PRINETTO % % IEEE Computer Society % Test Technology Technical Committee (Vice Chair) % % Politecnico di Torino % Dip. di Automatica e Informatica % Corso Duca degli Abruzzi 24 % I-10129 Torino TO % Italy % % Tel: + 39 011 564.7007 % Fax: + 39 011 564.7099 % % E-mail: Paolo.Prinetto@polito.it % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% From pilz@ifi.unizh.ch Mon Nov 2 11:15:48 1998 +0100 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <08493-0@josef.ifi.unizh.ch>; Mon, 2 Nov 1998 11:15:30 +0100 Return-Path: X-Received: from exchange1.ntu.edu.sg by josef.ifi.unizh.ch with SMTP (PP) id <04573-0@josef.ifi.unizh.ch>; Sat, 31 Oct 1998 03:43:37 +0100 X-Received: by EXCHANGE1 with Internet Mail Service (5.5.2232.9) id ; Sat, 31 Oct 1998 10:40:13 +0800 Message-ID: <30C163033B80D111A5E008002BB53BBA016CDAD7@EXCHANGE1> From: ISIC99 To: ISIC99 Subject: ISIC-99: Call for papers Date: Sat, 31 Oct 1998 10:40:04 +0800 MIME-Version: 1.0 X-Mailer: Internet Mail Service (5.5.2232.9) Content-Type: text/plain; charset="iso-8859-1" ReSent-Date: Mon, 2 Nov 1998 11:15:23 +0100 (MET) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: ISIC-99: Call for papers ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 51 FIRST CALL FOR PAPERS ===================== ISIC-99: 8TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS, DEVICES & SYSTEMS 8 - 10 September 1999 Grand Hyatt Singapore ORGANIZERS: School of Electrical & Electronic Engineering Nanyang Technological University, Singapore And IEEE Singapore Section SUPPORTED BY: IEE Singapore Centre THE SYMPOSIUM The 8th International Symposium on Integrated Circuits, Devices and Systems, ISIC-99, will be held on 8-10 September 1999. This symposium provides a forum for integrated circuit designers, CAD developers, manufacturing engineers, and academics to present, share and discuss new research developments, future trends and innovative ideas. Keynote addresses will be delivered by Mark R. Pinto, Director, Silicon Electronics Research Laboratory, Bell Laboratories, Lucent Technologies; and Ingo Wolff, President, Institute of Mobile and Satellite Communication Techniques of Germany. Papers are solicited in subject areas including but not limited to the following: A. INTEGRATED CIRCUITS 1. Low-Power Low-Voltage IC 2. Memories 3. Mixed Signal Circuits 4. RF IC 5. IC Interconnections 6. Fault Tolerant Circuits 7. IC Sensors and MEMs 8. Switched Capacitor and Current Mode Circuits 9. Multiple-Valued Logic Circuits B. DEVICE AND IC TECHNOLOGY 1. Device Physics and Modeling 2. Scaling 3. Compound Semiconductor Devices 4. SOI 5. Testing and Yield Enhancement 6. Process Simulation 7. New Processes and Materials 8. Reliability and Failure Analysis 9. Assembly and Packaging C. INTEGRATED SYSTEMS AND APPLICATIONS 1. DSP ASIC 2. AD/DA Converters 3. Systems on a Chip 4. Multi-Media IC 5. Communication Integrated Circuits and Systems 6. FPGA/CPLD Applications 7. Neural Networks and Fuzzy Systems D. DESIGN AUTOMATION 1. Hardware Description Languages 2. Logic and System Synthesis 3. Simulation, Verification and Testability 4. Mixed Mode Simulation 5. AI Methodology 6. MCM Layout TUTORIAL SESSIONS Tutorial sessions on RF IC Design and Systems, DSP IC Design, HDL for Mixed Signal Design, and Dynamic Characterization of A/D Converters are planned on the first day of the symposium. Invitations are solicited for more tutorial topics of current interest. Participants who wish to contribute by giving tutorial sessions may submit proposals to the Organizing Committee. Proposed topics of sufficient interest among the delegates will be considered for the tutorials. EXHIBITION An exhibition of relevant equipment and systems will be held in conjunction with the regular sessions for paper presentations on the second and third day of the symposium. REGISTRATION FEE Tutorial 8 Sept. 1999 S$250 per session Payment to be made by 15 June 1999 (Fee includes tutorial handout, lunch, tea breaks and 3% GST) Symposium 9 & 10 Sept. 1999 Early Bird: S$680 (Payment to be made by 15 June 1999) Standard : S$780 (Payment after 15 June 1999) (Fee includes symposium proceedings, tea breaks, lunches, banquet and 3% GST) Exchange Rate : US$1 to S$1.7 (indicative) IMPORTANT DATES Submission of extended summary : 31 March 1999 Notice of acceptance : 30 April 1999 Submission of camera-ready papers : 15 June 1999 SUBMISSION OF PAPERS Authors are invited to submit three copies of an extended summary of not more than 1000 words and preferably with diagrams, illustrations and references by 31 March 1999. Please send summary to: ISIC-99 Secretariat Nanyang Technological University Conference Management Centre Administration Annex #04-06 Nanyang Avenue Singapore 639798 Republic of Singapore Tel: (65) 790-4723 Fax: (65) 793-0997 Email: isic99@ntu.edu.sg http: //www.ntu.edu.sg/home/isic99/ INTERNATIONAL ADVISORY COMMITTEE L Chan Chartered Semiconductor Manufacturing C Y Chang National Chiao Tung University Y C Jenq Portland State University Y C Liang IEEE Singapore Section K S Lock IEE Singapore Section M R Pinto Lucent Technologies M M Smith Sematech W Milne Cambridge University Y Takefuji Keio University H S Tan Nanyang Technological University C M Tang Lucent Technologies T L Tansley Macquarie University I Wolff Institute of Mobile and Satellite Communication Techniques ORGANIZING COMMITTEE Chairman Y C Tong Co-Chairman M A Do Advisor M H Er Secretary P K Chan Technical Program S S Rofail Publications & Publicity L S Ng Finance D J Ho Logistics T H Ooi IEEE Liaison M H Lim ======================================================================= 8TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS, DEVICES & SYSTEMS (ISIC-99) 8-10 September 1999, Grand Hyatt Singapore Preliminary Registration ( ) I intend to present a paper. The abstract is attached. Subject Area / Category (e.g. A1, B2, etc.) _____________________________________________________________________ _____________________________________________________________________ ( ) I intend to attend the conference. Please send me further details and the registration form. Family Name ____________________________________(Prof/Dr/Mr/Mrs/Ms) Given Name ____________________________________ Job Title ____________________________________ Organization ____________________________________ Address ____________________________________ ____________________________________ Country ____________________________________ Email ____________________________________ Telephone ____________________________________ Fax ____________________________________ +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ From pilz@ifi.unizh.ch Tue Nov 3 10:43:12 1998 +0100 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <11144-0@josef.ifi.unizh.ch>; Tue, 3 Nov 1998 10:42:53 +0100 Return-Path: X-Received: from pol88b.polito.it by josef.ifi.unizh.ch with SMTP (PP) id <08558-0@josef.ifi.unizh.ch>; Tue, 3 Nov 1998 09:26:03 +0100 X-Received: from chiusella.polito.it.polito.it (chiusella.polito.it) by polito.it (PMDF V4.2-15 #3020) id <01J3QCQW94NK8X0287@polito.it>; Tue, 3 Nov 1998 09:15:57 GMT+1 X-Received: by chiusella.polito.it.polito.it (4.1/SMI-4.1) id AA24480; Tue, 3 Nov 98 09:15:56 +0100 Date: Tue, 03 Nov 1998 09:15:56 +0100 From: tttc@chiusella.polito.it (Paolo Prinetto) Subject: IEEE TTTC - D&T CfT To: pilz@ifi.unizh.ch Message-id: <9811030815.AA24480@chiusella.polito.it.polito.it> X-Envelope-to: pilz@ifi.unizh.ch Content-transfer-encoding: 7BIT Apparently-To: PILZ Markus ReSent-Date: Tue, 3 Nov 1998 10:42:44 +0100 (MET) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: IEEE TTTC - D&T CfT ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 52 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % IEEE Computer Society % Test Technology Technical Committee % % % .... FOR YOUR INFORMATION.... % % A free service of the Technical Meeting Group % % % This message contains public information, only, and % the receiver is allowed, and invited, to copy it and % distribute it further. % % % For more information contact % or visit http://www.computer.org/tab/tttc/ % % If you would like to be removed from this mailing list, % please send an e-mail to % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% Call For Papers MEMS Design & Test IEEE Design and Test of Computers Special Issue Winter Issue of 1999 Guest Editors: Shawn Blanton, Carnegie Mellon University Bernard Courtois, TIMA Laboratory IEEE Design and Test of Computers seeks original manuscripts for a theme issue on the design and test of Microelectromechanical Systems (MEMS) scheduled to appear in the Winter issue of 1999. Articles concerning applied research and practical experience reports are solicited. The topics of interest include, but are not limited to: - Design and simulation tools - Synthesis tools - Fault models and failure mechanisms - Test methodology development - Test generation and fault simulation tools - MEMS design and/or test case studies Submitted articles must not have been previously published or currently submitted for publication elsewhere. Submit articles by January 15, 1999 to: Shawn Blanton, Guest Editor Dept. of Electrical and Computer Engineering 2109 Hamerschlag Hall Carnegie Mellon University 5000 Forbes Avenue Pittsburgh, PA 15213-3890, USA E-mail: blanton@ece.cmu.edu - Phone: +1 412-268-2987 - Fax: +1 412-268-1374 Authors should submit their original work to the guest editor by January 15, 1999, formatted according to the instructions below. Notification of acceptance will be sent May 15, 1999. Camera-ready copy for accepted papers will be due July 15, 1999. Important dates: January 15, 1999: Submission deadline May 15, 1999: Authors notified of acceptance with requested revisions July 15, 1999: Final copy due to Design & Test Managing Editor Winter 1999: Publication in IEEE Design and Test of Computers Please address all other correspondence regarding this special issue to: Bernard Courtois, Guest Editor TIMA Laboratory 46 Avenue Felix Viallet 38031 Grenoble Cedex, France E-mail: Bernard.Courtois@imag.fr - Phone: +33 4 76 57 46 15 - Fax: +33 4 76 47 38 14 Submission requirements: Send six (6) copies of the manuscript, in English. Manuscripts are not to exceed 35 double-spaced pages, inclusive of figures and tables, in A4 or 8.5 by 11 inches. Type size must be at least 12 point. Each copy of the manuscript must contain a cover page with author contact information (name, postal address, telephone number, and e-mail address) and a 100-word abstract. Manuscripts must be cleared for publication. Accepted manuscripts will be edited for technical content, structure, style, clarity, and grammar. Detailed information for authors can be found at the Computer Society D&T website at: http://www.computer.org/pubs/dt/d&t.htm %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % Paolo PRINETTO % % IEEE Computer Society % Test Technology Technical Committee (Vice Chair) % % Politecnico di Torino % Dip. di Automatica e Informatica % Corso Duca degli Abruzzi 24 % I-10129 Torino TO % Italy % % Tel: + 39 011 564.7007 % Fax: + 39 011 564.7099 % % E-mail: Paolo.Prinetto@polito.it % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% From pilz@ifi.unizh.ch Sun Nov 8 13:19:33 1998 +0100 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <23931-0@josef.ifi.unizh.ch>; Sun, 8 Nov 1998 13:19:23 +0100 Return-Path: X-Received: from isis.lip6.fr by josef.ifi.unizh.ch with SMTP (PP) id <14448-0@josef.ifi.unizh.ch>; Thu, 5 Nov 1998 21:17:02 +0100 X-Received: from src.lip6.fr (root@src.lip6.fr [132.227.64.100]) by isis.lip6.fr (8.8.8/jtpda-5.2.9.1+lip6) with ESMTP id VAA19266 for ; Thu, 5 Nov 1998 21:17:00 +0100 (MET) X-Received: from hephaistos.lip6.fr (fko@hephaistos.lip6.fr [132.227.64.27]) by src.lip6.fr (8.8.8/jtpda-5.2) with ESMTP id VAA00979 for ; Thu, 5 Nov 1998 21:21:59 +0100 From: Fabrice.Kordon@lip6.fr (Fabrice KORDON) X-Received: from (fko@localhost) by hephaistos.lip6.fr (8.8.6/jtpda-5.2) id VAA15432 for pilz@ifi.unizh.ch; Thu, 5 Nov 1998 21:16:16 +0100 (MET) Date: Thu, 5 Nov 1998 21:16:16 +0100 (MET) Message-Id: <199811052016.VAA15432@hephaistos.lip6.fr> To: pilz@ifi.unizh.ch Subject: Rapid System Prototyping - 1999 edition ReSent-Date: Sun, 8 Nov 1998 13:18:53 +0100 (MET) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: Rapid System Prototyping - 1999 edition ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 53 Please, feel free to forward this message to interested people. ======================================================================== ###### ##### ###### ##### ##### # # # # # # # # # # # # # # # # # # # ###### ##### ###### ###### ###### # # # # # # # # # # # # # # # # # ##### # ##### ##### ======================================================================== 10th IEEE International Workshop on Rapid System Prototyping June 16-18, 1999 Sheraton Sankley, Clearwater, Florida, U.S.A http://www-src.lip6.fr/rsp/ ======================================================================== The IEEE International Workshop on Rapid System Prototyping (RSP) presents and explores the trends in rapid prototyping of Computer Based Systems including, but not limited to, communication, information, and manufacturing systems. It aims to bring together researchers from both hardware and software to share their experience with rapid prototyping. The 10th annual workshop will focus on improved approaches to resolve prototyping issues and problems raised by incomplete specifications, increased system complexity and reduced time to market requirements for a multitude of products. The workshop will include a keynote presentation and formal paper sessions with a wide range of system prototyping topics including, but not limited to: * System Emulation * Virtual Prototyping * Hardware-Software Codesign * Tools for Hardware Prototyping * Tools for Software Prototyping * Methodologies for Hardware Prototyping * Methodologies for Software Prototyping * The Role of FPGAs in System Prototyping * Prototyping Case Studies * Very Large Scale System Engineering * Hardware/Software Tradeoffs * System Verification/Validation * Prototype to Product Transition * Prototyping of Real-Time Systems The program committee invites authors to submit a full paper (preferred) or an extended Summary. Submissions should be electronic in pdf format (preferred) or PostScript presenting original and unpublished work. Clearly describe the nature of the work, explain its significance, highlight its novel features, and state its current status. Authors of selected papers will be requested to prepare a manuscript for the workshop proceedings. Papers length should not exceed 7 pages in the standard IEEE format. * Papers due: January 29, 1999 * Notification of Acceptance: February 26, 1999 * Final Camera Ready Manuscript due: March 26, 1999 ======================================================================== From pilz@ifi.unizh.ch Sun Nov 8 00:28:03 1998 +0100 Return-Path: Received: from mail.cs.ucr.edu by josef.ifi.unizh.ch with SMTP (PP) id <18077-0@josef.ifi.unizh.ch>; Sun, 8 Nov 1998 00:27:58 +0100 Received: from hill.ucr.edu (hill.ucr.edu [138.23.169.109]) by barrichello.ucr.edu (8.8.8/8.8.8) with ESMTP id PAA04348 for ; Sat, 7 Nov 1998 15:27:06 -0800 From: Codes' 99 account Received: (from codes99@localhost) by hill.ucr.edu (8.8.8/8.8.8) id PAA31302 for codesign@ifi.unizh.ch; Sat, 7 Nov 1998 15:27:05 -0800 Date: Sat, 7 Nov 1998 15:27:05 -0800 Message-Id: <199811072327.PAA31302@hill.ucr.edu> To: codesign@ifi.unizh.ch Subject: 7t International Workshop on H/S Co-Design - CALL FOR PAPERS Status: RO X-Status: X-Keywords: X-UID: 54 Second call for Papers 7th International Workshop on Hardware/Software Co-Design CODES'99 Rome, Italy - May 3-5, 1999 http://www.cs.ucr.edu/codes99/ The CODES workshop is the major international forum for the presentation and exchange of ideas in the hardware/software co-design of embedded computing systems that include functionality mapped to both hardware and software processing components. Presentations and discussions address theoretical aspects, design methods, tools, and case studies. Areas of interest include, but are not limited to: * Computer-aided techniques for co-design: specification and modeling, design representation, simulation, synthesis, partitioning, estimation, formal verification, testing, design space exploration. * Software for co-design: software development environments, real-time operating systems, process scheduling, software synthesis, system integration, testbenches and testing, retargetable compilation. * Co-design architectures: distributed and multiprocessor architectures, hardware/software interfaces, prototyping approaches, emulation and debugging techniques, testing methods. * System development process: design methodology, concurrent engineering, design reuse, process management, intellectual property, system integration, case studies. The workshop's structure promotes active discussion among all participants in an informal setting, including short oral presentations of accepted papers followed by poster sessions for in-depth discussions. Paper submissions are due only a few months before the workshop, so that submissions may focus on the latest research. Publication of each accepted paper in the published workshop proceedings (by ACM SIGDA, in hardcopy, publicly-accessible web page, and CD-ROM compendium) is optional. Submission instructions: Submit one email message to codes99@cs.ucr.edu by January 8, 1999 with the following format: * Subject: CODES99 submission, Include-in-proceedings: {YES or NO}, Phone number of main contact, email addresses of all authors, URL of related work, title of the paper, number of pages in the paper, three key words describing the work, where you received your CFP, and then the paper itself in pdf (preferred) or postscript format (either attached or included in the email body itself). * The paper must be 5 pages or less, including figures and references, with a minimum font size of 9 pt, two-column format, as close as possible to camera ready. Please note that 5 pages is a hard limit. Submissions exceeding this limit will not be reviewed. It should be formatted for 8 inch by 11 inch paper (not A4 paper). Please note that larger-sized paper formats like A4 can cause significant printing difficulties in the U.S. * By submitting a paper, the author(s) agree that if the paper is accepted, to present the paper in person at the workshop, and if the paper is to be included in the proceedings, to prepare a final camera-ready version. * Proposals for group discussions may also be submitted. These should be 2 pages or less. * Notification of acceptance will be by February 24. Organizers: General Co-chairs Ahmed Amine Jerraya Luciano Lavagno System Level Synthesis Group Dipartimento di Elettronica TIMA Laboratory Politecnico di Torino 46 Avenue Felix Viallet Corso Duca degli Abruzzi 24 F-38031 Grenoble Cedex, FRANCE I-10129, Torino, ITALY Tel: +33 476 574 759 Tel: +39 11 564-4150 Fax: +33 476 473 814 Fax: +39 11 564-4099 Email: ahmed.jerraya@imag.fr Email: lavagno@polito.it Program Chair Frank Vahid Department of Computer Science University of California Riverside, CA 92521, USA Tel: +1 909 787-4710 Fax: +1 909 787-4643 Email: vahid@cs.ucr.edu Technical Program Committee Brian Bailey, Mentor Graphics, USA Tarek Ben-Ismail, HP Labs, Bristol, UK Gaetano Borriello, University of Washington, USA Joseph Buck, Synopsys, USA Raul Camposano, Synopsys, USA Giovanni De Micheli, Stanford University, USA Rolf Ernst, University of Braunschweig, D Daniel Gajski, University of California at Irvine, USA Rajesh Gupta, University of California at Irvine, USA Joerg Henkel, NEC, USA Ahmed Jerraya, TIMA, F Kayhan Kucukcakar, Escalade, USA Sanjaya Kumar, Honeywell, USA Luciano Lavagno, Politecnico di Torino, I Jan Madsen, Technical University of Denmark, DK Franz Rammig, C-Lab, Univ. of Paderborn, D Wolfgang Rosenstiel, University of Tubingen, D James Rowson, Cadence, USA Alberto Sangiovanni-Vincentelli, UC Berkeley, USA Miguel Santana, STMicroelectronics, F Don Thomas, Carnegie-Mellon University, USA Kees Vissers, Philips, NL Wayne Wolf, Princeton University, USA Hiroto Yasuura, Kyushu University, Japan Sponsored by: IEEE Computer Society, IEEE CAS, IFIP 10.5, ACM/SIGDA, ACM/SIGSOFT. From pilz@ifi.unizh.ch Thu Nov 12 14:11:09 1998 +0100 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <01823-0@josef.ifi.unizh.ch>; Thu, 12 Nov 1998 14:10:59 +0100 Return-Path: X-Received: from pol88b.polito.it by josef.ifi.unizh.ch with SMTP (PP) id <01519-0@josef.ifi.unizh.ch>; Thu, 12 Nov 1998 14:01:42 +0100 X-Received: from chiusella.polito.it.polito.it (chiusella.polito.it) by polito.it (PMDF V4.2-15 #3020) id <01J435ACRVLC8X49RQ@polito.it>; Thu, 12 Nov 1998 13:02:52 GMT+1 X-Received: by chiusella.polito.it.polito.it (4.1/SMI-4.1) id AA22562; Thu, 12 Nov 98 13:02:52 +0100 Date: Thu, 12 Nov 1998 13:02:52 +0100 From: tttc@chiusella.polito.it (Paolo Prinetto) Subject: IEEE TTTC - JETTA: CfP (Microprocessor Test and Verification) To: pilz@ifi.unizh.ch Message-id: <9811121202.AA22562@chiusella.polito.it.polito.it> X-Envelope-to: pilz@ifi.unizh.ch Content-transfer-encoding: 7BIT Apparently-To: PILZ Markus ReSent-Date: Thu, 12 Nov 1998 14:10:54 +0100 (MET) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: IEEE TTTC - JETTA: CfP (Microprocessor Test and Verification) ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 55 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % IEEE Computer Society % Test Technology Technical Committee % % % .... FOR YOUR INFORMATION.... % % A free service of the Technical Meeting Group % % % This message contains public information, only, and % the receiver is allowed, and invited, to copy it and % distribute it further. % % % For more information contact % or visit http://www.computer.org/tab/tttc/ % % If you would like to be removed from this mailing list, % please send an e-mail to % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% CALL FOR PAPERS Journal of Electronic Testing: Theory and Applications, Fall 1999 Special Issue on Microprocessor Test and Verification Guest Editor: Magdy Abadir, Motorola Because of the difficult test and verification challenges facing us today in various processor design environments, there has been a growing interest in exploiting techniques from the test field to solve problems in verification and vice versa. The walls that existed between the design engineers, test engineers and verification engineers are crumbling down opening the doors for many interesting possibilities to tackle the difficult problems that will be facing us in the new millennium. This special issue will focus on the common challenges and solutions for processor test and verification. Areas of interest include, but are not limited to: *Experiences on test and verification of high performance processors *Test/Verification of multimedia processors *Performance testing *High-level test generation for functional verification *Emulation techniques *Formal techniques and their applications *Verification coverage *Circuit level verification *Timing verification techniques *Path analysis for verification or test *Silicon debugging *Design error models *Design error diagnosis *Design for Testability or Verifiability INSTRUCTIONS FOR AUTHORS Papers will be selected through the journal's peer review process. Manuscripts should describe previously unpublished work and may be no longer than 30 pages of double-spaced text, figures, tables and references. The first page should include the title of the paper, full name(s) of the author(s), affiliation(s), complete postal and electronic mail addresses, telephone and FAX numbers, a statement clearly indicating that the manuscript is submitted to the special issue, an approximately 300-word abstract and a list of keywords that identify the central issues in the manuscript. Authors must follow JETTA's manuscript style given on the inside of the back cover of the journal and send six copies to: Ms. Cheryl Knight JETTA - Editorial Office Kluwer Academic Publishers 101 Philip Drive, Assinippi Park Norwell, MA 02061, U.S.A. To expedite the review process the authors should also electronically send a postscript version of their paper, and an abstract in ASCII with the paper title and author names, in separate files to the guest editor (abadir@ibmoto.com). Ms. Knight may be contacted by electronic mail (cknight@wkap.com) or phone (+1-781-871-6600) or FAX (+1-781-871-6528). On technical matters, contact the guest editor by electronic mail (abadir@ibmoto.com), or phone (+1-512-424-8192). DEADLINES Six copies of the manuscript are due by December 11, 1998 Notification of accepted papers will be sent by March 29, 1999 Final version of the manuscript will be due no later than May 30, 1999 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % Paolo PRINETTO % % IEEE Computer Society % Test Technology Technical Committee (Vice Chair) % % Politecnico di Torino % Dip. di Automatica e Informatica % Corso Duca degli Abruzzi 24 % I-10129 Torino TO % Italy % % Tel: + 39 011 564.7007 % Fax: + 39 011 564.7099 % % E-mail: Paolo.Prinetto@polito.it % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% From pilz@ifi.unizh.ch Mon Nov 16 18:01:48 1998 +0100 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <13027-0@josef.ifi.unizh.ch>; Mon, 16 Nov 1998 18:01:38 +0100 Return-Path: X-Received: from pol88b.polito.it by josef.ifi.unizh.ch with SMTP (PP) id <00628-0@josef.ifi.unizh.ch>; Mon, 16 Nov 1998 12:30:47 +0100 X-Received: from chiusella.polito.it.polito.it (chiusella.polito.it) by polito.it (PMDF V4.2-15 #3020) id <01J48I3IA6KW8X5G1W@polito.it>; Mon, 16 Nov 1998 09:03:09 GMT+1 X-Received: by chiusella.polito.it.polito.it (4.1/SMI-4.1) id AA09422; Mon, 16 Nov 98 09:03:05 +0100 Date: Mon, 16 Nov 1998 09:03:05 +0100 From: tttc@chiusella.polito.it (Paolo Prinetto) Subject: IEEE TTTC - TWS'99 : CfP To: pilz@ifi.unizh.ch Message-id: <9811160803.AA09422@chiusella.polito.it.polito.it> X-Envelope-to: pilz@ifi.unizh.ch Content-transfer-encoding: 8BIT Apparently-To: PILZ Markus ReSent-Date: Mon, 16 Nov 1998 18:01:32 +0100 (MET) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: IEEE TTTC - TWS'99 : CfP ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 56 2nd Call for Papers The 11th Workshop on äTest Technology and Reliability of Circuits and Systemsô sponsored by: Gesellschaft fuer Informatik (GI) Gesellschaft fuer Mikroelektronik (GMM) Informationstechnische Geselschaft (ITG) and the IEEE Test Technology Technical Committee (TTTC) will take place from Febr. 28th to March 2nd 1999 at Potsdam (Germany), Inselhotel This workshop has established itself as the most important German event in the area of test technology. In 1999, emphasis is on test and reliability aspects of complex core-based systems built from HW and SW components. Both scientific contributions and industrial reports on real-life problems and solutions are welcome. The workshop is jointly organized by: M. Goessel, University of Potsdam, and H. T. Vierhaus, Technical University of Brandenburg at Cottbus. Contributions in the following topic areas (not exclusively) are welcome: - specification of systems for test and reliability - validation and verification of test concepts - test and reliability in telecommunication systems - test and reliability in automotive applications - on-line test - fault tolerant circuits and systems - test and reliability of micro-systems - test of core-based HW / SW systems - testable design and self test for digital, digital / analog and for mechatronic systems - test generation and fault simulation for delay faults, sequential circuits, overcurrent effects, memory test Send a 3-4 pages abstract in English or German (3 copies or a postscript file) until Nov. 20th, 1998 to: H. T. Vierhaus Technical University of Brandenburg at Cottbus Computer Engineering Universit„tsplatz 3-4 P. O. Box 10 13 44 D-03013 Cottbus Germany email: htv@informatik.tu-cottbus.de Further information: http://www.informatik.tu-cottbus.de/˙wwwteci/ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % IEEE Computer Society % Test Technology Technical Committee % % % .... FOR YOUR INFORMATION.... % % A free service of the Technical Meeting Group % % % This message contains public information, only, and % the receiver is allowed, and invited, to copy it and % distribute it further. % % % For more information contact % or visit http://www.computer.org/tab/tttc/ % % If you would like to be removed from this mailing list, % please send an e-mail to % % % Paolo PRINETTO % Test Technology Technical Committee (Vice Chair) % % Politecnico di Torino % Dip. di Automatica e Informatica % Corso Duca degli Abruzzi 24 % I-10129 Torino TO % Italy % % Tel: + 39 011 564.7007 % Fax: + 39 011 564.7099 % % E-mail: Paolo.Prinetto@polito.it % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% From pilz@ifi.unizh.ch Thu Nov 26 15:23:38 1998 +0100 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <07377-0@josef.ifi.unizh.ch>; Thu, 26 Nov 1998 15:23:07 +0100 Return-Path: X-Received: from picolit.diegm.uniud.it by josef.ifi.unizh.ch with SMTP (PP) id <06079-0@josef.ifi.unizh.ch>; Thu, 26 Nov 1998 14:43:14 +0100 X-Received: from localhost (localhost [127.0.0.1]) by picolit.diegm.uniud.it (8.6.9/8.6.9) with SMTP id OAA00967; Thu, 26 Nov 1998 14:37:16 +0100 Message-Id: <199811261337.OAA00967@picolit.diegm.uniud.it> X-Authentication-Warning: picolit.diegm.uniud.it: Host localhost didn't use HELO protocol X-Mailer: exmh version 1.6.9 8/22/96 To: mrs8n@mrssun.ee.virginia.edu, isss-people@ics.uci.edu, codesign@ifi.unizh.ch Subject: CFP: International Workshop on Logic Synthesis Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Date: Thu, 26 Nov 1998 14:37:14 +0100 From: Luciano Lavagno ReSent-Date: Thu, 26 Nov 1998 15:23:00 +0100 (MET) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: CFP: International Workshop on Logic Synthesis ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 57 (apologies for duplicates of this message) ------------------------------------------------------------------------ International Workshop on Logic Synthesis Granlibakken Resort, Lake Tahoe, California June 27-30, 1999 Call for Participation Logic Synthesis has traditionally been focused on optimization techniques for combinational and sequential circuits through the manipulation of Boolean equations and state machines. IWLS '99, the eighth workshop in this series, seeks papers both on these topics and on new directions in synthesis-based design methodology. Topics of interest include (but are not limited to): Area, timing, power optimization Logic synthesis systems CMOS, ECL, GaAs optimization Designer experiences with synthesis Interface specification and synthesis Digital noise and EMI avoidance Two-Level logic optimization Interaction with physical design Multi-Level logic optimization Incremental synthesis and ECO FSM optimization and encoding Asynchronous logic synthesis Sequential circuit optimization Reachability and coverage analysis Formal verification Retiming and resynthesis Optimization at the RTL level Technology mapping Timing verification FPGA and PLD synthesis Testing and synthesis for test Don't-cares and Boolean Relations Interaction with module generators Symbolic Synthesis Use of synthesis in new applications SAT Algorithms and applications Reconfigurable computing The traditional goal of IWLS has been to foster presentation of new ideas and work in early stages of development. For this reason, the program is very open, with high acceptance rate, heavy use of posters and short talks for presentation, and large amounts of time in the schedule for discussions around posters. Focus group discussions are also used to encourage exchange of ideas among all the participants on "hot", new and controversial topics. Authors may submit extended abstracts for their proposed presentation. These must be no less than 1000 words and no greater than 2500 words (4 pages). These abstracts are not intended to be complete papers, but rather should contain the idea of the proposed presentation. We encourage submissions in the early stages of research which may highlight important new problems without necessarily providing complete solutions. The abstracts should be submitted by e-mailing self-contained Postscript, PDF or HTML files (regular mail submissions are not accepted) to: iwls-submit@gandalf.polito.it by March 15, 1999. Acceptance notices will be sent by April 1, 1999. A set of workshop notes will be distributed to the participants. There will be no published proceedings. Authors can request their contribution not to be included in the notes. IWLS '99 WEB site: http://www.diegm.uniud.it/iwls99 ------------------------------------------------------------------------ General chair: Fabio Somenzi, University of Boulder, (303) 4430254 fabio@duke.colorado.edu Program chair: Luciano Lavagno, Universita' di Udine, +39 0432558288 lavagno@diegm.uniud.it Technical Program Committee Pranav Ashar NEC C&C Labs Yusuke Matsunaga Fujitsu Labs Luca Benini U. di Bologna Shin-Ichi Minato NTT Michel Berkelaar TU-Eindhoven Jose Monteiro U. Tecnica de Lisboa Robert Brayton U.C. Berkeley Steven Nowick Columbia University Franc Brglez North Carolina S.U. Massoud Pedram U. Southern Cal. Jordi Cortadella U. Pol. de Catalunya Tsutomu Sasao Kyushu Inst. of Tech. Masahiro Fujita Fujitsu Labs Hamid Savoj Magma Design Automation Wolfgang Kunz U. of Frankfurt Ellen Sentovich Cadence Berkeley Labs Luciano Lavagno U. di Udine Narendra Shenoy Synopsys Sharad Malik Princeton U. Fabio Somenzi U. of Colorado Diana Marculescu U. of Maryland Leon Stok IBM Watson Res. Center ------------------------------------------------------------------------ From pilz@ifi.unizh.ch Fri Dec 4 10:55:33 1998 +0100 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <25825-0@josef.ifi.unizh.ch>; Fri, 4 Dec 1998 10:55:23 +0100 Return-Path: X-Received: from alps.ecn.purdue.edu by josef.ifi.unizh.ch with SMTP (PP) id <09636-0@josef.ifi.unizh.ch>; Thu, 3 Dec 1998 05:37:49 +0100 X-Received: (from eigenman@localhost) by alps.ecn.purdue.edu (8.8.8/8.8.8moyman) id WAA20980; Wed, 2 Dec 1998 22:55:14 -0500 (EST) Date: Wed, 2 Dec 1998 22:55:14 -0500 (EST) Message-Id: <199812030355.WAA20980@alps.ecn.purdue.edu> From: Rudi Eigenmann To: Subject: Call for participation ReSent-Date: Fri, 4 Dec 1998 10:55:04 +0100 (MET) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: Call for participation ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 58 Call for Participation Workshop on Performance Evaluation with Realistic Applications Sponsored by the Standard Performance Evaluation Corporation (SPEC) - Held in conjunction with the SPEC Joint Meeting, January 27-29, 1999. Date: Monday, January 25, 1999 Location: Hyatt Hotel, San Jose, Calif. Cost: Free (pre-registration is required) The Standard Performance Evaluation Corporation (SPEC), known for its benchmark development, has a broad industrial member base. Although SPEC benchmarks are quite widely used in academic research as well, there has not been an active dialog between the SPEC membership and the research community in developing and using benchmarks and performance evaluation methodologies. The 1-day workshop intends to bridge this gap. Participants are invited to present research results that make use of SPEC benchmarks, describe studies with applications that may be used as next-generation benchmarks, discuss issues and solutions in developing new benchmarks, and present novel approaches for evaluating research results. In addition, SPEC members will be presenting their benchmark suites. There will be a panel to discuss the role of SPEC benchmarks, other benchmarks, and suggestions for future improvements. Selected presentations from the workshop are planned for publication as a special issue in a performance evaluation journal. Workshop attendees are invited to attend one or several sessions of the SPEC annual meeting, which is held on the three days following the workshop. An agenda with the open SPEC meetings will be made available to all workshop participants. At the 1999 annual meeting SPEC willcelebrate its 10th anniversary! Deadlines: December 15, 1998: Intent to participate. Send 100-200 word abstract to specworkshop@spec.org December 22, 1998: Notification of accepted presentations January 5, 1999: 1-page abstract of presentations due at specworkshop@spec.org January 5, 1999: Pre-registration (free) for attendees without presentation (registration information will be posted at www.spec.org) Workshop Coordinators: Rudolf Eigenmann, Purdue University, eigenman@purdue.edu, +1.765.494.1741 Reinhold Weicker, Siemens AG, weicker.pad@sni.de, +49.5251.8.12766 For more information: Please contact Liz Zapf, SPEC, info@spec.org, +1.703.331.0180 From pilz@ifi.unizh.ch Fri Dec 4 12:40:37 1998 +0100 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <25729-0@josef.ifi.unizh.ch>; Fri, 4 Dec 1998 10:51:17 +0100 Return-Path: X-Received: from viper.ics.ele.tue.nl by josef.ifi.unizh.ch with SMTP (PP) id <18012-0@josef.ifi.unizh.ch>; Thu, 3 Dec 1998 11:38:40 +0100 X-Received: from akebono.ics.ele.tue.nl (akebono.ics.ele.tue.nl 131.155.40.19) by viper.ics.ele.tue.nl (8.8.7/1.57) id LAA17435; Thu, 3 Dec 1998 11:38:33 +0100 (MET) X-Received: by akebono.ics.ele.tue.nl (Postfix, from userid 8003) id B62AC1299; Thu, 3 Dec 1998 11:35:04 +0100 (MET) From: lech@ics.ele.tue.nl Sender: lech@ics.ele.tue.nl Subject: EUROMICRO'99 DSD Workshop, Call for Papers Reply-To: lech@ics.ele.tue.nl Message-Id: <19981203103504.B62AC1299@akebono.ics.ele.tue.nl> Date: Thu, 3 Dec 1998 11:35:04 +0100 (MET) ReSent-Date: Fri, 4 Dec 1998 10:50:57 +0100 (MET) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: EUROMICRO'99 DSD Workshop, Call for Papers ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 59 _________________________________________________________________ We apologize if you receive multiple copies of this message. Please, feel free to distribute it to interested persons. _________________________________________________________________ ***************************************************************** * EUROMICRO'99 * * 25th Anniversary EUROMICRO Conference * * Workshop on Digital System Design * * Milan, Italy, September 8th-10th, 1999 * ***************************************************************** Dear Colleague, On behalf of both the EUROMICRO Association and the Organizing Committee of the EUROMICRO'99 Conference, I cordially invite you to submit papers and attend the 25th Anniversary EUROMICRO Conference, taking place in Milan, Italy, September 8th-10th, 1999. Building on a more than twenty-year lasting successful history of the EUROMICRO Association and EUROMICRO Conferences, we have introduced a new multiple workshop structure of the Conferences. After a great success of the EUROMICRO'98 Conference, we are continuing with this multiple workshop structure. The 25th Anniversary EUROMICRO'99 Conference solicits the submission of papers for the following workshops: · Digital System Design: Architectures Methods and Tools · Dependable Computing Systems · Software Process and Product Improvement · Multimedia and Telecommunication · Music Technology and Audio Processing There will be many special events during this Silver Anniversary Conference. Two of them of a particular interest are perhaps the following: · "Back to the Future: Microprocessors for the 21st Century" - five keynote speakers from the top microprocessor companies will reveal their plans for future architectures, and · "Music Technology: Live and Loud" - a number of concerts will be given with use of the recent music technology and a conference CD will be produced. The EUROMICRO Workshop on Digital System Design: Architectures Methods and Tools was the largest and a very successful workshop of the EUROMICRO'98 Conference. The mission of the Digital System Design Workshop is to be the superior-quality discussion forum of the state-of-the-art research, development and applications for the computer system architecture and design automation communities. The Workshop addresses both architectures and implementations of (embedded) computer systems as well as efficient design methods and tools. Please, find below the call for papers of the Digital System Design Workshop and the http links to the additional up-to-date information on the Workshop and EUROMICRO'99 Conference. I am looking forward to see you at the EUROMICRO'99 Conference, Lech Jozwiak, Member of the Board of Directors of the EUROMICRO Association Program Chair of the EUROMICRO Workshop on Digital System Design _______________________________________________________________________________ EUROMICRO'99 EUROMICRO WORKSHOP on DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS Milan, Italy, September 8 - 10, 1999 _______________________________________________________________________________ CALL FOR PAPERS The workshop on Digital System Design addresses both architectures and implementations of (embedded) computer systems as well as efficient design methods and tools. It is a discussion forum of the state-of-the-art research, development and applications for the computer system architecture and design automation communities. TOPICS OF INTEREST include but are not limited to: CPU and memory architectures: arithmetic and logic units, co-processors, pipelining, superscalarity, cache, MMU. Special architectures: DSP, ASIPs, graphic and image processors, custom computing machines, processing arrays and FPGAs, reconfigurable structures, dependable structures. Specification and modeling: (hardware/software) system specification and modeling, system and hardware description languages, component modeling. Validation: simulation, emulation, prototyping and testing at the system, RT and logic level; multilevel- and co-simulation; formal verification. Synthesis: system on chip design; system, hardware-software, high-level, RT-level and logic synthesis; intellectual property and design reuse; synthesis for low-power, speed and testability; system, hardware/software and logic partitioning. SUBMISSION OF PAPERS Prospective authors are encouraged to submit by Internet (http://www.ics.ele.tue.nl/DSD-99) or e-mail (LECH@ics.ele.tue.nl) PostScript version of their full paper to the program chairman. If electronic submission is not possible, four copies of the full paper should be sent by post. The paper should not exceed 4000 words and include an abstract of up to 150 words. The title page should clearly show the name, mailing address, the e-mail address and the fax number of the author to contact as well as the topic areas of the submitted paper. The following signed statement should be included on the title page: All necessary clearances have been obtained for the publication of this paper. If accepted, the author(s) will prepare the final camera-ready manuscript in time for inclusion in the proceedings, and will personally present the paper at the workshop. The program committee will decide for each accepted paper if it will be presented in a long (30 min.) or short (15 min.) presentation or as a poster. The long and short presentation papers 8 pages will be assigned and the poster papers 4 pages will be assigned in the proceedings. Papers exceeding 8 pages will be charged NLG 100 per page in excess. The proceedings will be published by the IEEE Computer Society. IMPORTANT DATES * Deadline for submission: February 28, 1999 * Notification of acceptance: April 30, 1999 * Deadline for final version: June 15, 1999 SPECIAL SESSIONS, PANELS AND TUTORIALS Proposals of special sessions, panels and tutorials are welcome. Please send suggestions to the program chairman before the paper submission deadline. GENERAL INFORMATION Milan is located in North Italy close to Alps. It has convenient direct flight connections with many European and other airports. It has also train connections with many European towns. ADDITIONAL UP-TO-DATE INFORMATION http://www.ics.ele.tue.nl/DSD-99 GENERAL INFORMATION ON EUROMICRO'99 CONFERENCE http://www.amp.york.ac.uk/external/milan/web/welcome/front.htm _______________________________________________________________________________ REFERENCE ADDRESSES Program Chair: Lech Józwiak Eindhoven University of Technology, Faculty of Electrical Engineering P.O. Box 513, EH 10.25 5600 MB Eindhoven, The Netherlands Tel: +31.40.2473645 Fax: +31.40.2433066 e-mail: LECH@ics.ele.tue.nl Steering Committee: L. Józwiak Program Chair, Eindhoven U. of Tech. (NL) K. Kuchcinski Past Program Chair, Linköping U. (S) A. Nunez Deputy Program Chair, U. of Las Palmas (E) Organizing Chair: Mariagiovanna Sami Department of Electronics and Inform. Politecnico di Milano Piazza Leonardo da Vinci 32, I-20133 Milano, Italy Tel: +39 2 2399 3516 Fax: +39 2 2399 3411 e-mail: sami@elet.polimi.it Deputy Organizing Chair: N. Scarabottolo, Pol. di Milano (I) _______________________________________________________________________________ Program Committee M. Anido, U. of Rio de Janeiro (BR) S. Baranov, Ben-Gurion U. (IL) R. Drechsler, A-L U. Freiburg (D) N. Dutt, U. of Calif., Irvine (USA) P. Eles, U. of Timisoara (RO) M. Fernandez, U. Complutense (E) M. Glesner, Darmstadt U. of Tech. (D) A. Gonzalez, U. Pol. De Catalunya (E) E. Gramatová, Slovak Ac. of Sci. (SLO) L. Józwiak, Eindhoven U. of Tech. (NL) K. Judmann, U. of Vienna (A) K. Kuchcinski, Linköping U. (S) L. Lindh, Mälardalen U. (S) T. Luba, Warsaw U. of Tech. (PL) J. Madsen Tech. Univ. of Denmark (DK) A. Nunez, U. of Las Palmas (E) A. Paschalis, Inst. of Inf. & Telec.(Gr) A. Pawlak, IRESTE, Nantes (F) M. Perkowski, Portland St. U. (USA) A. Postula, U. of Queensland (AU) B. Rouzeyre, U. Montpellier II (F) M. Sami, Pol. di Milano (I) T. Sasao, Kyushu Ins. of Techn. (J) G. Saucier, INPG/CSI (F) N. Scarabottolo, Pol. di Milano (I) H. Selvaraj, Monash U. (AU) J. Sosnowski, Warsaw U. of Tech. (PL) M. Stevens, Eindhoven U. (NL) D. Tabak, George Mason U. (USA) F. Vajda, KFKI-MSZKI (H) M. Valero, U. Pol. de Catalunya (E) K. Waldschmidt, J. W. Goethe U. (D) C. Wolinski, IRISA, Rennes (F) H. Yasuura, Kyushu U. (J) From pilz@ifi.unizh.ch Tue Dec 8 14:03:41 1998 +0100 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <10671-0@josef.ifi.unizh.ch>; Tue, 8 Dec 1998 13:06:29 +0100 Return-Path: X-Received: from tik2.ethz.ch by josef.ifi.unizh.ch with SMTP (PP) id <10594-0@josef.ifi.unizh.ch>; Tue, 8 Dec 1998 13:03:22 +0100 X-Received: from tik.ee.ethz.ch (tec16 [129.132.119.16]) by tik2.ethz.ch (8.8.8/8.8.8) with ESMTP id NAA09850 for ; Tue, 8 Dec 1998 13:03:21 +0100 (MET) Sender: platzner@tik.ee.ethz.ch Message-ID: <366D1589.3035D440@tik.ee.ethz.ch> Date: Tue, 08 Dec 1998 13:03:21 +0100 From: Marco Platzner Organization: Swiss Federal Institute of Technology (ETH) X-Mailer: Mozilla 4.5 [en] (X11; I; SunOS 5.5.1 sun4u) X-Accept-Language: en MIME-Version: 1.0 To: codesign@ifi.unizh.ch Subject: Job opportunities at ETH Zurich Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit ReSent-Date: Tue, 8 Dec 1998 13:06:01 +0100 (MET) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: Job opportunities at ETH Zurich ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 60 Open Positions for Research Assistants The Computer Engineering and Networks Laboratory invites applications for the position of doctoral assistants in the Computer Engineering Group. We are engaged in several research projects in the areas of modeling, simulation, and design of hardware/software systems. We have open positions for research assistants in the following projects: A) Design of Embedded Hardware/Software Systems In this project we develop novel and efficient automated design methods for complex hardware/software systems. Currently investigated topics include design space exploration with evolutionary algorithms, applications of dynamically reconfigurable hardware, and interface/communication synthesis. B) Modeling and Simulation of Heterogeneous Systems In this interdisciplinary project we develop methods and tools for modeling and simulation of systems consisting of electronic and mechanical components. Currently investigated topics include the integration of different simulation methodologies, 3-D visualization and animation of simulated systems, and the generation of virtual prototypes. This project is carried out in close cooperation with industry. Candidates with a background in engineering or applied sciences and a strong motivation to work in one of these challenging areas are encouraged to apply. The open positions should lead to a doctoral degree in electrical engineering within approximately 3 years. The ETH Zurich as one of the top technical universities offers an excellent infrastructure and attractive conditions. Applicants should direct questions or send a detailed curriculum vitae to: Prof. Dr.-Ing. Lothar Thiele Institute TIK ETH Zentrum, Gloriastr. 35 8092 Zurich, Switzerland phone: +41 1 632 7031 fax: +41 1 632 1035 e-mail: thiele@tik.ee.ethz.ch http://www.tik.ee.ethz.ch/~tec Best Regards, Marco Platzner. ______________________________________________________________________ _/_/_/_/ _/ _/ _/ Dr. Marco Platzner _/_/_/_/_/_/_/ _/ _/ _/ _/ _/ Institute TIK, ETZ G-85 _/ _/ _/ _/ _/ _/ _/_/ Gloriastr.35 _/_/_/ _/ _/_/_/_/ _/ _/ _/ _/ CH-8092 Zurich _/ _/ _/ _/ / _/ _/ _/ Switzerland _/_/_/ _/ _/ _/ phone: +41-1-6327544 mailto:platzner@tik.ee.ethz.ch fax: +41-1-6321035 http://www.tik.ee.ethz.ch/~platzner Computer Engineering and Communication Networks Lab Swiss Federal Institute of Technology (ETH) Zuerich ______________________________________________________________________ From pilz@ifi.unizh.ch Mon Dec 14 10:47:56 1998 +0100 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <28815-0@josef.ifi.unizh.ch>; Mon, 14 Dec 1998 10:47:36 +0100 Return-Path: X-Received: from rasips1.rasip.fer.hr by josef.ifi.unizh.ch with SMTP (PP) id <29918-0@josef.ifi.unizh.ch>; Fri, 11 Dec 1998 14:38:47 +0100 X-Received: (from wdta@localhost) by rasips1.rasip.fer.hr (8.8.8/8.8.8) id OAA17267 for pilz@ifi.unizh.ch; Fri, 11 Dec 1998 14:35:01 +0100 (MET) From: WDTA Message-Id: <199812111335.OAA17267@rasips1.rasip.fer.hr> Subject: Please read - WDTA 99 To: pilz@ifi.unizh.ch Date: Fri, 11 Dec 1998 14:34:58 +0100 (MET) X-Mailer: ELM [version 2.4ME+ PL31 (25)] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit ReSent-Date: Mon, 14 Dec 1998 10:46:47 +0100 (MET) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: Please read - WDTA 99 ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 61 Please read .. sorry if you have received this already ------ cut here --------- please feel free to distribute ------------- Call for Papers SUBMISSION DEADLINE MARCH 1st -------------------------------------------------------------- | 1999 International Workshop on Design, Test and Applications | -------------------------------------------------------------- Dubrovnik President Hotel, Dubrovnik, Croatia, June 14-16, 1999. Aim of the 1999 Workshop on Design, Test and Application (WDTA '99) is to present novel industrial and academic research and development achievements, trends and forecasts in the area of electronic design, test and wide variety of applications. The Workshop will emphasis design methodologies and novel architectures for real world applications. WDTA will also be a place to share ideas between participants, learn most recent developments and present commercial solutions. --------------------- | IN COOPERATION WITH | --------------------- - IEEE Region 8 - IEEE Croatia Section - IEEE Computer Society Croatia Section ---------- | SPONSORS | ---------- - Faculty of Electrical Eng. and Computing, University of Zagreb - Croatian Ministry of Science and Technology TOPICS OF INTEREST: ------------------- WDTA '99 SPECIAL SESSION: Multimedia chips and architectures Submissions are being solicited for topics of interest that include, but are not limited to: System and design methodologies Specification languages High-level synthesis Hardware/software codesign Modeling and simulation Design reuse, IP issues Design process management Implementation issues of real-world applications VLSI systems Mixed signal circuits, subsystems and systems System-on-a-chip architectures Low power /high performance design Physical design Testing of analog, digital, and mixed circuits Microsystems and applications Reconfigurable systems Configurable computing PLD/FPGA architectures CAD algorithms Novel applications Multimedia and digital content Audio and image processing architectures Compression/decompression algorithms Secure content distribution Embedded and real-time systems Consumer electronic designs Electronic education Teleteaching WWW-based curricula SUBMISSION REQUIREMENTS: ------------------------ Four page paper must be electronically submitted by email (wdta@wdta.hr) following the instructions listed below. Email submission must contain: 1. Author(s) name(s) and title(s), 2. Affiliation(s), 3. Full correspondence address, phone and fax number and email address of principal author with the statement: "If paper is accepted at least one of the authors will register and present the paper at the Workshop" (1-3 all in ASCII format) and 4. Full paper (max four pages including text and figures in PDF or Postscript format). IMPORTANT DATES: ---------------- Special session proposals February 15, 1999. !!!!! Submission deadline March 1, 1999. !!!!!! Notification of acceptance March 25, 1999. Final papers deadline May 7, 1999. Advanced registration deadline May 14, 1999. Workshop June 14-16, 1999. WDTA WEB page: http://www.wdta.hr E-mail: wdta@wdta.hr OFFICIAL LANGUAGE ----------------- Official language of the Workshop will be English. LOCATION & TRAVEL ----------------- "Those who seek paradise on Earth should come to Dubrovnik and see Dubrovnik" (Bernard Shaw). Dubrovnik will be just the way you are yourself when you come to it. And you will leave it the way Dubrovnik is. Unique. Perfect. Average temperature of 21.9 degrees Celsius (72 F) and see warm enough for swimming (avg. temp 20.9C=69F) makes June best time to visit Dubrovnik and see it's cultural heritage. More details on Dubrovnik, tourist and travel information can be found on WDTA WEB page. UNIVERSITY BOOTH ---------------- University booth will be organized where student research results can be presented. For more details please contact General Chair. REGISTRATION ------------ Registration details can be found on WDTA WEB page or can be requested by sending email to wdta@wdta.hr. Limited number of rooms at reduced rates have been reserved for WDTA participants and therefore advanced registration is encouraged. Inexpensive student accommodation will also be available. COMMERCIAL PRESENTATIONS & EXHIBITION ------------------------------------- Commercial Exhibition will be organized during the Workshop, focussing on electronic components (such as PLDs/FPGAs), design tools, test and measurement equipment and computer and networking equipment. Please see if your company or company you do business with would be interested in presenting the products. Our intention is to focus on Central and Eastern Europe markets. For further information please contact General Chair. General Chair: -------------- Mario Kovac University of Zagreb FER, Unska 3 10000 Zagreb, Croatia tel: +385 1 6129-759 fax: +385 1 6129-809 email: mario.kovac@fer.hr WDTA Program Co-Chairs: ----------------------- Sorin Alexander Huss Darmstadt Univ. Germany mailto://huss@vlsi.informatik.tu-darmstadt.de Alex Veidenbaum Univ. of California Irvine USA mailto://alexv@enterprise.ics.uci.edu Program Committee: ------------------ -Stephen P. Athan, Univ. of South Florida, USA -Magdy Bayoumi, Univ. of Southwestern Louisiana, USA -Ivo Bolsens, IMEC, Belgium -Stephen D.Brown, University of Toronto, Canada -Bernard Courtois, TIMA CMP, France -Nikil Dutt, Univ. of California Irvine, USA -Daniel D. Gajski, Univ. of California Irvine, USA -Francesco Gregoretti, Politecnico di Torino, Italy -Roman Hermida, Univ. Complutense, Spain -Slavko Krajcar, University of Zagreb, Croatia -Fadi Kurdahi, Univ. of California Irvine, USA -Nakamura Yukihiro, Univ. Kyoto, Japan -Franc Novak, Institut Jozef Stefan, Slovenia -Thomas Olbrich, AMS International AG, Austria -Franz Josef Rammig, Univ. Paderborn/HNI, Germany -N. Ranganathan, Univ. of South Florida, USA -Marta Rencz, MicReD Ltd, Hungary -Slobodan Ribaric, University of Zagreb, Croatia -Rhondalee Rohleder, QuickLogic Corporation,USA -Elias K. Stefanakos, Univ. of South Florida, USA -Raimund Ubar, Tallinn Technical Univ., Estonia -Idalina J. M.Videira, IST/INESC, Portugal -Zvonko G. Vranesic, University of Toronto, Canada -Norbert Wehn, Univ. Kaiserslautern, Germany -Mladen Victor Wickerhauser, Washington Univ. in St. Louis, USA -Mario Zagar, University of Zagreb, Croatia -Baldomir Zajc, Univ. of Ljubljana, Slovenia -Yervant Zorian, LogicVision, Inc., USA ------------------------------ | SUBMISSION DEADLINE MARCH 1st| ------------------------------ From pilz@ifi.unizh.ch Sat Dec 19 18:23:17 1998 +0100 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <23781-0@josef.ifi.unizh.ch>; Sat, 19 Dec 1998 18:22:54 +0100 Return-Path: X-Received: from viper.ics.ele.tue.nl by josef.ifi.unizh.ch with SMTP (PP) id <22602-0@josef.ifi.unizh.ch>; Wed, 16 Dec 1998 14:47:50 +0100 X-Received: from akebono.ics.ele.tue.nl (akebono.ics.ele.tue.nl 131.155.40.19) by viper.ics.ele.tue.nl (8.8.7/1.57) id OAA10900; Wed, 16 Dec 1998 14:47:49 +0100 (MET) X-Received: by akebono.ics.ele.tue.nl (Postfix, from userid 8016) id 043F912D6; Wed, 16 Dec 1998 14:45:46 +0100 (MET) From: lech@ics.ele.tue.nl Sender: lech@ics.ele.tue.nl Subject: FDL'99 Call for Contributions Reply-To: lech@ics.ele.tue.nl Message-Id: <19981216134546.043F912D6@akebono.ics.ele.tue.nl> Date: Wed, 16 Dec 1998 14:45:46 +0100 (MET) ReSent-Date: Sat, 19 Dec 1998 18:22:49 +0100 (MET) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: FDL'99 Call for Contributions ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 62 Dear Colleagues, please consider submission of your papers to the FDL'99 - the International Forum on Design Languages that will be held in the Ecole Normale Superieure de Lyon, Aug 30-Sept 3,1999. FDL'99 is composed of three topical workshops: * FDL Workshop with VHDL Users' Forum in Europe (Aug. 31-Sept.1) * Workshop on Virtual Component Design & Reuse (Sept. 1-2) and * Workshop on System Specification & Design Languages (Sept.2-3) Please find below the FDL'99 Call for Papers. With best regards, Lech Jozwiak FDL'99 Program Committee Member _____________________________________________________________________ This message contains public information, only, and the receiver is allowed, and invited, to copy it and distribute it further. Our apologies if you received duplicates of this message due to the mailing list aliases. You can also visit the FDL'99 web site at http://www.ecsi/org/ecsi/fdl The ECSI Team _______________________________________________________________________ ******************************************************************* * FDL'99 * * FORUM ON DESIGN LANGUAGES * * HDL Workshop with VHDL Users' Forum in Europe (Aug. 31-Sept.1) * * Workshop on Virtual Component Design & Reuse (Sept. 1-2) * * Workshop on System Specification & Design Languages (Sept.2-3) * * Ecole Normale Superieure de Lyon, Aug 30-Sept 3,1999 * ******************************************************************* A SIG-VHDL event sponsored by ECSI, co-sponsored by IFIP 10.5, VI, OVI, ITG, GI, GMM featuring CALL FOR CONTRIBUTIONS _____________________________________________________________________ The Forum on Design Languages (FDL) is the European forum to ex-change experiences and to learn about new efforts and trends in the appli-cation of languages and their associated design methods and tools in mi-cro-electronic design. It is a multi-facetted event that offers a wonderful opportunity to get up-to-date information thanks to hosting several events at the same time and the same location, namely: The HDL Workshop with the VHDL Users' Forum in Europe (HDL&VUFE) is the European event that gathers together VHDL and other HDL users. It provides a complete snapshot of the status of the practical use of the VHDL and other hardware description languages in the electronic design community, covering the aspects of (formal) specification, modeling, simulation, synthesis, and testing. It also provides an update on the latest developments and trends in the evolution of these languages through standardization projects, and an opportunity to contribute to these efforts. The Workshop on Virtual Component Design & Reuse (VCDR) follows up two occurrences of the Workshop Reuse Techniques for VLSI Design in Karlsruhe in 1997 and 1998. It is the annual event dedicated to a broad spectrum of digital and analog VC reuse. The main objective is to present new ideas and methodologies for reuse and IP. Contributions from industry and research institutions will be presented from the do-mains of commercial systems, upcoming development trends and stan-dardization activities. The workshop addresses all aspects of research and development for de-sign reuse and VCs at all relevant levels of abstraction. The Workshop on System Specification & Design Languages (SSDL) continues the SLDL workshop held 4 times (Dallas-1996, Santa Clara-1997, Barga-1997, Lausanne-1998) and is aimed at becoming THE yearly event on this subject. It addresses the need to develop industry-wide consensus on the key problems met by the designers of Systems on a Chip (SoC) as they relate to e.g. the description of design specification, functional and implementa-tion constraints, usability by EDA tools. It aims at developing coordinated industry standards. The workshop will address all topics relevant to the SoC's, that can in-clude digital hardware, analog hardware, software, sensors, micro- me-chanical components (MEMs), batteries, chemical captors, optical devices. In addition, the Forum will provide several tutorials on selected hot topics before the technical sessions and several hands-on tutorials in parallel with technical sessions. These will allow attendees to try EDA tools with the help of instructors from EDA companies. Finally, the Forum will also host several working groups meetings of the IEEE Design Automation Standards Committee (DASC). These meetings are open to everybody interested. TOPICS OF INTEREST Authors are invited to submit original technical contributions describing methods, tools, and design practices... see: http://www.ecsi.org/ecsi/fdl for the list of topics PRE-FORUM TUTORIALS Proposals for half-day tutorials are invited. Proposals will be selected on the evidence that they can transfer in 5 hours a comprehensive knowledge of the topics of interest they are addressing. PANEL SESSIONS Proposals for panels should clearly state the topic, a title, the composition of panel members and, if available, the name of the panelists, their affiliations and domain of expertise. The panels will last no more than one hour and 30 minutes and involve an average of 4 panelists and a moderator. HANDS-ON-LABS AND WORKING GROUP MEETINGS Hands-on-labs from EDA tool providers (commercial and academic) are invited to be given on Unix or PC workstations, in parallel with technical sessions. A title and a summary of the lab contents are required. Working group meetings are welcome, in conjunction with the event or on Saturday Sept. 4. Applications should be directed to the FDL Organization Co-Chair as soon as possible to facilitate room allocation. REQUIREMENTS FOR SUBMISSION OF CONTRIBUTIONS Each submission should include a cover page and the proposed contribution. The cover page should include the complete coordinates of each author, and the name of the presenter if the contribution is accepted. The contribution should include 1- the name of the workshop (HDL & VUFE, VCDR, SSDL) and a list of topics that most closely match its con-tent, 2- a title, and 3- either an extended abstract of approximately 1000-2000 words (abstracts not in this format will be rejected), or a full paper not exceeding 10 pages in 12pt, one column format. Contributions must include descriptions of key ideas, results, contributions, limitations, experimental condi-tions (if applicable), and appropriate references to other related works. Some outstanding late contributions can be submitted until July 2. Late contributions will not exceed 20% of all accepted contributions. Accepted authors are NOT required to prepare a full-length final paper. Slide handouts are accepted as final versions for contributions that have been submitted as an extended abstract. Abstract-only final versions are also accepted for confidential presentations that are subject to non-disclosure constraints. Accepted contribu-tions will be bound and distributed at the Forum. The best accepted papers will be candidate to be published in an edited book (publisher yet to be announced). FORM OF SUBMISSIONS Interested authors are invited to send the re-quested information in electronic format to both Jean Mermet, FDL General Chair and Ralf Seepold, FDL Program Chair Preferred electronic formats are in this order: PDF, RTF, Postscript, Compressed submissions with GNU gzip, Unix compress, PKZip are also accepted. ______________________________________________________________________ IMPORTANT DATES IN 1999 Paper or abstract contributions due March 26 Panel session & tutorial proposals May 7 Notification of acceptance June 4 Final paper contributions due July 2 Late contributions July 2 FDL'99 Aug 30-Sept. 3 Half-day tutorials August 30 HDL & VUFE Aug. 31-Sept. 1 VCDR September 1-2 SSDL September 2-3 ______________________________________________________________________ CONTACT POINTS FDL GENERAL CHAIR Dr. Jean Mermet Laboratoire TIMA ECSI, Parc Equation France jean.mermet@imag.fr FDL ORGANIZATION CO-CHAIR Dr. Anne Mignotte Ecole Normale Supérieure de Lyon France anne.mignotte@ens-lyon.fr FDL PROGRAM CHAIR Dr. Ralf Seepold FZI Karlsruhe Germany seepold@fzi.de HDL & VUFE CHAIR Prof. Donatella Sciuto Politecnico di Milano Italy sciuto@elet.polimi.it VCDR CHAIR Dr. Ralf Seepold SSDL CHAIR Prof. Eugenio Villar Univ. of Cantabria Spain villar@teisa.unican.es TUTORIAL CHAIR Prof. Wolfgang Rosenstiel Universitaet Tuebingen Germany rrosenstiel@informatik.uni-tuebingen.de ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ I * * S European CAD Standardization Initiative * C* Parc Equation, 2 Av. de Vignate, F-38610 GIERES, France * E * Tel. +33 476 63 49 34, Fax. +33 476 42 87 87 * * Email: office@ecsi.alpes-net.fr * * Home Page: http://www.ecsi.org * * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ From pilz@ifi.unizh.ch Sat Dec 19 18:32:33 1998 +0100 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <23899-0@josef.ifi.unizh.ch>; Sat, 19 Dec 1998 18:32:18 +0100 Return-Path: X-Received: from pol88b.polito.it by josef.ifi.unizh.ch with SMTP (PP) id <07884-0@josef.ifi.unizh.ch>; Wed, 16 Dec 1998 21:06:50 +0100 X-Received: from chiusella.polito.it.polito.it (chiusella.polito.it) by polito.it (PMDF V4.2-15 #3020) id <01J5F2NV6DK08WXK0B@polito.it>; Wed, 16 Dec 1998 20:25:30 GMT+1 X-Received: by chiusella.polito.it.polito.it (4.1/SMI-4.1) id AA21936; Wed, 16 Dec 98 20:34:33 +0100 Date: Wed, 16 Dec 1998 20:34:33 +0100 From: tttc@chiusella.polito.it (Paolo Prinetto) Subject: IEEE TTTC - P1500 : new task force To: pilz@ifi.unizh.ch Message-id: <9812161934.AA21936@chiusella.polito.it.polito.it> X-Envelope-to: pilz@ifi.unizh.ch Content-transfer-encoding: 7BIT Apparently-To: PILZ Markus ReSent-Date: Sat, 19 Dec 1998 18:32:13 +0100 (MET) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: IEEE TTTC - P1500 : new task force ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 63 CALL for VOLUNTEERS Task Force on: "Mergeable Core Test Requirements" IEEE P1500 Working Group TTTC Standards +++++++++++++++++++++++++++++++++++++++++++++++++++ The IEEE P1500 Working Group focuses on facilitating test reuse for embedded cores. During the last Working Group meeting during ITC '98 (10/18-19/98) an issue concerning the test requirements for "merged" cores was raised in a presentation entitled "Lucent's Perspective on SOC Testing". The presentation emphasized the growing importance of soft and firm cores, which are typically merged with their surrounding logic. It was felt that these cores present similar test problems as "non-merged" cores. Merging soft/firm cores from the test perspective may not be always desireable and may call for a standard test interface as in the case of "non-merged" cores. The P1500 Working Group agreed to further investigate the above issue and the following action was initiated: A new Task Force entitled "Mergeable Core Test Requirements" was formed. The primary objective of this Task Force is to investigate and identify the test requirements of merged cores (soft and firm) and to verify whether the currently investigated solutions by the P1500 WG can address these requirements. Members from system oriented companies are invited to join this Task Force and help specify the standardization requirements. To join the Task Force, please send email to Sudipta Bhawmik (bhawmik@lucent.com). For more information on IEEE P1500 check: http://grouper.ieee.org/groups/1500 or contact the Working Group Chair: Yervant Zorian (zorian@logicvision.com) %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % IEEE Computer Society % Test Technology Technical Council % Electronic Broadcasting Service % % % This message contains public information, only. % You are invited to copy and distribute it further. % % For more information contact % or visit http://www.computer.org/tttc/ % % If you would like to be removed from this mailing list, % please send an e-mail to % % % Paolo PRINETTO % Test Technology Technical Council (Vice Chair) % % Politecnico di Torino % Dip. di Automatica e Informatica % Corso Duca degli Abruzzi 24 % I-10129 Torino TO % Italy % % Tel: +39 011 564.7007 % Fax: +39 011 564.7099 % % E-mail: Paolo.Prinetto@polito.it % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% From pilz@ifi.unizh.ch Sat Dec 19 19:04:05 1998 +0100 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <23884-0@josef.ifi.unizh.ch>; Sat, 19 Dec 1998 18:32:05 +0100 Return-Path: X-Received: from pol88b.polito.it by josef.ifi.unizh.ch with SMTP (PP) id <18749-0@josef.ifi.unizh.ch>; Thu, 17 Dec 1998 08:56:10 +0100 X-Received: from chiusella.polito.it.polito.it (chiusella.polito.it) by polito.it (PMDF V4.2-15 #3020) id <01J5FRHUT0Z48WZZ1G@polito.it>; Thu, 17 Dec 1998 08:16:52 GMT+1 X-Received: by chiusella.polito.it.polito.it (4.1/SMI-4.1) id AA29253; Thu, 17 Dec 98 08:26:07 +0100 Date: Thu, 17 Dec 1998 08:26:07 +0100 From: tttc@chiusella.polito.it (Paolo Prinetto) Subject: IEEE TTTC - Home page URL's To: pilz@ifi.unizh.ch Message-id: <9812170726.AA29253@chiusella.polito.it.polito.it> X-Envelope-to: pilz@ifi.unizh.ch Content-transfer-encoding: 7BIT Apparently-To: PILZ Markus ReSent-Date: Sat, 19 Dec 1998 18:32:00 +0100 (MET) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Subject: IEEE TTTC - Home page URL's ReSent-Message-ID: Status: RO X-Status: X-Keywords: X-UID: 64 Dear TTTC member, As you know, TTTC has a web site with a list of home page URL's of its members: http://www2.san-jose.ate.slb.com:65080/tttc/ The purpose of this email is to strongly encourage every one to submit your home page URL to this site. We are all busy, but this will not take more than a couple of minutes. This home page repository is very useful: for example, a student looking for material in a certain area can quickly find the experts that work in that area, and easily get in contact with them, or just download papers from their home pages. And this is just one example... But most of you have not done it as yet. So please send email to west@ieee.org, subject "tttc home page directory", containing exactly these three items: -- your personal home page URL -- your name and affiliation -- your general areas of technical interest Thanks for your support of this neat idea. Miron Dr. Miron Abramovici Bell Labs - Lucent Technologies 600 Mountain Ave Rm. 2C-225 Murray Hill, NJ 07974-0636 +1 908 582-3933 fax: +1 908 582-4092 miron@research.bell-labs.com http://www.bell-labs.com/user/miron/ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % IEEE Computer Society % Test Technology Technical Council % Electronic Broadcasting Service % % % This message contains public information, only. % You are invited to copy and distribute it further. % % For more information contact % or visit http://www.computer.org/tttc/ % % If you would like to be removed from this mailing list, % please send an e-mail to % % % Paolo PRINETTO % Test Technology Technical Council (Vice Chair) % % Politecnico di Torino % Dip. di Automatica e Informatica % Corso Duca degli Abruzzi 24 % I-10129 Torino TO % Italy % % Tel: + 39 011 564.7007 % Fax: + 39 011 564.7099 % % E-mail: Paolo.Prinetto@polito.it % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% From pilz@ifi.unizh.ch Mon Dec 21 20:51:20 1998 +0100 Status: R X-Status: X-Keywords: Return-Path: Received: from rzcomm1.rz.tu-bs.de by josef.ifi.unizh.ch with SMTP (PP) id <02669-0@josef.ifi.unizh.ch>; Mon, 21 Dec 1998 20:51:16 +0100 Received: from ida.ing.tu-bs.de (willy.ida.ing.tu-bs.de [134.169.132.54]) by rzcomm1.rz.tu-bs.de (8.8.6/8.8.6) with ESMTP id UAA12493; Mon, 21 Dec 1998 20:49:26 +0100 (MET) Message-ID: <367EA607.1EBA782@ida.ing.tu-bs.de> Date: Mon, 21 Dec 1998 20:48:23 +0100 From: "Prof. Rolf Ernst" X-Mailer: Mozilla 4.5 [en] (Win98; I) X-Accept-Language: en MIME-Version: 1.0 To: ISSS , Codesign Subject: DATE 99 Conference and Exhibition Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit ________________________________________________________________________ DATE99 Design, Automation and Test in Europe Conference and Exhibition Munich, Germany, March 9-12, 99 http://www.date-conference.com ________________________________________________________________________ DATE99 is the single unified European event bringing together researchers, users and vendors in the field of electronic systems design engineering. It is the successor of the very successful DATE98 which attracted close to 4.000 participants from industry and academia. DATE99 consists of a conference with tutorials and a commercial EDA tool exhibition. The conference addresses all aspects of research into technologies for electronic systems engineering. It covers the design process, test, and tools for design automation of electronic products ranging from integrated circuits to distributed large-scale systems. The presentations are arranged in 4 tracks covering high-level design, formal methods and verification, low power design, analog circuit design, physical design and test. The paper sessions are complemented by special sessions on hot topics, panel sessions on controversial developments in the field as well as educational embedded tutorials. The keynote session focuses on system design & test issues including top ranking speakers from BMW, Nokia and Synopsys. A user's forum focuses on design experience and industrial methodologies. Last but not least, DATE99 has organized a PCB symposium which already attracted a large audience at DATE98, when it still was run as a fringe event. Six half day tutorials presented by world-wide leaders in the respective fields give the unique opportunity for a quick start or an update in important technical areas. The exhibition includes all major EDA vendors of the world. Already a major success last year, this year's exhibition shows an increase by 20% in booking both in space and in the number of exhibitors. The observed growth is almost solely due to bookings of a larger number of European and US startup companies offering novel tools and solutions. It is an expression of the increasing dynamics of the EDA market and of the importance of DATE99 as a platform for this development. This fact alone makes the DATE 99 visit a must for the European professional in the field. Additional space for demo suites positioned in close vicinity to the exhibition give the opportunity for in-depth discussions in a confidential environment. Hands-on tutorials allow for on-site tool evaluations. A long list of fringe and on-site meetings is yet another indication of the DATE99 importance. The second week in March 99, Munich will be the center of the EDA world. All this will happen in the superb new facilities of the Munich ICM which offers an ideal environment for this event. For detailed information see http://www.date-conference.com From pilz@ifi.unizh.ch Thu Dec 24 07:20:08 1998 +0100 Status: R X-Status: X-Keywords: Return-Path: Received: from ccs1.iis.sinica.edu.tw by josef.ifi.unizh.ch with SMTP (PP) id <15820-0@josef.ifi.unizh.ch>; Thu, 24 Dec 1998 07:20:03 +0100 Received: (eric@localhost) by ccs1.iis.sinica.edu.tw (8.8.8/8.7.5) id OAA18534 for codesign@ifi.unizh.ch; Thu, 24 Dec 1998 14:19:17 +0800 (CST) Date: Thu, 24 Dec 1998 14:19:17 +0800 (CST) From: eric@iis.sinica.edu.tw (Pao-Ann Hsiung) Message-Id: <199812240619.OAA18534@ccs1.iis.sinica.edu.tw> To: codesign@ifi.unizh.ch Subject: CFP: Codesign of Parallel and Distributed Systems ********************************************************************* C A L L F O R P A P E R S ============================= SPECIAL SESSION on ```````````````````````````````````````````````````````````````` "HARDWARE-SOFTWARE CODESIGN OF PARALLEL AND DISTRIBUTED SYSTEMS" ```````````````````````````````````````````````````````````````` "http://www.iis.sinica.edu.tw/~eric/pdpta99-codesign/" The 1999 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'99) June 28 - July 1, 1999 Monte Carlo Resort, Las Vegas, Nevada, USA A special session on the HARDWARE-SOFTWARE CODESIGN of parallel and distributed systems is begin organized at PDPTA'99, which will be held in Las Vegas, Nevada, June 28 - July 1, 1999. Architectures supporting parallel and distributed computing include both hardware and software. The success of such architectures depends significantly on how the hardware and software interact. This in turn requires careful codesign approaches which include co-partitioning, scheduling, co-synthesis, co-simulation, and co-verification. Due to their complex behavior and structural restrictions, parallel and distributed systems present a greater challenge to codesign methodologies than conventional systems. Object-oriented modeling/design, formal specification/verification methods, graph-theoretic analysis, virtual prototyping, functional/structural partitioning are some promising techniques which can be employed for hardware-software codesign. Parallel and distributed processing is the computing trend and hardware-software codesign is the technique for supporting this trend. SESSION SCOPE: All hardware-software codesign related topics that deal with parallel and distributed systems are invited. Topics of interest include, but are not limited to, the following: * Specification/Modeling, * Object-Oriented Technology * Co-design Methodologies, * Virtual Components * Co-partitioning, * Software Synthesis * Co-simulation Strategies, * Hardware Synthesis * Co-verification Techniques * Embedded/Real-Time Systems SUBMISSION OF PAPERS: To submit a paper to the special session, please do the following: (1) Prepare a manuscript in PostScript/Microsoft Word-7.0 format of maximum 7 pages: single-spaced, single-column, US-Letter/A4 size, with title, authors, affiliations, e-mail addresses, and a 100-word abstract on the first page. (2) Send an ascii-text e-mail with the paper title and the corresponding author's name, mailing address, e-mail address, and telephone/fax numbers. (3) E-mail the above two to: "eric@iis.sinica.edu.tw". If electronic submission is not possible, please mail the above to the following address: Dr. Hsiung, Pao-Ann (Mailbox A-38) Institute of Information Science Academia Sinica No. 128, Sec. 2, Academic Road Nankang, Taipei 115, Taiwan, R.O.C. (4) Important Dates: Submission Deadline: March 1, 1999 Paper Notification: April 1, 1999 Camera-Ready papers: May 1, 1999 Pre-Registration: May 1, 1999 PDPTA'99 Conference: June 28-July 1, 1999 (5) A minimum of six (6) papers will be selected for the session. All submissions will be reviewed by at least 2 referees. Papers must not have been previously published or currently submitted for publication elsewhere. Pre-registration at the conference is a must for all accepted papers to be published in the proceedings. All accepted papers must be presented at PDPTA'99, Las Vegas, USA. PUBLICATION: The conference proceedings will be published by CSREA Press (ISBN). It will be a multivolume set. The proceedings will be available at the conference. All accepted papers will also be considered for journal publication (soon after the conference). ORGANIZERS/SPONSORS: A number of university faculty members and their staff in cooperation with the Monte Carlo Resort (Conference Division, Las Vegas ), will be organizing the conference. The conference is sponsored by the Computer Science Research, Education, and Applications Press (CSREA: USA Federal EIN # 58-2171953) in cooperation with the National Supercomputing Center for Energy and the Environment (Department of Energy, USA), The International Association for Mathematics and Computers in Simulation (IMACS), The International Technology Institute (ITI), The Java High Performance Computing research group (JHPC; www.jhpc.org), the Computer Vision Research and Applications Tech. (CVRA), developers of high-performance machines and systems (pending) and other related computer associations (pending.) LOCATION OF CONFERENCE: The conference will be held in the Monte Carlo Resort hotel, Las Vegas, Nevada, USA. This is a mega hotel with excellent conference facilities and over 3000 rooms. The hotel is minutes from the Las Vegas airport with free shuttles to and from the airport. This hotel has many vacation and recreational attractions, including: waterfalls, casino, spa, pools & kiddie pools, sunning decks, Easy River water ride, wave pool with cascades, lighted tennis courts, health spa (with workout equipment, whirlpool, sauna, ...), arcade virtual reality game rooms, nightly shows, snack bars, a number of restaurants, shopping area, bars, ... Many of these attractions are open 24 hours a day and most are suitable for families and children. The negotiated hotel's room rate for conference attendees is very reasonable ($79 + tax) per night (no extra charge for double occupancy) for the duration of the conference. The hotel is within walking distance from most other Las Vegas attractions (major shopping areas, recreational destinations, fine dining and night clubs, free street shows, ...). For the benefit of our international colleagues: the state of Nevada neighbors with the states of California, Oregon, Idaho, Utah, and Arizona. Las Vegas is only a few driving hours away from other major cities, including: Los Angeles, San Diego, Phoenix, Grand Canyon, ... EXHIBITION: An exhibition is planned for the duration of the conference. We have reserved 20+ exhibit spaces. Interested parties should contact H. R. Arabnia (address is given below). All exhibitors will be considered to be the co-sponsors of the conference. Each exhibitor will have the opportunity to include a two-page description of their latest products in the conference proceedings (if submitted by May 1, 1999). MEMBERS OF PROGRAM & ORGANIZING COMMITTEES: The Program Committee is currently being formed. Those interested in joining the Program Committee should email H. R. Arabnia (hra@cs.uga.edu) the following information: Name, affiliation and position, complete mailing address, email address, tel/fax numbers, a short biography together with research interests. SESSION CHAIR/ORGANIZER: Address: Dr. Pao-Ann Hsiung Institute of Information Science Academia Sinica No. 128, Sec. 2, Academic Road Nankang, Taipei 115, TAIWAN, R.O.C. E-mail: eric@iis.sinica.edu.tw Tel. : +886-2-27883799 Fax : +886-2-27824814 URL : http://www.iis.sinica.edu.tw/~eric/pdpta99-codesign/ CONFERENCE CONTACT: Hamid R. Arabnia The University of Georgia Department of Computer Science 415 Graduate Studies Research Center Athens, Georgia 30602-7404, U.S.A. Tel: (706) 542-3480 Fax: (706) 542-2966 E-mail: hra@cs.uga.edu (A link for pdpta99 will soon be created at http://www.jhpc.org/pdpta, http://www.cps.udayton.edu/~pan/pdpta, and http://fukuda.aist-nara.ac.jp/pdpta99.)