From codesign-request@ifi.unizh.ch Tue Jan 7 18:07:34 1997 Return-Path: Received: from pophost.cs.tamu.edu by josef.ifi.unizh.ch with SMTP (PP) id <28204-0@josef.ifi.unizh.ch>; Tue, 7 Jan 1997 17:45:50 +0100 Received: from chipmonks.cs.tamu.edu (233@chipmonks.cs.tamu.edu [128.194.146.168]) by cs.tamu.edu (8.8.4/8.8.4) with ESMTP id KAA17393 for ; Tue, 7 Jan 1997 10:44:44 -0600 (CST) From: Fabrizio Lombardi Subject: CFP: 1997 IEEE INT. WORKSHOP ON MEMORY TECHNOLOGY, DESIGN AND TESTING Received: (from lombardi@localhost) by chipmonks.cs.tamu.edu (8.8.4/8.8.4) id KAA02585 for codesign@ifi.unizh.ch; Tue, 7 Jan 1997 10:43:56 -0600 (CST) Date: Tue, 7 Jan 1997 10:43:56 -0600 (CST) Message-Id: <199701071643.KAA02585@chipmonks.cs.tamu.edu> To: codesign@ifi.unizh.ch Status: RO X-Status: CALL FOR PAPERS AND PARTICIPATION 1997 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN AND TESTING August 11-12, 1997 Submission deadline: January 15, 1997 Send submissions to: TECHNICAL PROGRAM CHAIR Thomas Wik LSI Logic, MS E-194 1501 McCarthy Blvd Milpitas CA 95035, USA 408/954--4471; trw@lsil.com Address general inquiries to: GENERAL CHAIR Fabrizio Lombardi Computer Science MS 3112 Texas A&M University College Station TX 77843, USA 409/845--5464; fax 847--8578 lombardi@cs.tamu.edu The 1997 IEEE International Workshop on Memory Technology, Design and Testing will be held at the Hilton Hotel and Towers, 300 Almaden Blvd, San Jose, California, USA (408/287--2100), on August 11-12, 1997. The workshop will include all aspects of memory design, process technologies and testability related topics. Memory circuit designs, cell structures, fabrication processes, design architectures as related to testing, verification and test methods for SRAM, DRAM, Flash and Non-Volatile memories, EPROM, EEPROM, embedded memories, logic-enhanced and FIFO memories, 3-D memories and content addressable memories. Some representative topics are: - Memory fault modeling and test generation - Built-in test and testable designs for memories - Concurrent checking and memory fault diagnosis - Quality and reliability issues - Space applications and radiation hardening issues - Memory failure and yield analysis - High-speed, innovative designs - Fault isolation, reconfiguration and repair - Multiported, multibuffered memories - Logic-enhanced and programmable memories - Application-specific and embedded memories - Multimegabit SRAMs and DRAMs - CMOS, BiCMOS and bipolar designs for high yield and reliability Authors please submit five (5) copies of an extended abstract of about 1000 words of original work on any aspect of memory technology, design and testing to the Technical Program Chair. Submissions should include full names and affiliations of authors, contact information and should indicate the intended presenter. Submissions are due January 15, 1997. Authors will be notified of acceptance on March 31, 1997. Final papers will be due May 15, 1997. Presentations will be 30 minutes, inclusive of discussion. Sponsored by: IEEE Computer Society Technical Committee on Test Technology Technical Committee on VLSI In cooperation with: IEEE Solid-State Circuit Council/Society PUBLICITY CHAIR Fred "Jackie" Meyer Computer Science MS 3112 Texas A&M University College Station TX 77843, USA 409/845--1014; fmeyer@cs.tamu.edu FINANCE CHAIR Duncan "Hank" Walker Computer Science MS 3112 Texas A&M University College Station TX 77843, USA 409/862--4387; fax 847--8578 walker@cs.tamu.edu STEERING COMMITTEE Rochit Rajsuman, Chair LSI Logic, MS E-171 1501 McCarthy Blvd Milpitas CA 95035, USA 408/433--8789; rajsuman@lsil.com Bernard Courtois INPG/TIMA Grenoble, France Ad J. van de Goor Delft University of Technology Delft, The Netherlands Yervant Zorian Lucent Technologies Princeton NJ, USA PROGRAM COMMITTEE Abhaya Asthana Lucent Technologies Princeton NJ, USA Bruce Cockburn University of Alberta Edmonton AB, Canada Mike DePaolis Lucent Technologies Princeton NJ, USA Bob Evans MosAid San Jose CA, USA E. Fujiwara Tokyo Institute of Technology Tokyo, Japan Susanne Griep Siemens AG Munchen, Germany S. Horiguchi Japan Advanced Institute of Science and Technology Tatsunokuchi, Japan Swee Yong Khim Texas Instruments Singapore David Lepejian HPL Milpitas CA, USA Yashwant Malaiya Colorado State University, USA P. Olivo University of Bologna Bologna, Italy Ritu Shrivastava Alliance Semiconductor San Jose CA, USA From codesign-request@ifi.unizh.ch Tue Jan 14 20:00:57 1997 Return-Path: Received: from hudson.wash.inmet.com by josef.ifi.unizh.ch with SMTP (PP) id <08409-0@josef.ifi.unizh.ch>; Tue, 14 Jan 1997 20:00:31 +0100 Received: (from dlb@localhost) by hudson.wash.inmet.com (8.7.6/8.7.3) id NAA00545; Tue, 14 Jan 1997 13:59:33 -0500 Date: Tue, 14 Jan 1997 13:59:33 -0500 Message-Id: <199701141859.NAA00545@hudson.wash.inmet.com> From: David Barton To: codesign@ifi.unizh.ch Subject: Systems Level Design Language Workshop Status: RO X-Status: CALL FOR PARTICIPATION First Workshop on Systems Design Languages April 7th and 8th, 1997 San Jose, CA Sponsoring organizations: Special Interest Group on Systems Design Languages of the Design Automation Technical Committee (SIGSDL of DTAC) Working Group on Systems Evaluation of IEEE Technical Committee on Engineering of Computer-Based Systems Your participatating in the First Workshop on Systems Design Languages is eagerly invited. The two day workshop will be on April 7th and 8th in San Jose, California (exact site to be announced). The purpose of the workshop is to: (i) determine the state of the art in systems description and systems evaluation; and (ii) explore the direction of future research. For the purposes of this effort, a system can include digital hardware, analog hardware, software, and mechanical components. All descriptions of current work are welcome, including existing systems design languages, work on future design languages, formal semantics, working systems description systems, and any other related subjects. Prospective participants are requested to submit a one or two paragraph abstract of their presentation to David Barton (dlb@wash.inmet.com) or Perry Alexander (alex@ece.uc.edu). The format will be informal, stressing exchange between the participants and attendees. Presentations by slides for overhead projectors is preferred. Immediately following the workshop on April 9th and 10th will be a meeting of the Systems Level Description Committee (SLDL) of the Program Technical Advisory Board (PTAB) of the EDA Industry Council. Those interested in this organization are encouraged to contact the chair, David Barton, at the Email address above. This meeting will be limited to active members of the committee. Dave Barton <*> dlb@wash.inmet.com )0( http://www.intermetrics.com/~dlb From codesign-request@ifi.unizh.ch Thu Jan 23 09:25:34 1997 Return-Path: Received: from bikini.ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <03448-0@josef.ifi.unizh.ch>; Thu, 23 Jan 1997 09:25:20 +0100 Return-Path: X-Received: from epsilon.ece.nwu.edu by josef.ifi.unizh.ch with SMTP (PP) id <15520-0@josef.ifi.unizh.ch>; Thu, 23 Jan 1997 00:44:01 +0100 X-Received: (from daemon@localhost) by epsilon.ece.nwu.edu (8.8.5/8.8.3) id NAA18759 for ; Wed, 22 Jan 1997 13:11:44 -0600 (CST) X-Received: from seattle.ece.nwu.edu(129.105.5.174) by epsilon.ece.nwu.edu via smap (V2.0beta) id xma018755; Wed, 22 Jan 97 13:11:39 -0600 X-Received: (from daemon@localhost) by seattle.ece.nwu.edu (8.8.3/8.8.3) id NAA24331 for ; Wed, 22 Jan 1997 13:11:39 -0600 (CST) X-Received: from ee.princeton.edu(128.112.48.182) by seattle.ece.nwu.edu via smap (V2.0beta) id xma024324; Wed, 22 Jan 97 13:11:14 -0600 X-Received: from new-delhi (sharad@new-delhi.Princeton.EDU [128.112.48.45]) by ee.Princeton.EDU (8.6.10/8.6.10-1) with ESMTP id OAA18602 for ; Wed, 22 Jan 1997 14:11:13 -0500 From: Sharad Malik X-Received: by new-delhi (8.6.10/viktor-1) id OAA24459; Wed, 22 Jan 1997 14:11:11 -0500 Date: Wed, 22 Jan 1997 14:11:11 -0500 Message-Id: <199701221911.OAA24459@new-delhi> To: fpga97@seattle.ece.nwu.edu Subject: Int. Workshop on Logic Synthesis: CFP ReSent-Date: Thu, 23 Jan 1997 09:25:06 +0100 (MET) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Message-ID: Status: RO X-Status: 1997 IEEE/ACM International Workshop on Logic Synthesis http://www.ee.princeton.edu/iwls97.html Granlibakken Resort, Lake Tahoe, California May 18-21 , 1997 Call for Participation Contents 1. Synopsis 2. Benchmarks 3. About IWLS 4. About Granlibakken 5. Executive Committee 6. Technical Program Committee 7. Sponsored by... Synopsis Logic Synthesis has traditionally focused on optimization techniques for combinational and sequential circuits through the manipulation of Boolean equations and state machines. IWLS '97, the sixth workshop in this series, seeks presentations both on these topics and on new directions in synthesis-based design methodology. Topics of interest include: Area, timing, power optimization Logic synthesis systems CMOS, ECL, GaAS Optimization Designer Experiences with Synthesis Two-level Logic Optimization Interaction with physical design Multi-level Logic Optimization Incremental Synthesis/ECO Support FSM Optimization Asynchronous Logic Synthesis Sequential Circuit Optimization Formal Verification Retiming and resynthesis Optimization at the RTL Level Technology Mapping Timing Verification FPGA and PLD Synthesis Testing and Synthesis for test Don't-Cares and Boolean Relations Interaction with module generators Symbolic Synthesis Use of synthesis in new applications Synthesis in FPGA-Based Emulation Applications of SAT Authors may submit extended abstracts for their proposed presentation. These must be no less than 1000 words and no more than 2500 words. These abstracts are not intended to be complete papers, but rather should convey the main ideas of the proposed presentation. We encourage submissions in the early stages of research which may highlight important new problems without necessarily providing complete solutions. The abstracts may be submitted by e-mailing self-contained Postscript files to iwls-submit@ee.princeton.edu by February 15, 1997. Acceptance notices will be sent by March 31, 1997. A set of workshop notes will be distributed at the conference. There will be no published proceedings. Benchmarks A benchmark set is being assembled by the CAD Benchmarking Laboratory. To contribute new benchmarks, or to obtain information about the existing suite, please write: benchmarks@cbl.ncsu.edu. About IWLS IWLS '93 and IWLS '95 introduced a number of format changes from previous workshops, which the committee tentatively intends to maintain for IWLS '97. These include an open program with high acceptance rate, heavy use of posters and short talks for presentation, and large amounts of time in the schedule for poster presentations. In addition, IWLS '97 will emphasize open discussions and ongoing research which are not provided by the traditional conference format. About Granlibakken The Granlibakken Conference Center is located in Tahoe City on the west shore of Lake Tahoe, 180 miles east of San Francisco. It boasts 160 rooms, clustered into two- and three-bedroom condominiums. Each bedroom is an attractive hotel room with private bath. Many of the clusters share a kitchen, living room and dining room -- a miniature lobby for private meetings. Organizations sending several people to the workshop may wish to rent entire two- and three-bedroom townhouses. The Granlibakken management has reserved space on Thursday, May 22 for organizations who wish to hold private, one-day workshops immediately preceding IWLS, and have agreed to charge organizations the IWLS conference rate for these meetings. Contact Mary Brown at Granlibakken sales (1-800-552-4494) for details. Granlibakken is within 10 minutes' drive of the West's premier ski resorts: Alpine Meadows and Squaw Valley USA. When California enjoys high snowfall, both areas remain open until Memorial Day. A wealth of hiking trails snake through the area. Weather permitting, Granlibakken's tennis courts and pool will be open for use. The weather in late May is variable; warm, sunny days and cool clear nights are the rule. Getting There Granlibakken is easily reached from either the San Francisco Bay Area or Reno, NV. Take Interstate 80 to Truckee. From there, follow State Route 89 south to Tahoe City. Turn right at the stop light in Tahoe City. After 1/4 mile, turn right on Granlibakken road and proceed to the end. Contacts/Executive Committee General Chair Rick Cadence mcgeer@cadence.com (408) McGeer Berkeley Labs 428-5325 Tech. Program Sharad Princeton (609) Chair Malik University sharad@ee.princeton.edu 258-4625 Benchmark Franc (919) Chair Brglez NCSU brglez@cbl.ncsu.edu 248-1925 Conference Kris Cadence (408) Coordinator Lamanno Berkeley Labs krisl@cadence.com 894-2479 Technical Program Committee Pranav Ashar NEC Michel Berkelaar TU-Eindhoven Robert K. Brayton UC Berkeley Franc Brglez NCSU Giovanni de Micheli Stanford Srinivas Devadas MIT Ewald Detjens Mentor Graphics Antun Domic Cadence Masahiro Fujita Fujitsu Laboratories of America Wolfgang Kunz University of Potsdam Luciano Lavagno Politecnico di Torino/Cadence Berkeley Labs Ken McElvain Synplicity Rick McGeer Cadence Berkeley Labs Sharad Malik (chair) Princeton University Shin-ichi Minato NTT Massoud Pedram USC Richard Rudell Synopsys Tsutomu Sasao Kysushu Institute of Technology Gabriele Saucier INPG Ellen Sentovich Cadence Berkeley Labs Fabio Somenzi University of Colorado Leon Stok IBM TJ Watson Research Center Sponsor Sponsored by the IEEE Computer Society, Technical Committee on VLSI. In co-operation sponsoship by ACM/SIGDA is being sought. From codesign-request@ifi.unizh.ch Mon Jan 27 09:35:36 1997 Return-Path: Received: from bikini.ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <08158-0@josef.ifi.unizh.ch>; Mon, 27 Jan 1997 09:35:21 +0100 Return-Path: X-Received: from 130.251.51.22 by josef.ifi.unizh.ch with SMTP (PP) id <23322-0@josef.ifi.unizh.ch>; Fri, 24 Jan 1997 20:28:14 +0100 X-Received: from phoenix (phoenix [130.251.51.35]) by hermes.dibe.unige.it (8.6.12/8.6.9) with SMTP id OAA00914; Fri, 24 Jan 1997 14:35:40 GMT Message-ID: <32E8BD0C.11B2@dibe.unige.it> Date: Fri, 24 Jan 1997 14:45:48 +0100 From: Alessandro De Gloria Reply-To: adg@dibe.unige.it Organization: university of genova - dibe X-Mailer: Mozilla 3.01 (WinNT; I) MIME-Version: 1.0 To: codesign reflector Subject: Call For Paper Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit ReSent-Date: Mon, 27 Jan 1997 09:34:17 +0100 (MET) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Message-ID: Status: RO X-Status: Journal of System Architecture Special Issue on Microprocessor Architecture This special issue of the Journal will present research and industrial trends in the field of microprocessor design. Papers are invited on any aspects of Microprocessor Architecture. Topic areas include: Novel architecture and computing techniques Application and technology impact on microprocessor architecture Architectural implication of application characteristics Microprocessor Architecture for embedded system Performance Evaluation and Measurements Superscalar, superpipelined and VLIW microprocessor Low Power Architecture Design Architecture Design Techniques Re-configurable Architectures Non-numeric microprocessors Language and Operating System Support System Design of Computer Systems Submitting of Papers Prospective authors should send their full paper either by electronic mail or five copies by postal mail to the guest editor. The following statement should be included in the submission: "All necessary clearances have been obtained for the publication of this paper. If accepted, the author(s) will prepare the final electronic submission by the stated deadline". The closing date for submissions is 15th June 1997. Authors will be notified of acceptance by 15 September 1997. The approximate publication date will be February 1998. Reply to: Guest Editor : Dr. Alessandro De Gloria University of Genoa - DIBE Via Opera Pia 11 16145 Genova - Italy Tel & Fax +39-10-3532785 e-mail: adg@dibe.unige.it From codesign-request@ifi.unizh.ch Fri Jan 31 08:38:03 1997 Return-Path: Received: from june.cs.washington.edu by josef.ifi.unizh.ch with SMTP (PP) id <12457-0@josef.ifi.unizh.ch>; Fri, 31 Jan 1997 08:37:44 +0100 Return-Path: Received: (gaetano@localhost) by june.cs.washington.edu (8.8.5+CS/7.2ju) id XAA15601; Thu, 30 Jan 1997 23:36:31 -0800 Date: Thu, 30 Jan 1997 23:36:31 -0800 From: gaetano@cs.washington.edu (Gaetano Borriello) Message-Id: <199701310736.XAA15601@june.cs.washington.edu> To: ahmed.jerraya@imag.fr, alberto@ic.EECS.Berkeley.EDU, brian_bailey@mentorg.com, codesign@ifi.unizh.ch, codesign@vhdl.org, ernst@ida.ing.tu-bs.de, fuhrman@gmr.com, gaetano@cs.washington.edu, gajski@uci.edu, gdp@el.wpafb.af.mil, hartenst@rhrk.uni-kl.de, isss-people@ics.uci.edu, jbuck@synopsys.com, jst@it.dtu.dk, keutzer@synopsys.com, koopman@cs.cmu.edu, mde@ap.co.umist.ac.uk, nanni@pegasus.stanford.edu, raul@synopsys.com, rgupta@gupta.ICS.UCI.EDU, roger@ahl.co.uk, rosenstiel@peanuts.informatik.uni-tuebingen.de, rwt@hpl.hp.co.uk, sciuto@elet.polimi.it, skumar@src.honeywell.com, thomas@ece.cmu.edu, vahid@cs.ucr.edu, wolf@princeton.edu, yasuura@is.kyushu-u.ac.jp Subject: CODES/CASHE'97 Advance Program/Reg Form/Hotel Info Status: RO X-Status: The 1997 Codes/CASHE'97 Workshop will be held in Braunschweig, Germany on 24-26 March 1997. The advance program, registration information and form, and accomodations details are attached. This information as well as much more is available at the workshop web pages that can be found at: http://www.cs.washington.edu/homes/gaetano/codes.html or http://www.ida.ing.tu-bs.de/codes.html Hope to see you there. Gaetano Borriello, Program Chair Rolf Ernst, General Chair ******************************************************************************* ADVANCE PROGRAM Monday, March 24 07:45-08:45 - Registration and Breakfast Buffet 08:45-09:00 - Opening Session - Welcome from chairs - Organization of program 09:00-10:30 - Session 1: Scheduling and Allocation - Enforcing Schedulability of Multi-Task Systems by Hardware-Software Codesign Y. Shin, K. Choi - Allocation of Multirate Systems on Multiprocessors with Memory Hierarchy Modeling and Optimization Y. Li, W. Wolf - An Approach to Mixed Systems Co-Synthesis T. Benner, R. Ernst - Critical Path Driven Cosynthesis for Hetergeneous Target Architectures P. Bjorn-Jorgensen, J. Madsen 10:30-10:45 - Break 10:45-12:00 - Session 2: Target Architectures and Debugging - A Generic Multi-Unit Architecture for Codesign Methodologies G. Gogniat, M. Auguin, C. Belleudy - An Event-Driven Multi-Threading Architecture for Embedded Systems R. Gerndt, R. Ernst - Design-For-Debug in Hardware/Software Co-Design H. P. E. Vranken, M. P. J. Stevens, M. T. M. Segers 12:00-13:30 - Lunch 13:30-15:00 - Session 3: Optimization - Modifying Min-Cut for Hardware and Software Functional Partitioning F. Vahid - Embedded Code Optimization via Common Control Structure Detection L. Lavagno, J. Cortadella, A. Sangiovanni-Vincentelli - Software Implementation Techniques for Hw/Sw Embedded Systems J. P. Calvez, O. Pasquier, J. Peckol - System Level Memory Optimization for Hardware-Software Co-Design K. Danckaert, F. Catthoor, H. De Man 15:00-15:15 - Break 15:15-17:00 - Invited Talks - Fault Tolerant Systems: Requirements and Restrictions for Electronic Mass Production in Autmotive Applications S. Schwehr, Temic (Daimler Benz) - Trade-offs in the Design of Mixed Hardware-Software Systems: a Perspective from Industry Kees Vissers, Philips Research Dinner at the hotel +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Tuesday, March 25 08:00-09:00 - Breakfast Buffet 09:00-10:30 - Session 4: Communication Issues - Communication Synthesis for Embedded Systems with Global Considerations R. B. Ortega, G. Borriello - Interface Optimization During Hardware-Software Partitioning L. Freund, D. Dupont, M. Israel, F. Rousseau - An Object-Oriented Communication Library for Hardware-Software CoDesign F. Vahid and L. Tauro - The Importance of Interfaces: A HW/SW Codesign Case Study D. C. R. Jensen, J. Madsen, S. Pedersen 10:30-10:45 - Break 10:45-12:00 - Session 5: Synthesis of Run-Time Environments - Run-Time Scheduler Synthesis for Hardware-Software Systems and Application to Robot Control Design V. Mooney, T. Sakamoto, G. De Micheli - Automatic Generation of a Real-Time Operating System for Embedded Systems F. Balarin, M. Chiodo, A. Jurecska, L. Lavagno, B. Tabbara, A. Sangiovanni-Vincentelli - Software Architecture Synthesis for Retargetable Real-Time Embedded Systems P. Chou, G. Borriello 12:00-13:30 - Lunch 13:30-15:00 - Session 6: Modeling and Simulation - A Flexible Model for Evaluating the Behavior of Hardware/Software Systems A. Allara, S. Filipponi, W. Fornaciari, F. Salice, D. Sciuto - A Codesign Environment Supporting Hardware/Software Modeling at Different Levels of Detail S. Kumar, F. Rose - Optimizing Communication in Embedded System Co-simulation K. Hines, G. Borriello - Modeling Micro-Controller Peripherals for High-Level Co-Simulation and Synthesis H. Hsieh, L. Lavagno, C. Passerone, C. Sansoe, A. Sangiovanni-Vincentelli 15:30-15:15 - Break Group Discussion: 15:15-17:00 - Java and Embedded System Design - L. Lavagno - Real-time Operating System Issues - R. Gupta 17:00-18:00 - Break 18:00-20:00 - Workshop Dinner 20:00 - Open discussion about organization, issues, and next workshop +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Wednesday, March 26 08:00-09:00 - Breakfast Buffet 09:00-10:30 - Session 7: Acceleration - Software Acceleration Using Coprocessors: Is it Worth the Effort? M. Edwards - Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators R. W. Hartenstein, J. Becker - A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor S. Kimura, M. Yukishita, Y. Itou, A. Nagoya, M. Hirao, K. Watanabe - A HW/SW Co-design Environment for Multi-media Equipments Development using Inverse Problem F. Suzuki, H. Koizumi, M. Hiramine, K. Yamamoto, H. Yasuura, K. Okino 10:30-10:45 - Break 10:45-12:00 - Session 8: Trading-off Hardware and Software - Architecture Synthesis and Partitioning of Real-Time Systems: A Comparison of Three Heuristic Search Strategies J. Axelsson - An Evolutionary Approach to System-Level Synthesis J. Teich, T. Blickle, L. Thiele - An Approach to the Synthesis of HW and SW in Codesign V. Carchiolo, M. Malgeri, G. Mangioni 12:00-13:30 - Lunch 13:30-15:00 - Closing Session - Five minute statements by attendees - Closing remarks ****************************************************************************** ****************************************************************************** REGISTRATION FORM Last Name: ______________________________________________________ First Name: ______________________________________________________ Affiliation: ______________________________________________________ or IEEE member number: ______________________________________________________ Member (IEEE or ACM): _____ Non-member: _____ Full-time student: _____ Street: ______________________________________________________ City / State: ______________________________________________________ Postal Code / Country: ______________________________________________________ Daytime Phone Number: ______________________________________________________ Fax Number: ______________________________________________________ Email: ______________________________________________________ Do you have any special needs: ______________________________________________ ______________________________________________________ ______________________________________________________ ______________________________________________________ Advance Registration Fees (until February 28, 1997): Members (ACM or IEEE) ____________ DM 480 Non-members ____________ DM 600 Full-time students ____________ DM 360 Late / On-Site Registration Fees (after February 28, 1997): Members (ACM or IEEE) ____________ DM 590 Non-members ____________ DM 730 Full-time students ____________ DM 440 Registration fees include the Workshop reception, Monday dinner and Tuesday banquet, 2 lunch buffets, all refreshments at breaks as well as one copy of the Workshop Proceedings. Checks and money transfers should be drawn to: "73640 - Codes/CASHE'97" Bankhaus Lobbecke und Co Acct.No.: 1 500 000 Bank Code: 270 30 500 Please send checks to: B. Boettger "Codes/CASHE'97" Institut fur Datenverarbeitungsanlagen Technische Universitat Braunschweig Hans-Sommer-Str. 66 D-38106 Braunschweig Germany After receipt of the registration fee, you will get a confirmation via mail or email. No refunds will be made unless a written request for cancellation is made before February 28, 1997. ****************************************************************************** ****************************************************************************** ACCOMODATIONS The "Holiday Inn" at Braunschweig Auguststr. 6-8 Tel.: +49 531 48 14-0 D-38100 Braunschweig Fax.: +49 531 48 14-100 This year's Workshop location is the "Holiday Inn" at Braunschweig which is an upper-class hotel with 140 bedrooms, 10 meeting rooms, bar and restaurant. A limited number of rooms have been blocked for the Codes/CASHE'97 Workshop. Please make your reservation directly to the hotel's reservations department (tel.: ++49 531 4814 ext. 706 or fax: ++49 531 4814 ext. 100) by Saturday, March 22, 1997, 5:00 p.m., stating that you will be attending the Codes/CASHE 97 workshop to take advantage of the special rate. After this date, reservations will be based on room and rate availability. Rooms will be held until 6:00 p.m. unless guaranteed with an accepted credit card. Check-in time is 1:00 p.m., guests can check in earlier subject to room availability, check-out time is 1:00 p.m. Cancellation policy is 2 weeks prior to arrival. The special hotel rates for the workshop are: Single: DM 146 (~US$97) Double: DM 175 (~US$117) No extra tax charges. These rates include a breakfast buffet. ****************************************************************************** From codesign-request@ifi.unizh.ch Thu Feb 6 02:58:24 1997 Return-Path: Received: from omega.ntu.ac.sg by josef.ifi.unizh.ch with SMTP (PP) id <27365-0@josef.ifi.unizh.ch>; Thu, 6 Feb 1997 02:58:00 +0100 Received: from ntuvax.ntu.ac.sg by ntuvax.ntu.ac.sg (PMDF V5.0-6 #7636) id <01IF2BRU3N7KAM5WPL@ntuvax.ntu.ac.sg> for codesign@ifi.unizh.ch; Wed, 05 Feb 1997 17:05:02 +0800 Date: Wed, 05 Feb 1997 17:05:02 +0800 From: ISIC97@ntuvax.ntu.ac.sg Subject: CFP: International Symposium On IC Technology, Systems & Applications To: codesign@ifi.unizh.ch Message-id: <01IF2BRU3RXEAM5WPL@ntuvax.ntu.ac.sg> Organization: Nanyang Technological University - Singapore X-VMS-To: IN%"codesign@ifi.unizh.ch" MIME-version: 1.0 Content-type: TEXT/PLAIN; CHARSET=US-ASCII Content-transfer-encoding: 7BIT Status: RO X-Status: http://gamma.ntu.ac.sg:8000/~isic97/cfp.html ISIC-97 7TH INTERNATIONAL SYMPOSIUM ON IC TECHNOLOGY, SYSTEMS & APPLICATIONS 10 - 12 September 1997 Hyatt Regency, Singapore ORGANIZER School of Electrical & Electronic Engineering Nanyang Technological University Singapore SUPPORTED BY Lucent Technologies, Bell Labs Innovations IEEE Singapore Section IEE Singapore Centre THE SYMPOSIUM The 7th International Symposium on IC Technology, Systems and Applications, ISIC-97, will be held on 10-12 September 1997. Four tutorial sessions will be held in parallel on the first day. This symposium will provide a forum for IC designers and manufacturing engineers, as well as academics to present and share new research and development results, techniques and problems. ISIC-97 coincides with the 50th anniversary of the invention of the TRANSISTOR. To celebrate this occasion, the symposium will be highlighted by the following keynote addresses : 1. The Invention of the Transistor - The Foundation of the Silicon Age - Ian Ross, President Emeritus of Bell Laboratories 2. Chips, Circuits and Systems in a Works-with World - Arno Penzias, Nobel Laureate, Vice President of Research, Lucent Technologies / Bell Laboratories 3. The Integrated Circuit into the Next Century: When Do We Approach the Limits of Physics, Complexity, and Affordability? - Mark Pinto, Director, IC Research, Lucent Technologies / Bell Laboratories 4. Issue of Manufacturing Limitations on ICs. - Mark Melliar-Smith, President and CEO of SEMATECH Papers are solicited in subject areas including but not limited to the following: A. DEVICE & IC TECHNOLOGY 1. Compound Semiconductor Devices 2. SOI 3. Testing and Yield Enhancement 4. Process Simulation 5. Device Physics and Modeling 6. Scaling of Devices and Technologies 7. New Processes and Materials 8. Reliability and Failure Analysis 9. Assembly and Packaging B. INTEGRATED CIRCUITS AND SYSTEMS 1. Artificial Neural Networks and Fuzzy Logic 2. Fault-Tolerant Circuits 3. Circuit Design and Architecture 4. Timing and Communications 5. IC Sensors and MEMs 6. Switched Capacitor and Current Mode Circuits 7. Multiple-Valued Logic Circuits 8. BiCMOS Circuits 9. Low-Power Low-Voltage IC designs 10.Memories 11.Mixed-Signal Circuits and Systems C. DESIGN AUTOMATION 1. Logic and System Synthesis 2. Simulation, Verification and Testability 3. Performance Optimization Methods 4. AI Methodology 5. Physical Design and Back Annotation 6. Innovative Design Capture Techniques 7. High Level Description Language 8. MCM Layout D. APPLICATIONS 1. Audio, Electroacoustics and Video 2. Military Applications 3. Cellular Mobile Communications 4. Switched Mode Power Supplies 5. Broadband Communication Applications E. SIGNAL PROCESSING 1. Speech and Image Processing 2. Multi-Dimensional Signal Processing 3. Wavelet Theory & Applications 4. Acoustic Signal Processing 5. Adaptive and Nonlinear Filtering 6. Multimedia 7. Specialized Signal Processors TUTORIAL SESSIONS The following four tutorial sessions will be held in parallel on 10 September 1997 : 1. RF IC Design and Systems - Lucent Technologies, USA 2. DSP IC Design and Systems - Mentor Graphics, USA 3. Behavioral Synthesis - The Next 10X Productivity Improvement for VLSI Design - Synopsys, USA 4. Low Power IC Design - Kaushik Roy, Purdue University, USA PAPERS OF SPECIAL INTEREST 1. Dynamic Translinear Circuits - J. Mulder, W.A. Serdijn, A.C. Vander Woerd, A.H.M. Van Roermund Delft University of Technology, The Netherlands 2. Decision Diagrams for Representation of Discrete Functions in VLSI Computer-Aided Design Systems - R.S. Stankovic, University of Nis, Yugoslavia - B.J. Falkowski, Nanyang Technological University, Singapore 3. Evolutionary Algorithms for Computer-Aided Design of Integrated Circuits - Rolf Drechsler, Albert-Ludwigs University, Germany PRELIMINARY REGISTRATION 7TH INTERNATIONAL SYMPOSIUM ON IC TECHNOLOGY, SYSTEMS & APPLICATIONS (ISIC-97) 10 - 12 September 1997, Hyatt Regency, Singapore (Please photocopy this form for additional registrations) ( ) I intend to present a paper. The abstract is attached. Subject Area / Category (e.g. A1, B2 .. etc) ( ) I intend to attend the symposium. Please send me further details and the registration form. ( ) I intend to attend Tutorial Session # 1 2 3 4 ( Please ( where applicable.) Family Name: ___________________________ Given Name : _____________________ (Prof/Dr/Mr/Mrs/Ms) Job Title: ________________________________________________________________ Organization: _____________________________________________________________ Address: __________________________________________________________________ __________________________________________________________________ __________________________________________________________________ Country : ___________________________Email : _______________________________ Telephone : __________________________ Fax : _______________________________ Names and addresses of individuals who might be interested in this symposium are: Name: __________________________ Name : ______________________________ Organization: __________________ Organization: _______________________ Address : ______________________ Address : __________________________ ______________________ __________________________ ______________________ __________________________ Country ________________________ Country __________________________ Fax : __________________________ Fax : ___________________________ Email : ________________________ Email: ___________________________ EXHIBITION An exhibition of relevant industrial equipment and systems will be held in conjunction with the regular sessions for paper presentations on the second and third day of the symposium REGISTRATION FEE Tutorials 10 Sept. 1997 S$200 per session (payment made by 15 June 1997) (fee inclusive of tutorial handout, lunch, tea breaks and 3% GST) Symposium 11 & 12 Sept. 1997 Early Bird: S$500 (payment made by 15 June 1997) Standard : S$600 (payment after 15 June 1997) (fee inclusive of symposium proceedings, tea breaks, lunches, banquet and 3% GST) Exchange Rate : US$1 ( S$1.40 KEYDATES Submission of extended summary : 31 March 1997 Notification of Acceptance : 30 April 1997 Submission of camera-ready papers : 15 June 1997 SUBMISSION OF PAPERS Authors are invited to submit three copies of an extended summary of not more than 1000 words and preferably with diagrams, illustrations and references by 31 March 1997. Please send summary to: ISIC-97 Secretariat Ms Goh Bee Dee/ Ms Merlin Toh Nanyang Technological University Centre for Continuing Education Administration Annex #04-06 Nanyang Avenue Singapore 639798 Republic of Singapore E-mail: isic97@ntuvax.ntu.ac.sg Fax: (65) 793-0997 Tel: (65) 799-4723 Web page: http://gamma.ntu.ac.sg:8000/~isic97/cfp.html INTERNATIONAL ADVISORY COMMITTEE C Y Chang National Chiao Tung University M I Elmasry University of Waterloo K Emerson Mentor Graphics M H Er Nanyang Technological University Y C Jenq Portland State University C M Melliar-Smith Lucent Technologies W Milne Cambridge University A Sedra University of Toronto D B Scott Texas Instruments R Steele University of Southampton C M Tang Lucent Technologies T L Tansley Macquarie University J West Philips Semiconductors ORGANIZING COMMITTEE Symposium Chairman Y C Tong Symposium Co-Chairman M A Do Advisor H S Tan Secretary K T Lau Technical Programme S S Rofail Publications & Publicity L S Ng Finance D J Wong-Ho Logistics T H Ooi From codesign-request@ifi.unizh.ch Fri Feb 7 12:36:49 1997 Return-Path: Received: from yeti.dit.upm.es by josef.ifi.unizh.ch with SMTP (PP) id <23186-0@josef.ifi.unizh.ch>; Fri, 7 Feb 1997 12:01:22 +0100 Received: (lsanchez@localhost) by yeti.dit.upm.es (8.8.4/3.13) id LAA05873; Fri, 7 Feb 1997 11:52:08 +0100 (MET) Message-Id: <199702071052.LAA05873@yeti.dit.upm.es> Subject: CHDL '97 Advanced Programm To: sig-vhdl@ercole.cefriel.it, cobra@fzi.de, codesign@ifi.unizh.ch Date: Fri, 7 Feb 1997 11:52:08 +0100 (MET) From: Luis Sanchez Fernandez MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Status: RO X-Status: Dear Sir/Madam please find enclosed the Advanced Program of CHDL '97. My sincere apologies if you receive this message more than once. Regards, Luis Sanchez ---------------------------------------------------------------------------- CHDL '97 ADVANCE PROGRAMME ---------------------------------------------------------------------------- XIII IFIP WG 10.5 Conference on Computer Hardware Description Languages and Their Applications 1997 Silver Jubilee Hotel Beatriz - Toledo, Spain - 20-25 April 1997 ---------------------------------------------------------------------------- Note: This information about CHDL'97 can be found at http://www.it.uc3m.es/~ifip/chdl97/ and is mirrored at http://griao.IRO.UMontreal.CA/ifip/chdl97/ ---------------------------------------------------------------------------- Presentations Session C-1: Specification and Design of Reactive Systems G. Berry: Synchronous Languages for Hardware and Software Reactive Systems (Invited Talk) B. Kleinjohann, J. Tacken, Ch. Tahedl: Towards a Complete Design Method for Embedded Systems Using Predicate/Transition-Nets Session C-2: Verification Using Model Checking Techniques (+ Poster Presentations) F. Balarin, K. Sajid: Simplifying Data Operations for Formal Verification K. Schneider: CTL and Equivalent Sublanguages of CTL* R. Hojati, D. Dill, R.K. Brayton: Verifying Linear Temporal Properties of Data Insensitive Controllers Using Finite Instantiations C.-T. Chou, J.-L. Huang, M. Fujita: A High-Level Language for Programming Complex Temporal Behaviors and its Translation into Synchronous Circuits (Poster) J. Philipps, P. Scholz: System-Level Hardware Design with mu-Charts (Poster) M. Auguin, C. Belleudy, G. Gogniat: Interface Synthesis in Embedded Hardware-Software Systems (Poster) J.-P. Soininen, J. Saarikettu, V. Veijalainen, T. Huttunen: TripleS - A Formal Validation Environment for Functional Specifications (Poster) R.J. Machado, J.M. Fernandes, A.J. Proenca: SOFHIA: A CAD Environment to Design Digital Control Systems (Poster) A. Bardsley, D. Edwards: Compiling the Language Balsa to Delay Insensitive Hardware (Poster) C. Mandal, R.M. Zimmer: High-Level Synthesis of Structured Data Paths (Poster) Session C-3: Formal Characterizations of Systems K. Thirunarayan, R. Ewing: Charaterizing a Portable Subset of Behavioural VHDL-93 B. Berkane, S. Gandrabur, E. Cerny: Algebra of Communicating Timing Charts for Describing and Verifying Hardware Interfaces F. Corella, R. Shaw, C. Zhang: A Formal Proof of Absence of Deadlock for any Acyclic Network of PCI Buses Session C-4: Analog Languages V. Moser, H.-P. Amann, F. Pellandini: Behavioural Modelling of Sampled-Data with HDL-A and ABSynth Panel: Analog and Mixed-Signal HDLs Session C-5: Languages in Design Flows R. Camposano: Hardware Description Languages in Practical Design Flows (Invited Talk) J.-M. Daveau, G. Fernandes Marchioro, A.A. Jerraya: VHDL Generation from SDL Specification B. Landwehr, P. Marwedel, I. Markhof, R. Doemer: Exploiting Isomorphism for Speeding Up Binding in an Integrated Scheduling Allocation and Assignment Approach to Architectural Synthesis (Short Talk) Session C-6: Future Trends in Hardware Design (+ Poster Display) C. Ussery, S. Curry: Design and Verification Flows for Large Systems in Silicon (Special Talk) M. Heuchling, W. Ecker, M. Mrva: Applying the Software V-Process to the Hardware Design J. Mountjoy, P. Hartel, H. Corporaal: Modular Operational Semantic Specification of Transport Triggered Architectures Session C-7: HDLs for the XXI Century Panel: The Next HDL Paradigms? Session C-8: Formal Methods for Asynchronous and Distributed Systems F. Corella: The World of I/O: A Rich Application Area for Formal Methods (Invited Talk) H. Barringer, D. Fellows, G. Gough, A. Williams: Abstract Modelling of Asynchronous Micropipeline Systems using Rainbow R. Nalumasu, G. Gopalakrishnan: A New Partial Order Reduction Algorithm for Concurrent System Verification (Short Talk) ---------------------------------------------------------------------------- CHDL'97 Papers in Sessions of the VHDL Users' Forum in Europe L. Kruse, D. Rabe, W. Nebel: VHDL Power Simulator: Power Analysis at Gate Level J. Benzakki, B. Djafri: Object Oriented Extensions to VHDL. The LaMI Proposal ---------------------------------------------------------------------------- Joint Tutorials Tutorial 1 J. Bergstra, M. Broy, N. Harman, B. Moeller, A. Ponse: Formal Methods in Hardware Design Tutorial 2 J. Bhasker: The IEEE Standard VHDL Synthesis Packages: IEEE Std 1076.3-1996 Tutorial 3 S. Krolikoski, O. Levia, C. Ussery: VHDL Lite - How VHDL Can Be Slimmed Down Tutorial 4 L. Jozwiak: Quality-driven Design of Electronic Systems Tutorial 5 S. Olcoz: VLSI Embedded System Design Tutorial 6 W. Ecker: Behavioral and System-Level VHDL Tutorial 7 D. Andreu: Methods of PSPICE Analog, Digital and Mixed Behavioral Macromodeling of Electronic Devices and Circuits Tutorial 8 A. Vachoux: VHDL 1076.1 through Examples ---------------------------------------------------------------------------- General Chair Prof. Dr. Carlos Delgado Kloos Universidad Carlos III de Madrid C/Butarque, 15 E-28911 Leganes (Madrid/Spain) Tel: (+34-1) 624-9979 Fax: (+34-1) 624-9430 E-mail: chdl97@it.uc3m.es Program Chair Prof. Dr. Eduard Cerny Universite de Montreal C.P. 6128, Succ. Centre-Ville H3C 3J7 Montreal (Quebec) Canada Tel: (+1-514) 343-7472 Fax: (+1-514) 343-5834 E-mail: chdl97@iro.umontreal.ca Tutorial Chair Prof. Dr. Przemyslaw Bakowski IRESTE University of Nantes La Chantrerie, CP 3003 F-44087 Nantes cedex 03 (France) Tel: (+33) 240.68.30.79 Fax: (+33) 240.68.30.66 E-mail: pbakowsk@ireste.fr Exhibition Chair Dr. Serafin Olcoz Yanguas SIDSA Tel: (+34-1) 8043914 Fax: (+34-1) 8044551 E-mail: sera@www.tgi.es Local Arrangements Peter T. Breuer Salvador Lopez Mendoza Andres Marin Lopez Natividad Martinez Madrid Luis Sanchez Fernandez (UPM) Aurora Sanchez Garrido Ingenieria Telematica Universidad Carlos III de Madrid C/Butarque, 15 E-28911 Leganes (Madrid/Spain) Tel: (+34-1) 624-9947 Fax: (+34-1) 624-9430 E-mail: chdl97@it.uc3m.es Asia-Pacific Representative Prof. Masaharu Imai Department of Computer Science Graduate School of Engineering Science Osaka University 1-3 Machikane-yama, Toyonaka, Osaka, Japan 560 Tel & Fax: (+81-6) 850-6623 E-mail: imai@ics.es.osaka-u.ac.jp, m.imai@ieee.org Program Committee * David Agnew, Canada * Francois Anceau, France * Przemyslaw Bakowski, France * Mario R Barbacci, USA * Howard Barringer, UK * Graham Birtwistle, UK * Dominique Borrione, France * Raul Camposano, USA * Eduard Cerny, Canada * Luc Claesen, Belgium * Edmund M Clarke, USA * Francisco Corella, USA * Werner Damm, Germany * Carlos Delgado Kloos, Spain * Nikil D Dutt, USA * Hans Eveking, Germany * Norbert Fristacky, Slovakia * Masahiro Fujita, Japan * Ganesh Gopalakrishnan, USA * Werner Grass, Germany * Reiner Hartenstein, Germany * Graham Hellestrand, Australia * Masaharu Imai, Japan * Steven D Johnson, USA * Thomas Kropf, Germany * David C Luckham, USA * Paul Menchini, USA * Jean Mermet, France * Wolfgang Nebel, Germany * Adam Pawlak, Germany * Robert Piloty, Germany * Paolo Prinetto, Italy * Franz Rammig, Germany * Peter Schwarz, Germany * Jorgen Staunstrup, Denmark * P A Subrahmanyam, USA * Flavio Wagner, Brazil * Ronald Waxman, USA * Akihiko Yamada, Japan * Michael Yoeli, Israel ---------------------------------------------------------------------------- Toledo Toledo is without doubt one of the cities with the greatest density of monuments in the world. Nearly all the different stages of Spanish art are represented in Toledo, which has Moorish-Mudejar-Jewish buildings, such as the Transito and Santa Maria la Blanca Synagogues; Gothic structures, such as the splendid cathedral; and Renaissance buildings. In the 16th century, the city became home to El Greco, and Toledo has many of his paintings, among which is "The Burial of the Count of Orgaz", his masterpiece, which is housed in the Mudejar Church of Santo Tome. Among its many museums, of special note is the one located in the old Santa Cruz Hospital. ---------------------------------------------------------------------------- Toledo'97 events comprise CHDL'97, Spring'97 Conference of the VHDL Users' Forum for CAD in Europe, the Workshop on Libraries, Component Modelling and Quality Assurance and the Esprit NADA Workshop. There is only one registration for the combined event and the participants will receive all the proceedings. ---------------------------------------------------------------------------- ======================================================================= Toledo'97 HOTEL RESERVATION FORM Hotel Beatriz, Toledo ======================================================================= A block of rooms has been reserved for Toledo'97 participants. Please indicate that you attend Toledo'97 when making your reservation to benefit from the special rates. Please handle your reservation directly with the hotel *before March 1* to guarantee a room. 10% of the total amount will be withheld when making the reservation. Cancellation charge will be 10% of the total. Hotel Beatriz, Ctra. de Avila, km. 2,750 E-45005 Toledo, Spain Tel.: (+34-25) 222211 Fax: (+34-25) 215865 Please book accommodation for: Last name: ........................................................... First name: ........................................................... Affiliation: ........................................................... Address: ........................................................... Postal code: ...................... City: .............................. Country: ........................................................... Phone: ...................... Fax: .............................. The rates are: 6.805 Pta (double room + buffet breakfast) 10.015 Pta (double room + buffet breakfast + lunch) 10.540 Pta (single room + buffet breakfast) 13.750 Pta (single room + buffet breakfast + lunch) (7% VAT included) Room desired: [ ] Single [ ] Double (Together with:............................... ..............................................) [ ] Lunch Total (in Pta): .............. Arrival date: ..................... Departure date: ..................... METHODS OF PAYMENT [ ] Credit card: [ ] MasterCard/Eurocard [ ] Visa [ ] Diners [ ] American Express Card holder's name .......................................... Credit card number .......................................... Expiration date .......................................... Card holder's signature .......................................... ................... .......................................... Date Signature [ ] bank transfer to: INPARSA Account code: 6000023102; Bank code: 2038-5516-95 Bank Name: Caja Madrid Address: Agen 5, E-45005 Toledo/Spain *Please indicate participant's name and affiliation in the transfer!* ................... .......................................... Date Signature Please send the Hotel Reservation Form to the Hotel and the Reservation Form to the General Chair ======================================================================= Toledo'97 REGISTRATION FORM ======================================================================= Preliminary Conference Structure Su, 20 April Mo, 21 Tu, 22 We, 23 Th, 24 Fr, 25 Time April April April April April Morning C1 C5 V1 C8 V5 L1 V7 L3 L7 N4 9:00-10:30 Tutorials C2 C6 V2 V6 L2 V8 L4 L8 N5 11:00-13:00 Lunch Break Afternoon C3 N1 N3 V3 Social V9 L5 L9 14:30-16:00 Tutorials C4 N2 C7 V4 Event V10 L6 L10 16:30-18:00 ---------------------------------------------------------------------------- C=CHDL97, V=VHDL Users Forum, L=Workshop on Libraries..., N=NADA workshop ---------------------------------------------------------------------------- Please complete and sign this form, and send it by mail or fax to: Carlos Delgado Kloos Universidad Carlos III de Madrid C/Butarque, 15 E-28911 Leganes (Madrid/Spain) Spain Tel: (+34-1) 624-9947 Fax: (+34-1) 624-9430 E-mail: chdl97@it.uc3m.es Please use one form per person and write in block letters. I will attend the Toledo'97 events. Last name: ......................................................... First name: ......................................................... Affiliation: ......................................................... Address: ......................................................... Postal code: ...................... City: ............................ Country: ......................................................... Phone: ...................... Fax: ............................ Email: ......................................................... TUTORIALS If you are going to attend any tutorial, tick which one(s): Morning Tutorials: [ ] Tutorial 1: Formal Methods in Hardware Design [ ] Tutorial 3: VHDL Lite - How VHDL Can Be Slimmed Down [ ] Tutorial 5: VLSI embedded system design [ ] Tutorial 7: Methods of PSPICE analog, digital and mixed behavioral macromodeling of electronic devices and circuits Afternoon Tutorials: [ ] Tutorial 2: The IEEE Standard VHDL Synthesis Packages: IEEE Std 1076.3-1996 [ ] Tutorial 4: Quality-driven design of Electronic systems [ ] Tutorial 6: Behavioral and system-level VHDL [ ] Tutorial 8: VHDL 1076.1 through examples Registration Fees (in Pesetas) ------------------------------ on or before after March 1 March 1 Morning Tutorial: 20.000 20.000 .......... Afternoon Tutorial: 20.000 20.000 .......... Conference (Normal) 50.000 55.000 .......... Conference (Discount) 45.000 50.000 .......... Student (1): 30.000 35.000 .......... Social Event (excursion + banquet) ticket: 10.000 10.000 .......... Single day 20.000 20.000 .......... (tick which one(s)) ---------- Mon [ ] Tue [ ] Wed [ ] Thurs [ ] Fri [ ] TOTAL FEE (in Pesetas): .......... ========== (1) Please attach proof of student status (will also be requested at the welcome desk). * All fees are in Spanish Pesetas (Pta), payable in advance. * Early registration deadline is *March 1, 1997*. * Tutorial fee covers: tutorial admission, tutorial notes and refreshments on April 20, 1997 * Conference fee covers: conference admission, final proceedings and refreshments on April 21 to 25, 1997, Social Event on April 23, 1997 * Discount applies to [ ] IFIP, [ ] ATI or [ ] GUVE members. Membership No:................. * Student and one day fee don't cover the Social Event. Methods of payment (all payments in Spanish Pesetas): I would like to pay the registration fee by [ ] eurocheque (must accompany registration form) in Pesetas, payable to Universidad Carlos III de Madrid [ ] bank transfer to: Univ. Carlos III de Madrid, Ref. 442 Account code: 2110064856; Bank code: 0049-0581-19 Bank Name: Banco Central Hispano; Address: Juan de la Cierva 38, E-28911 Getafe (Madrid/Spain) Fees to be charged to the participant; Please indicate participant's name and affiliation in the transfer! [ ] cheque (must accompany registration form): in Pesetas, drawn to a Spanish bank, payable to Universidad Carlos III de Madrid, fees to be charged to the issuer of the cheque [ ] credit card: [ ] MasterCard/Eurocard [ ] Visa Card holder's name .......................................... Credit card number .......................................... Expiration date .......................................... Card holder's signature .......................................... Cancellation by mail or fax is possible if received by April 1, 1997, 75% of the payment will be refunded. After that date, no refunds will be made. A substitute participant can be named at any time. Please specify your dietary requirements for lunch and conference banquet: Please specify any other requirements: ................... .......................................... Date Signature Please send the Hotel Reservation Form to the Hotel and the Registration Form to the General Chair. From codesign-request@ifi.unizh.ch Tue Feb 11 22:37:47 1997 Return-Path: Received: from pol88b.polito.it by josef.ifi.unizh.ch with SMTP (PP) id <04809-0@josef.ifi.unizh.ch>; Tue, 11 Feb 1997 22:37:39 +0100 Received: from chiusella.polito.it.polito.it (chiusella.polito.it) by polito.it (PMDF V4.2-15 #3020) id <01IFASEYHX34HSK4OO@polito.it>; Tue, 11 Feb 1997 18:27:22 GMT+1 Received: by chiusella.polito.it.polito.it (4.1/SMI-4.1) id AA10777; Tue, 11 Feb 97 18:27:10 +0100 Date: Tue, 11 Feb 1997 18:27:10 +0100 From: prinetto@chiusella.polito.it (Paolo Prinetto) Subject: ETW'97: IEEE European Test Workshop - Remind To: codesign@ifi.unizh.ch Errors-to: Rapalino@cclix1.polito.it Errors-to: Rapalino@cclix1.polito.it Message-id: <9702111727.AA10777@chiusella.polito.it.polito.it> X-Envelope-to: codesign@ifi.unizh.ch Content-transfer-encoding: 7BIT Apparently-To: codesign@ifi.unizh.ch Status: RO X-Status: Dear colleague, March 1st 1997, the submission deadline for ETW'97: IEEE European Test Workshop is approaching quickly. For your convenience we enclose the call for papers. The ETW'97 internet web page at http://www.polito.it/etw97/ includes updated registration information. We look forward to hearing from you soon. Best regards. Paolo Prinetto ................................................................................. ETW'97 IEEE European Test Workshop Cagliari (Grand Hotel Chia Laguna), Italy May 28 - 30, 1997 The IEEE European Test Workshop is a well-recognized forum for presenting and discussing trends and hot topics in the area of electronic circuit and system testing. The Workshop provides the ideal environment for cross-fertilizing industrial and academic experiences and needs. You are all invited to submit your contributions to ETW'97, which moves from Montpellier to another nice seaside resort in the Mediterranean area. The topics include but are not limited to: - Test Automation - DFT and BIST - ATPG and Fault Simulation - IDDQ Testing - ATE - Application-Driven System Test - Synthesis for Testability - Online Test - Defect Analysis - Mixed-Signal and Analog Testing - Test Quality and Test Economics. The program committee invites original presentations in these areas. Each submission should include a 50-word abstract and a list of keywords, and may be a full paper or an extended summary. Also identify a contact author and include a complete mailing address, phone number, fax number and E-mail address. Submitted materials may be included in an informal workshop compendium of papers. Best contributions will be selected for publication in a special issue of the Journal of Electronic Testing: Theory and Applications (JETTA), published by Kluwer. If you wish to submit a presentation, please observe the following deadlines: * Submission deadline: March 1, 1997 * Notification of acceptance: April 15, 1997 Submit paper proposals to: ETW'97 Secretariat Politecnico di Torino Dip. Automatica e Informatica Corso Duca degli Abruzzi, 24 I-10129 Torino Italy Phone: +39 11 564.7043 Fax: +39 11 564.7099 E-mail: etw97@polito.it For general information, contact: Paolo Prinetto Politecnico di Torino Dip. Automatica e Informatica Corso Duca degli Abruzzi, 24 I-10129 Torino Italy Phone: +39 11 564.7007 Fax: +39 11 564.7099 E-mail: paolo.prinetto@polito.it The ETW'97 is sponsored by the IEEE Computer Society Test Technology Technical Committee, in cooperation with the European group of the Test Technology Technical Committee (ETTTC). Daily flights connect most European airports to Cagliari. A shuttle service will be provided from Cagliari airport to the Grand Hotel Chia Laguna. For further information, please visit the ETW'97 internet web page at http://www.polito.it/etw97/ ------------------------------------------------------------------------ General Chair P. Prinetto Politecnico di Torino (Italy) General Co-Chair T. W. Williams IBM (USA) General Vice Chair J. Figueras University of Catalunya (Spain) Program Chair H. J. Wunderlich University of Siegen (Germany) Program Co-Chair B. Bennetts LogicVision Europe (United Kingdom) Finance Chair M. Sonza Reorda Politecnico di Torino (Italy) Local Arrangements Chair A. Benso Politecnico di Torino (Italy) Publicity Chair C. Landrault LIRMM (France) Program Committee E.J. Aas - Univ. of Trondheim (NL) K. Baker - Philips (NL) S. Barbagallo - Italtel (I) B. Becker - Univ. of Freiburg (D) G. Carlsson - Ericsson (S) M. Croft - Mentor Graphics (UK) B. Courtois - TIMA CMP (F) W. Daehn - SICAN GmbH (D) C. Ellingham - Synopsys (USA) J. Figueras - Univ. of Catalunya (E) H. Fujiwara - NAIST (J) C. Gauthron - Compass (F) S. Griep - Siemens (D) J. Hlavicka - Univ. of Czech (CZ) A. Hlawiczka - Univ. of Gliwice (PL) H. Kerkhoff - Univ. of Twente (NL) G. Krueger - SNI (D) C. Landrault - LIRMM (F) C. Lopez Barrio - Telefonica I+D (E) D. Medina - Italtel (I) H. Manhaeve - KIHWV (B) M. Nicolaidis - TIMA CMP (F) P. Olivo - Univ. di Ferrara (I) A. Paschalis - NCSR (GR) Z. Peng - Univ. of Linkoping (S) P. Prinetto - Politecnico di Torino (I) M. Renovell - LIRMM (F) R. Segers - Philips Semiconductors (NL) J.P. Teixeira - INESC (P) R. Ubar - Univ. of Tallinn (EE) R. Wagner - Bosch (D) T. W. Williams - IBM (USA) V. Yarmolik - Univ. of Minsk (BY) Y. Zorian - LogicVision (USA) ................................................................................. From codesign-request@ifi.unizh.ch Tue Feb 11 07:43:52 1997 Return-Path: Received: from june.cs.washington.edu by josef.ifi.unizh.ch with SMTP (PP) id <06308-0@josef.ifi.unizh.ch>; Tue, 11 Feb 1997 07:43:41 +0100 Return-Path: Received: (gaetano@localhost) by june.cs.washington.edu (8.8.5+CS/7.2ju) id WAA02385; Mon, 10 Feb 1997 22:42:19 -0800 Date: Mon, 10 Feb 1997 22:42:19 -0800 From: gaetano@cs.washington.edu (Gaetano Borriello) Message-Id: <199702110642.WAA02385@june.cs.washington.edu> To: ahmed.jerraya@imag.fr, alberto@ic.EECS.Berkeley.EDU, brian_bailey@mentorg.com, codesign@ifi.unizh.ch, codesign@vhdl.org, ernst@ida.ing.tu-bs.de, fuhrman@gmr.com, gaetano@cs.washington.edu, gajski@uci.edu, gdp@el.wpafb.af.mil, hartenst@rhrk.uni-kl.de, isss-people@ics.uci.edu, jbuck@synopsys.com, jst@it.dtu.dk, keutzer@synopsys.com, koopman@cs.cmu.edu, mde@ap.co.umist.ac.uk, nanni@pegasus.stanford.edu, raul@synopsys.com, rgupta@gupta.ICS.UCI.EDU, roger@ahl.co.uk, rosenstiel@peanuts.informatik.uni-tuebingen.de, rwt@hpl.hp.co.uk, sciuto@elet.polimi.it, skumar@src.honeywell.com, thomas@ece.cmu.edu, vahid@cs.ucr.edu, wolf@princeton.edu, yasuura@is.kyushu-u.ac.jp Subject: Codes'97 Registration and Advance Program Status: RO X-Status: The 1997 Codes/CASHE'97 Workshop will be held in Braunschweig, Germany on 24-26 March 1997. The advance program, registration information and form, and accomodations details are attached. This information as well as much more is available at the workshop web pages that can be found at: http://www.cs.washington.edu/homes/gaetano/codes.html or http://www.ida.ing.tu-bs.de/codes.html Hope to see you there. Gaetano Borriello, Program Chair Rolf Ernst, General Chair **************************************************************************** ADVANCE PROGRAM Monday, March 24 07:45-08:45 - Registration and Breakfast Buffet 08:45-09:00 - Opening Session - Welcome from chairs - Organization of program 09:00-10:30 - Session 1: Scheduling and Allocation - Enforcing Schedulability of Multi-Task Systems by Hardware-Software Codesign Y. Shin, K. Choi Seoul National University; Seoul, Korea - Allocation of Multirate Systems on Multiprocessors with Memory Hierarchy Modeling and Optimization Y. Li, W. Wolf Princeton University; Princeton, New Jersey, USA - An Approach to Mixed Systems Co-Synthesis T. Benner, R. Ernst Technical University of Braunschweig; Braunschweig, Germany - Critical Path Driven Cosynthesis for Hetergeneous Target Architectures P. Bjorn-Jorgensen, J. Madsen Technical University of Denmark; Lyngby, Denmark 10:30-10:45 - Break 10:45-12:00 - Session 2: Target Architectures and Debugging - A Generic Multi-Unit Architecture for Codesign Methodologies G. Gogniat, M. Auguin, C. Belleudy Universite de Nice Sophia/Antipolis; Nice, France - An Event-Driven Multi-Threading Architecture for Embedded Systems R. Gerndt, R. Ernst Technical University of Braunschweig; Braunschweig, Germany - Design-For-Debug in Hardware/Software Co-Design H. P. E. Vranken, M. P. J. Stevens, M. T. M. Segers Eindhoven University of Technology/Philips Semiconductors; Eindhoven, Netherlands 12:00-13:30 - Lunch 13:30-15:00 - Session 3: Optimization - Modifying Min-Cut for Hardware and Software Functional Partitioning F. Vahid University of California; Riverside, California, USA - Embedded Code Optimization via Common Control Structure Detection L. Lavagno, J. Cortadella, A. Sangiovanni-Vincentelli Cadence Berkeley Laboratories; Berkeley, California, USA Universitat Politecnica de Catalunya; Barcelona, Spain University of California; Berkeley, California, USA - Software Implementation Techniques for Hw/Sw Embedded Systems J. P. Calvez, O. Pasquier, J. Peckol IRESTE/University of Nantes; Nantes, France - System Level Memory Optimization for Hardware-Software Co-Design K. Danckaert, F. Catthoor, H. De Man IMEC; Leuven, Belgium Katholieke Universiteit Leuven; Leuven, Belgium 15:00-15:15 - Break 15:15-17:00 - Invited Talks - Fault Tolerant Systems: Requirements and Restrictions for Electronic Mass Production in Autmotive Applications S. Schwehr, Temic (Daimler Benz); Germany - Trade-offs in the Design of Mixed Hardware-Software Systems: a Perspective from Industry Kees Vissers, Philips Research; Netherlands Dinner at the hotel +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Tuesday, March 25 08:00-09:00 - Breakfast Buffet 09:00-10:30 - Session 4: Communication Issues - Communication Synthesis for Embedded Systems with Global Considerations R. B. Ortega, G. Borriello University of Washington; Seattle, Washington, USA - Interface Optimization During Hardware-Software Partitioning L. Freund, D. Dupont, M. Israel, F. Rousseau LaMI/Universite D'Evry; Evry, France ESIM; Marseille, France - An Object-Oriented Communication Library for Hardware-Software CoDesign F. Vahid and L. Tauro University of California; Riverside, California, USA Quickturn Design Systems; Mountain View, California, USA - The Importance of Interfaces: A HW/SW Codesign Case Study D. C. R. Jensen, J. Madsen, S. Pedersen Technical University of Denmark; Lyngby, Denmark 10:30-10:45 - Break 10:45-12:00 - Session 5: Synthesis of Run-Time Environments - Run-Time Scheduler Synthesis for Hardware-Software Systems and Application to Robot Control Design V. Mooney, T. Sakamoto, G. De Micheli Stanford University; Stanford, California, USA - Automatic Generation of a Real-Time Operating System for Embedded Systems F. Balarin, M. Chiodo, A. Jurecska, L. Lavagno, B. Tabbara, A. Sangiovanni-Vincentelli Cadence Berkeley Labs; Berkeley, California, USA Alta Group of Cadence Design Systems; Sunnyvale, California, USA Magneti Marelli; Torino, Italy University of California; Berkeley, California, USA - Software Architecture Synthesis for Retargetable Real-Time Embedded Systems P. Chou, G. Borriello University of Washington; Seattle, Washington, USA 12:00-13:30 - Lunch 13:30-15:00 - Session 6: Modeling and Simulation - A Flexible Model for Evaluating the Behavior of Hardware/Software Systems A. Allara, S. Filipponi, W. Fornaciari, F. Salice, D. Sciuto ITALTEL-SIT/Central Research Labs; Milano, Italy CEFRIEL; Milano, Italy Politecnico di Milano; Milano, Italy - A Codesign Environment Supporting Hardware/Software Modeling at Different Levels of Detail S. Kumar, F. Rose Honeywell Technology Center; Minneapolis, Minnesota, USA - Optimizing Communication in Embedded System Co-simulation K. Hines, G. Borriello University of Washington; Seattle, Washington, USA - Modeling Micro-Controller Peripherals for High-Level Co-Simulation and Synthesis H. Hsieh, L. Lavagno, C. Passerone, C. Sansoe, A. Sangiovanni-Vincentelli University of California; Berkeley, California, USA Politecnico di Torino; Torino, Italy 15:30-15:15 - Break Group Discussion: 15:15-17:00 - Java and Embedded System Design - L. Lavagno - Real-time Operating System Issues - R. Gupta 17:00-18:00 - Break 18:00-20:00 - Workshop Dinner 20:00 - Open discussion about organization, issues, and next workshop +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Wednesday, March 26 08:00-09:00 - Breakfast Buffet 09:00-10:30 - Session 7: Acceleration - Software Acceleration Using Coprocessors: Is it Worth the Effort? M. Edwards University of Manchester/UMIST; Manchester, United Kingdom - Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators R. W. Hartenstein, J. Becker Universitaet Kaiserslautern; Kaiserslautern, Germany - A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor S. Kimura, M. Yukishita, Y. Itou, A. Nagoya, M. Hirao, K. Watanabe Nara Institute of Science and Technology; Japan NTT Communication Science Laboratory; Japan - A HW/SW Co-design Environment for Multi-media Equipments Development using Inverse Problem F. Suzuki, H. Koizumi, M. Hiramine, K. Yamamoto, H. Yasuura, K. Okino Mitsubishi Electric Corporation; Japan Kyushu University; Japan Japan Micro Systems Corporation; Japan 10:30-10:45 - Break 10:45-12:00 - Session 8: Trading-off Hardware and Software - Architecture Synthesis and Partitioning of Real-Time Systems: A Comparison of Three Heuristic Search Strategies J. Axelsson Linkoping University; Linkoping, Sweden - An Evolutionary Approach to System-Level Synthesis J. Teich, T. Blickle, L. Thiele Swiss Federal Institute of Technology; Zurich, Switzerland - An Approach to the Synthesis of HW and SW in Codesign V. Carchiolo, M. Malgeri, G. Mangioni Universita' di Catania; Catania, Italy 12:00-13:30 - Lunch 13:30-15:00 - Closing Session - Five minute statements by attendees - Closing remarks *************************************************************************** *************************************************************************** REGISTRATION FORM Last Name: ____________________________________________________ First Name: ____________________________________________________ Affiliation: ____________________________________________________ Member (IEEE or ACM): _____ Non-member: _____ Full-time student: _____ IEEE member number: ____________________________________________________ Street: ____________________________________________________ City / State: ____________________________________________________ Postal Code / Country: ____________________________________________________ Daytime Phone Number: ____________________________________________________ Fax Number: ____________________________________________________ Email: ____________________________________________________ Do you have any special needs: ____________________________________________ ____________________________________________________ ____________________________________________________ ____________________________________________________ Advance Registration Fees (until February 28, 1997): Members (ACM or IEEE) ____________ DM 480 Non-members ____________ DM 600 Full-time students ____________ DM 360 Late / On-Site Registration Fees (after February 28, 1997): Members (ACM or IEEE) ____________ DM 590 Non-members ____________ DM 730 Full-time students ____________ DM 440 Registration fees include the Workshop reception, Monday dinner and Tuesday banquet, 2 lunch buffets, all refreshments at breaks as well as one copy of the Workshop Proceedings. Checks and money transfers should be drawn to: "73640 - Codes/CASHE'97" Bankhaus Lobbecke und Co Acct.No.: 1 500 000 Bank Code: 270 30 500 Please send checks to: B. Boettger "Codes/CASHE'97" Institut fur Datenverarbeitungsanlagen Technische Universitat Braunschweig Hans-Sommer-Str. 66 D-38106 Braunschweig Germany After receipt of the registration fee, you will get a confirmation via mail or email. No refunds will be made unless a written request for cancellation is made before February 28, 1997. *************************************************************************** *************************************************************************** ACCOMODATIONS The "Ramada Inn" at Braunschweig Auguststr. 6-8 Tel.: +49 531 48 14-0 D-38100 Braunschweig Fax.: +49 531 48 14-100 This year's Workshop location is the "Ramada Inn" at Braunschweig which is an upper-class hotel with 140 bedrooms, 10 meeting rooms, bar and restaurant. Note that the hotel has recently changed ownership (it used to be a "Holiday Inn"). A limited number of rooms have been blocked for the Codes/CASHE'97 Workshop. Please make your reservation directly to the hotel's reservations department (tel.: ++49 531 4814 ext. 706 or fax: ++49 531 4814 ext. 100) by Saturday, March 22, 1997, 5:00 p.m., stating that you will be attending the Codes/CASHE 97 workshop to take advantage of the special rate. After this date, reservations will be based on room and rate availability. Rooms will be held until 6:00 p.m. unless guaranteed with an accepted credit card. Check-in time is 1:00 p.m., guests can check in earlier subject to room availability, check-out time is 1:00 p.m. Cancellation policy is 2 weeks prior to arrival. The special hotel rates for the workshop are: Single: DM 146 (~US$97) Double: DM 175 (~US$117) No extra tax charges. These rates include a breakfast buffet. *************************************************************************** From codesign-request@ifi.unizh.ch Mon Feb 17 09:26:45 1997 Return-Path: Received: from bikini.ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <14664-0@josef.ifi.unizh.ch>; Mon, 17 Feb 1997 09:26:33 +0100 Return-Path: X-Received: from epsilon.ece.nwu.edu by josef.ifi.unizh.ch with SMTP (PP) id <18601-0@josef.ifi.unizh.ch>; Fri, 14 Feb 1997 01:38:17 +0100 X-Received: (from daemon@localhost) by epsilon.ece.nwu.edu (8.8.5/8.8.3) id MAA06184 for ; Thu, 13 Feb 1997 12:21:23 -0600 (CST) X-Received: from seattle.ece.nwu.edu(129.105.5.174) by epsilon.ece.nwu.edu via smap (V2.0beta) id xma006181; Thu, 13 Feb 97 12:21:20 -0600 X-Received: (from hauck@localhost) by seattle.ece.nwu.edu (8.8.5/8.8.3) id MAA19220 for fpga97; Thu, 13 Feb 1997 12:21:19 -0600 (CST) Date: Thu, 13 Feb 1997 12:21:19 -0600 (CST) From: Scott Alan Hauck Message-Id: <199702131821.MAA19220@seattle.ece.nwu.edu> To: fpga97@seattle.ece.nwu.edu Subject: Special Issue of TVLSI on FPGA Technology ReSent-Date: Mon, 17 Feb 1997 09:26:24 +0100 (MET) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Message-ID: Status: RO X-Status: ================================================================== CALL FOR PAPERS SPECIAL ISSUE ON RECENT ADVANCES IN FPGA TECHNOLOGY IEEE TRANSACTIONS ON VLSI SYSTEMS Field-Programmable Gate Arrays (FPGAs) have become an important technology for the implementation of VLSI circuits and systems due to the steady increase in FPGA density and speed. Aside from main-stream use in reasonably high volume production, the field- programmability and re-programmability of FPGAs enable many novel and promising applications, including rapid system prototyping, reconfigurable system designs, rapid system prototyping, circuit emulation, and reconfigurable custom computing. This special is- sue will be devoted to recent advances in all areas related to the FPGA technology. Topics of interest include, but not limited to: o Advances in FPGA architectures, including design of programm- able logic blocks, programmable interconnects, programmable I/Os, and development of new FPGAs and field-configurable memories. o Novel applications of FPGAs, including rapid prototyping, logic emulation, reconfigurable custom computing, and dynamically reconfigurable applications. o New CAD algorithms and tools for FPGAs, including new algo- rithms for sequential and combinational logic optimization, technology mapping, partitioning, placement, routing, and de- velopment of new FPGA synthesis or layout systems. o Advances in field-programmable technology, including new pro- cess and fabrication technologies, and field-programmable analog arrays. Authors of papers accepted for the 1997 ACM/SIGDA 5th Interna- tional Symposium on Field-Programmable Gate Arrays (FPGA'97) are especially encouraged to submit an extended version of their pa- pers for possible inclusion in the special issue. Submissions of relevant work not presented at FPGA'97 are also welcome. This special issue is being coordinated by Guest Editors Jason Cong of Univ. of California, Los Angeles (UCLA) and Carl Ebeling of Univ. of Washington. Prospective authors should submit postscript versions of their papers electronically using the www no later than March 31, 1997, and indicate they should be considered for this special issue: http://microsys6.engr.utk.edu/~tvlsi Alternatively, email may be used by contacting: tvlsi@microsys6.engr.utk.edu If neither of the electronic means is available to authors, trad- itional paper manuscripts should be sent to: IEEE Trans. on VLSI Systems c/o Prof. Bing Sheu Electrical Engineering Powell Hall, Room 604 University of Southern California Los Angeles, CA 90089-0271 ================================================================== From codesign-request@ifi.unizh.ch Thu Feb 20 10:22:58 1997 Return-Path: Received: from bikini.ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <17082-0@josef.ifi.unizh.ch>; Thu, 20 Feb 1997 10:22:51 +0100 Return-Path: <@uklirb.informatik.uni-kl.de:abakus@informatik.uni-kl.de> X-Received: from news.uni-kl.de by josef.ifi.unizh.ch with SMTP (PP) id <15982-0@josef.ifi.unizh.ch>; Thu, 6 Feb 1997 14:55:24 +0100 X-Received: from uklirb.informatik.uni-kl.de by news.uni-kl.de id uy25323; 6 Feb 97 14:54 MET X-Received: from irz1.informatik.uni-kl.de by uklirb.informatik.uni-kl.de id aa16804; 6 Feb 97 13:51 MET X-Received: by irz1.informatik.uni-kl.de (SMI-8.6/SMI-SVR4) id NAA21755; Thu, 6 Feb 1997 13:51:14 +0100 From: AG Hartenstein-UNI KL-FRG Message-Id: <199702061251.NAA21755@irz1.informatik.uni-kl.de> Subject: CfP: Emerging Software and Configware Technology To: pilz@ifi.unizh.ch Date: Thu, 6 Feb 1997 13:51:14 +0100 (MET) X-Mailer: ELM [version 2.4 PL24] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit ReSent-Date: Thu, 20 Feb 1997 10:22:03 +0100 (MET) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Message-ID: Status: RO X-Status: Subject: CfP: Emerging Software and Configware Technology C A L L F O R P A P E R S --- C A L L F O R R E V I E W E R S : Dear colleagues, Innovative hardware platforms and more and more blurring hardware/software boundaries stimulate advances in new directions of software technology. Configware is becoming a novel paradigm - as a layer between hardware and software. Hardware has become soft. Dynamically reconfigurable hardware (configware) is evolving from tinkertoy approach to structural programming paradigm, introducing a new class of instruction level parallelism (ILP). Novel architectures drive the need for new compilation techniques. Compiler and language designers must cooperate with hardware architects to exploit combinations of instruction level parallelism and concurrency by optimizing multi paradigm compilers for a novel class of inhomogenous high performance systems including new and emerging add-on technology platforms. See the following Call for papers - especially Minitrack-4. If you have questions, please do not hesitate to contact me. To keep things moving, we need your input: submit! - join us as a reviewer. _______________________________________________________________________ _______________________________________________________________________ Call For Papers and Referees Software Technology Track of the 31st Hawaii International Conference on System Sciences (HICSS-31) The Big Island of Hawaii - JANUARY 6-9, 1998 (14 minitracks) http://www.cba.hawaii.edu/hicss _______________________________________________________________________ _______________________________________________________________________ Authors are invited to submit papers describing the new advances in emerging software technology. We welcome papers that may be theoretical, conceptual, tutorial, or descriptive in nature. The Software Technology Track consists of the following fourteen (14) minitracks that cover a selection of emerging and strategically important areas in software. Minitrack-1: Agent Mobility and Communication Minitrack-2: Compiling for Distributed Embedded Systems Minitrack-3: Computational Steering Minitrack-4: Configware: dynamic Redefinition of Hardware/Software Boundary Minitrack-5: Coordination Languages, Models, Systems Minitrack-6: Distributed Heterogeneous Information Services Minitrack-7: Engineering Client-Server Systems Minitrack-8: Environmental Informatics Minitrack-9: High Speed Networks Minitrack-10: Performance Evaluation of Distributed Systems Minitrack-11: Virtual Shared Memory for Distributed Architectures Minitrack-12: Web Computing in Theory and Practice Minitrack-13: Wireless Networks and Mobile Computing Minitrack-14: Workflow Systems <<< Topics & coordinators of the above 14 minitracks are listed at the end >>> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ _______________________________________________________________________ Chairman --------- Hesham El-Rewini Department of Computer Science University of Nebraska at Omaha Omaha, NE 68182 Phone: (402) 554-2852 Fax: (402) 554-2975 Email: rewini@cs.unomaha.edu _______________________________________________________________________ 1997 Deadlines -------------- o A 300-word abstract by March 17 o Feedback to author on abstract by April 15 o Eight copies of the manuscript by June 2 o Notification of accepted papers by August 31 o Camera-ready copies of accepted manuscripts are due by October 1 _______________________________________________________________________ Instructions for Authors ------------------------ Submit a 300-word abstract to one of the minitrack coordinators according to their areas of responsibility (listed below) by March 17, 1997. Feedback on the appropriateness of the abstract will be sent to you by April 15, 1997. Submit eight (8) copies of the full manuscript by June 2, 1997. Manuscripts should have an abstract and be 22-25 typewritten, double-spaced pages in length. Papers must not have been previously presented or published, nor currently submitted for journal publication. Each manuscript will be subjected to a rigorous refereeing process involving at least five reviewers. Individuals interested in refereeing papers should contact the minitrack coordinators directly. _______________________________________________________________________ Tutorials --------- Tutorials will be offered on Tuesday, January 6, 1998. Interested speakers should submit full-day or half-day proposals to the chairman by March 17, 1997. _______________________________________________________________________ Track Advisory Committee ------------------------ - Gul Agha, University of Illinois, USA - Asuman Dogac, Middle East Technical University, Turkey - Wolfgang A. Halang, Fernuniversitaet, GERMANY - Abdelsalam Helal, MCC, USA - Innes Jelly, Sheffield Hallam University, UK - Michael A. Langston, University of Tennessee, USA - Alexey Lastovetsky, Russian Academy of Science, RUSSIA - Keqin Li, State University of New York, USA - Gregory A. Riccardi, Florida State University, USA - John Rosenberg, University of Sydney, AUSTRALIA - Diane T. Rover, Michigan State University, USA - Alok Sinha, Microsoft, USA - Anthony Skjellum, Mississippi State University, USA - Alexander D. Stoyenko, New Jersey Institute of Technology, USA - Ivan Stojmenovic, University of Ottawa, CANADA - Caetano Traina Junior, University of Sao Paulo, BRAZIL - Chung-Kwong Yuen, National University of Singapore, SINGAPORE - Albert Y. Zomaya, The University of Western Australia, AUSTRALIA _______________________________________________________________________ Topics and Coordinators of the Minitracks ***************************************** MINITRACK-1: AGENT MOBILITY AND COMMUNICATION ---------------------------------------------- Mobile agent infrastructure (transporting, naming, locating), multi-agent communication (brokering, mediation, filtering, routing, resource management), security, language support, agent standardization and agent based applications (Web data mining, online commerce, factory automation, etc.) COORDINATORS ------------ o Dejan Milojicic, dejan@osf.org TOG Research Institute, 11 Cambridge Center, Cambridge MA, 02142 o David Musliner, musliner@src.honeywell.com Honeywell Technology Center, MN65-2200, 3660 Technology Drive, Minneapolis, MN 55418 o Wolfgang Schroeder-Preikschat, wosch@cs.uni-potsdam.de University of Potsdam, Computer Science Department, Am Neuen Palais 10,14469 Potsdam, GERMANY _______________________________________________________________________ MINITRACK-2: COMPILING FOR DISTRIBUTED EMBEDDED SYSTEMS -------------------------------------------------------- Languages and paradigms, intermediate forms, extensions to conventional languages, macro and instruction level optimizations, instruction level parallelism , VLIW and multi-threading, speculative execution of code, branch-prediction techniques, compiling for compact binaries, source level transformations, partitioning and scheduling, continuos compilation with interpretation. COORDINATORS ------------ o Sandeep Kumar, sandeep@hpl.hp.com Hewlett-Packard Labs, 1 Main Street, Cambridge, MA 02142 o Santosh Pande, santosh.pande@uc.edu ECECS Dept., University of Cincinnati, Cincinnati, OH 45246 o Sekhar Darbha, darbha@ece.rutgers.edu ECE Dept., Rutgers University, Piscataway, NJ 08855 _______________________________________________________________________ MINITRACK-3: COMPUTATIONAL STEERING ------------------------------------ Applications: performance optimization, scientific visualization, scientific computations, modeling and design, simulations, network configuration and management. Infrastructure: instrumentation, monitoring and data collection, visualization and presentation, logging and evaluation of interactions, consistent snapshots, consistent updates, combined algorithmic and interactive approaches. COORDINATOR ----------- o Eileen Kraemer, eileen@cs.wustl.edu Washington University, Campus Box 1045, St. Louis, MO 63130 _______________________________________________________________________ MINITRACK-4: CONFIGWARE: DYNAMIC REDEFINITION OF HARDWARE/SOFTWARE BOUNDARY --------------------------------------------------------------------------- ILP (Instruction Level Parallelism) combining hardware and configware, innovative configware: from glue logic to programming paradigm, load balancing in host/accelerator heterogenous processing, innovative software frameworks, partitioning parallelizing compilers, reconfiguration from programming language sources (also new languages), speed-up by migration: software/configware/hardware, runtime/compiletime. COORDINATOR ----------- o Reiner W. Hartenstein, hartenst@rhrk.uni-kl.de Universitaet Kaiserslautern, Informatik (CS&E), Bau 12, Postfach 3049, D-67653 Kaiserslautern, Germany _______________________________________________________________________ MINITRACK-5: COORDINATION LANGUAGES, MODELS, SYSTEMS ----------------------------------------------------- Models, languages and mechanisms for coordination; operating system and middleware support; coordination mechanisms for WWW and multi-agent systems; compiling techniques and semantic issues for coordination languages; coordination in software architecture design, case studies with industrial relevance. COORDINATORS ----------- o Paolo Ciancarini, cianca@cs.unibo.it Dept. of Computer Science, Univ. of Bologna Pza. di Porta S.Donato, 5, 40127 Bologna, ITALY o Chris Hankin, clh@doc.ic.ac.uk Dept. of Computing, Imperial College, University of London, Huxley Building, 180 Queen's Gate, London SW7 2BZ, UK o Robert Tolksdorf, tolk@cs.tu-berlin.de Technische Universitat Berlin, Fachbereich 13, Informatik, Sekr. FR 6-10, D-10587 Berlin, GERMANY _______________________________________________________________________ MINITRACK-6: DISTRIBUTED HETEROGENEOUS INFORMATION SERVICES ------------------------------------------------------------ Core technology: Interoperability, novel open distributed architectures, mediator architectures. Languages and applications: active databases, data warehouses, advanced query models, data mining and knowledge discovery. Integration challanges: object and transaction model integration, global information. Multi-media information services. COORDINATORS ------------ o John Mylopoulos, jm@cs.toronto.edu Dept. of Computer Science, University of Toronto, Toronto, Ontario M5S 3H5, CANADA o Avigdor Gal, avigal@cs.toronto.edu Dept. of Computer Science, University of Toronto, Toronto, Ontario M5S 3H5, CANADA _______________________________________________________________________ MINITRACK-7: ENGINEERING CLIENT-SERVER SYSTEMS ----------------------------------------------- Downsizing and porting to client-server platforms, performance evaluation, design and management of client-server systems, object-oriented design techniques, support and CASE tools, validation and verification, practical experiences in building and assessing the performance of client-server systems. COORDINATORS ------------ o Doug Schmidt, schmidt@cs.wustl.edu Dept. of Computer Sc., Washington University, St. Louis, Missouri 63130-4899 o Stefano Russo, sterusso@unina.it Dipartimento di Informatica e Sistemistica, Universita' di Napoli "Federico II", Via Claudio 21, 80125 Napoli, ITALY _______________________________________________________________________ MINITRACK-8: ENVIRONMENTAL INFORMATICS --------------------------------------- Organized responses to environmental problems that may involve: storage, management and retrieval for large scientific databases (distributed ownership, heterogeneity, access, security, legacy, quality assurance); noisy and uncertain task environments; irregular spatial and temporal data distributions; knowledge representation; statistical computing, expert systems; visualization; decision support; Web-based collaboration. COORDINATORS ------------ o David A. Swayne, dswayne@uoguelph.ca Computing and Information Science Department, University of Guelph, Guelph Ontario, N1G 2W1, CANADA o Ralf Denzer Hochschule fuer Technik und Wirtschaft des Saarlandes Saarbruecken, Germany o Gerald Schimak Austrian Research Center Seibersdorf, Austria _______________________________________________________________________ MINITRACK-9: HIGH SPEED NETWORKS --------------------------------- Design and analysis of transmission algorithms, design and analysis of distributed protocols, dynamic and static routing schemes, analysis of admission and flow control algorithms, fault tolerance, reconfiguration techniques, embedding and mapping problems, broadcasting and multicasting, quality of service, multiaccess communication. COORDINATORS ------------ o Evangelos Kranakis, kranakis@scs.carleton.ca School of Computer Science, Carleton University, Ottawa Ontario K1S 5B6 o Danny Krizanc, krizanc@scs.carleton.ca School of Computer Science, Carleton University, Ottawa Ontario K1S 5B6 _______________________________________________________________________ MINITRACK-10: PERFORMANCE EVALUATION OF DISTRIBUTED SYSTEMS ----------------------------------------------------------- Distributed application and system modeling, interconnection network analysis, trace file analysis techniques, network of workstation environments, process migration, performance prediction techniques and tools, evaluating and standardizing benchmarks, benchmarking experiences. COORDINATORS ------------ o Mark J. Clement, clement@cs.byu.edu Dept. of Computer Science, Brigham Young University, 3372 TMCB, Provo, Utah 84602-6576 o Xian-He Sun, sun@bit.csc.lsu.edu Dept. of Computer Science, Louisiana State University, Baton Rouge, LA 70803-4020 _______________________________________________________________________ MINITRACK-11 VIRTUAL SHARED MEMORY FOR DISTRIBUTED ARCHITECTURES ----------------------------------------------------------------- Software tools offering virtually shared data objects, replication protocols and optimized caching techniques, distributed garbage collection, software supported fault tolerance, performance and scalability issues, naming issues, advanced programming techniques (blackboard versus message passing communication), limitations of client/server based technologies. COORDINATOR ----------- o eva Kuehn, eva@complang.tuwien.ac.at University of Technology Vienna, Institute of Computer Languages A-1040 Wien, Argentinierstr. 8, AUSTRIA _______________________________________________________________________ MINITRACK-12: WEB COMPUTING IN THEORY AND PRACTICE -------------------------------------------------- Development methodologies and run-time support for Web-oriented collaboration, practical application examples, parallelism within Web computing, Web-oriented operating systems, Web-enabled languages and tools, Web-oriented protocols, security in Web-based applications. COORDINATOR ----------- o Nikola Serbedzija, nikola@first.gmd.de GMD FIRST, Rudower Chaussee 5, D-12489 Berlin, GERMANY _______________________________________________________________________ MINITRACK-13: WIRELESS NETWORKS AND MOBILE COMPUTING ---------------------------------------------------- Data management, performance evaluation of mobile/wireless networks and systems, network layer routing protocols, security issues, scalability and reliability, intermittent connectivity, service integration and inter-networking of wired and wireless networks transaction management issues, tracking and addressing issues for mobile hosts, applications. COORDINATORS ------------ o Stephan Olariu, olariu@cs.odu.edu Dept. of Computer Science, Old Dominion University, Norfolk, VA 23529-0162 o Omran Bukhres, bukhres@cs.iupui.edu Dept. of Computer Science, Purdue University, 723 W. Michigan Ave. SL280, Indianapolis, IN 46202-5132 _______________________________________________________________________ MINITRACK-14: WORKFLOW SYSTEMS ------------------------------ Workflow concepts and products, workflow and business process modeling, user interaction in workflow management systems, networking and database support for workflow systems, inter- and intra-organizational workflow, workflow for global collaboration, recovery and fault tolerance issues. COORDINATORS ------------ o Gabriele Kotsis, gabi@ani.univie.ac.at Dept. of Applied Computer Sc. and Info. Systems, University of Vienna, Lanaugasse 2/8, A-1080 Vienna, AUSTRIA o Christine Strauss, strauss@pom.bwl.univie.ac.at Dept. of Business Administration and Management, University of Vienna, Bruenner Strasse 72, A - 1210 Vienna, AUSTRIA _______________________________________________________________________ End _______________________________________________________________________ Looking forward to your kind feedback. Best regards, Reiner Hartenstein ================================================================= Prof. Dr.-Ing. Reiner W. Hartenstein, Universitaet Kaiserslautern Informatik (CS&E) Bau 12 phone: +49 631 205-2606, fax: -2640 Postfach 3049 http://xputers.informatik.uni-kl.de D-67653 Kaiserslautern, Germany | e-mail: hartenst@rhrk.uni-kl.de HOME: Postf.1744, D-76607 Bruchsal,Germany | Fax: +49 7251 14823 ..._/ _/ _/_/_/ _/ _/ _/_/_/ _/_/_/ _/_/_/ _/_/ ....._/ ..._/_/ _/ _/ _/ _/ _/ _/ _/ _/ _/ ......._/_/ ..._/ _/_/_/ _/ _/ _/ _/_/_/ _/_/_/ _/_/ ._/_/_/_/_/ ._/_/ _/ _/ _/ _/ _/ _/ _/ _/ ...._/_/ _/ _/ _/ _/_/ _/ _/_/_/ _/ _/ _/_/ ....._/ From codesign-request@ifi.unizh.ch Thu Feb 20 14:28:12 1997 Return-Path: Received: from pol88b.polito.it by josef.ifi.unizh.ch with SMTP (PP) id <23992-0@josef.ifi.unizh.ch>; Thu, 20 Feb 1997 14:28:03 +0100 Received: from chiusella.polito.it.polito.it (chiusella.polito.it) by polito.it (PMDF V4.2-15 #3020) id <01IFMZ2SDD1SHSMCN0@polito.it>; Thu, 20 Feb 1997 11:47:53 GMT+1 Received: by chiusella.polito.it.polito.it (4.1/SMI-4.1) id AA11368; Thu, 20 Feb 97 11:47:42 +0100 Date: Thu, 20 Feb 1997 11:47:42 +0100 From: prinetto@chiusella.polito.it (Paolo Prinetto) Subject: 3rd IEEE International On-Line Testing Workshop - Call for Participation To: codesign@ifi.unizh.ch Message-id: <9702201047.AA11368@chiusella.polito.it.polito.it> X-Envelope-to: codesign@ifi.unizh.ch Content-transfer-encoding: 7BIT Apparently-To: codesign@ifi.unizh.ch Status: RO X-Status: Call for Participation 3rd IEEE International On-Line Testing Workshop Sofitel Capsis Beach Resort, Aghia Pelaghia headland, Crete, Greece July 7-9, 1997 ____________________________________________________________ The increased complexity of electronic systems has seen increasing reliability needs in various application domains as well as pressure for low cost products. There is a corresponding increased demand for cost-effective on-line test techniques. This workshop provides an informal forum to discuss all aspects of on-line testing. The Workshop is sponsored by the IEEE Computer Society Test Technology Technical Committee, co-organized by TTTC On-line Testing Technical Activity Committee, the European Group of the Test Technology Technical Committee (ETTTC), and NCSR Demokritos. The topics include (but are not limited to) the following ones: * Concurrent checking * Periodic testing in the field * Field diagnosis * Self-checking digital, analog and mixed-signal circuits * Coding theory * On-line and off-line BIST * Synthesis of on-line testable circuits * Radiation hardened/tolerant processes and design techniques * Sensors/detectors for on-line monitoring of current, temperature and other reliability relevant parameters * Fault-tolerant and fail-safe systems * On-line testing in automotive, railway, avionics, industrial control and space applications To encourage and facilitate informal discussion mandates that participation be limited. Those interested in presenting recent results at the workshop submit three copies of an extended abstract, one to three pages long, or full length paper to the Co-Program Chair D. Nikolos. Please observe the following deadlines: - submission deadline: March 3rd, 1997 - notification of acceptance: April 15th, 1997 Submit proposals to: General Information: Dimitris Nikolos Antonis Paschalis Michael Nicolaidis Dept. Comp. Eng. & NCSR "Demokritos" Reliable Int. Systems Group Informatics Aghia Paraskevi TIMA University of Patras 153 10, Athens 46 Av. Felix Viallet 26500 Patras, Greece Greece 38031 Grenoble, France Tel : +30 61 997-752 Tel: +30 1 65 20 847 Tel: +33 4 76 57 46 19 Fax : +30 61 991-909 Fax: +30 1 65 32 175 Fax: +33 4 76 47 38 14 nikolosd@cti.gr paschali@iit.nrcps. michael.nicolaidis@imag.fr ariadne-t.gr Web Site: HTTP://tima-cmp.imag.fr/tima/ris/ioltw.html US participants may contact Dhiraj Pradhan : Tel: +1 409 862 2438 - Fax: +1 409 862 2758 - E-mail: pradhan@cs.tamu.edu, for any additional information. Organisation Committee General Chairs Program Chairs M. Nicolaidis, TIMA D. Nikolos, U. Patras A. Paschalis, NCSR Demokritos D. Pradhan, Texas A&M U. Vice-General Chair Y. Zorian, LogicVision Local Arrangements Publications N. Gaitanis, NCSR Demokritos G. Alexiou, U. Patras Publicity Finance D. Gizopoulos, NCSR Demokritos P. Kostarakis, NCSR Demokritos ETTTC Liaison C. Landrault, LIRMM Program Committee J. A. Abraham, U. of Texas C. Lau, ONR M. Abramovici, Lucent Technologies H. Levendel, Lucent Technologies L. Alkalai, JPL/Caltech R. Leveugle, CSI/INPG E. Boehl, Robert Bosch GmbH J.C. Lo, Rhode Island U. S. Bracho, U. of Cantabria P. Marchal, CSEM SA T. Calin, TIMA C. Metra, U. Bologna K. T. Cheng, UCSB E.J. McCluskey, Stanford U. W. Debaney, Rome Lab. RL/ERDA T. Nanya, Tokyo Inst. of Techn. C. Dufaza, LIRMM A. Orailoglu, U. CA, San Diego R. O. Duarte, TIMA S. Piestrak, Tech. U. of Wroclaw J. Figueras, U. P. de Catalunya P. Prinetto, Politecnico di Torino W.K. Fuchs, Purdue Univ. A.D. Singh, Auburn U. M. Goessel, Max-Plank Society E.S. Sogomonyan, Rus. A. of Sc. J.P. Hayes, U. Michigan J. Stiffler, Sequoia Systems S. Hellebrand, U. Siegen V. Szekely, TU Budapest A. Ivanov, U. of Brit. Columbia F. Vargas, U. Catolique B. Kaminska, Ecole Pol. Montreal R. Velazco, LGI/INPG N. Kanopoulos, DCT T. Williams, IBM K. Kuchukian, Armenian NAS H.J. Wunderlich , U. Stuttgart P.K. Lala, N. Carolina A&T State U. _____________________________________________________________ About the location: Sofitel Capsis Beach Resort, is located at the Aghia Pelaghia headland, 12 miles from International Heraklion Airport, in Crete, the largest island of Greece. Crete has a 4,000 years old history, with the Minoan civilazation its crowning achievement. The palaces of Knossos and Phaestos were the royal residences as well as the administrative and religious centres of the region. The frescos, ceramics, and golden pieces found during excavations bring us to the soul of that world, peace-loving, light-hearted, but also powerful. Crete has a mild, sub-tropical climate, pleasant breezes and a constantly changing scenery among miles of beaches mountain chains, plateaus, valleys and deep gorges. IEEE COMPUTER SOCIETY Test Technology Technical Committee From eapls-request@mailbase.ac.uk Mon Mar 3 15:04:40 1997 Return-Path: Received: from naga.mailbase.ac.uk by josef.ifi.unizh.ch with SMTP (PP) id <13884-0@josef.ifi.unizh.ch>; Mon, 3 Mar 1997 15:04:25 +0100 Received: by naga.mailbase.ac.uk id (8.7.x for naga.mailbase.ac.uk); Mon, 3 Mar 1997 13:01:38 GMT Received: from MATHCT.DIPMAT.UNICT.IT by naga.mailbase.ac.uk id (8.7.x for naga.mailbase.ac.uk) with SMTP; Mon, 3 Mar 1997 13:01:04 GMT Date: Mon, 3 Mar 1997 12:45:44 +0100 (CET) From: LIPARI SCHOOL To: iclp-publicity@quintus.com, tapsoft@dcs.ed.ac.uk, PetriNets@daimi.aau.dk, concurrency@cwi.nl, types@dcs.gla.ac.uk, amast-info@cs.utwente.nl, "eatcsit eatcs-it"@cs.unibo.it, gulp@di.unipi.it X-Vmsmail-To: @MAILING_NONA.DIS Message-Id: <970303124544.d12@dipmat.unict.it> Subject: Lipari 97 X-List: eapls@mailbase.ac.uk X-Unsub: To leave, send text 'leave eapls' to mailbase@mailbase.ac.uk Reply-To: LIPARI SCHOOL Sender: eapls-request@mailbase.ac.uk Precedence: list Status: RO X-Status: Ninth International School for Computer Science Researchers "Architecture Design and Validation Methods" Lipari Island, 22 June - 5 July 1997 (http://www.unict.it/lipari/home.html) The Ninth School for Computer Science Researchers addresses PhD students and young researchers who want to get exposed to the forefront of research activity in the field of "Architecture Design and Validation Methods". The school will be held in the beautiful surroundings of the Island of Lipari which can be reached by ferry from Naples, Milazzo, Messina, Reggio Calabria and Palermo. The official language is English. Students must follow six courses and choose three of them for the exam. A proficiency final exam at the end of each chosen course is mandatory. Saturday of the first week will be entirely dedicated to open research problems and discussion. A letter of application must be sent to Prof. Alfredo Ferro (address below) and must be received by April 20, 1997. The application should contain a c.v. plus at least two letters of recommendation but no papers. Students will be informed about acceptance by April 30, 1997.The registration fee for the school is 300 U.S. dollars per person. American students of the EAACSS consortium will be excused from payment of registration fees . COURSES: - Raul Camposano, Synopsys Inc. "High Level Design" - Giovanni De Micheli, Stanford University "Logic Synthesis and Optimization" - Hans Eveking, Darmstadt University "Machine Assisted Verification" - Zohar Manna and Egon Boerger, Stanford/Pisa University "Validation Methods" -Ralph Otten, Delft University "Layout design" - Alberto San Giovanni Vincentelli, UC Berkeley "Hw/Sw Co-Design" Directors: Alfredo Ferro Egon Boerger Department of Mathematics Department of ComputerScience University of Catania University of Pisa Prof. Alfredo Ferro Dipartimento di Matematica-Citta' Universitaria Viale A. Doria, 6 - 95125 CATANIA - ITALY Tel. +39-95-221012 / 330533 (ext. 666) Fax: +39-95-330094 e-mail: SCHOOL@DIPMAT.UNICT.IT Under the auspices of E.A.A.C.S.S - European American Advanced Computer Science Schools consortium E.A.C.S.L. - European Association for Computer Science Logic A.I.L.A - Associazione Italiana Logica ed Applicazioni From codesign-request@ifi.unizh.ch Mon Mar 3 15:43:29 1997 Return-Path: Received: from bikini.ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <12383-0@josef.ifi.unizh.ch>; Mon, 3 Mar 1997 14:13:25 +0100 Return-Path: X-Received: from mail.ele.kth.se by josef.ifi.unizh.ch with SMTP (PP) id <22324-0@josef.ifi.unizh.ch>; Fri, 28 Feb 1997 11:44:12 +0100 X-Received: from brimer.ele.kth.se (brimer.ele.kth.se [130.237.20.10]) by mail.ele.kth.se (8.8.5/8.8.5) with ESMTP id LAA10813 for ; Fri, 28 Feb 1997 11:43:26 +0100 (MET) From: Fredrik Ostman X-Received: from aud.ele.kth.se (aud.ele.kth.se [130.237.20.172]) by brimer.ele.kth.se (8.8.5/8.7.5) with ESMTP id LAA24367 for ; Fri, 28 Feb 1997 11:43:24 +0100 (MET) X-Received: (fredrik@localhost) by aud.ele.kth.se (SMI-8.6/8.6.9) id LAA29877 for codesign-request@ifi.unizh.ch; Fri, 28 Feb 1997 11:43:56 +0100 Date: Fri, 28 Feb 1997 11:43:56 +0100 Message-Id: <199702281043.LAA29877@aud.ele.kth.se> To: codesign-request@ifi.unizh.ch Subject: State of the Art Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-MD5: aeunXsvPTUA4VUGENhsMuw== ReSent-Date: Mon, 3 Mar 1997 14:13:09 +0100 (MET) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Message-ID: Status: RO X-Status: Co-design Gurus, Co-design is slowly making its way into practical use in the manufacturing industries. Driving forces are market maturity, forcing manufacturers to customization and feature focus to satisfy customers, technological maturity with a continuous range of technologies from ultra soft Java applets to ultra high-speed optical tranceivers, making the speed/flexibility trade-off ever more important and difficult. The mere size of modern chips means chip-based systems must be more flexible (programmable) than before to be designable and sellable at all. Availability of commercial codesign tools is also a factor in the practical application of codesign. What has happened since codesign started to gain attention, e.g. since the first WS in Grassau 1992? What approaches have made it to practical use? Which are the dark horses? What approaches met unexpected obstacles? What kind of interests have manufacturers and tools vendors shown the codesign community? What kind of jobs did codesign PhDs get? Did they stay in the universities, did they get unrelated jobs in the industry, or are they actually doing commercial codesign? I welcome discussion, off-line or on the list, and also pointers to recent literature and reports on these issues. What is the state of the art of codesign? ______ _~ (_/_ _ _ _/) _ . /) / ) , _/) _ __/ _/(_(/_(/__/(_/_/Z_ (_/_/)_/__/))_(I_/)_ Fredrik :Ostman Electronic System Design Laboratory, Royal Institute of Technology Electrum 229, S-164 40 KISTA, Sweden +46 (8) 727 1318 fax +46 (8) 727 1240 fredrik@ele.kth.se = http://www.ele.kth.se/~fredrik From codesign-request@ifi.unizh.ch Thu Apr 17 17:40:22 1997 Return-Path: Received: from clavin.cs.tamu.edu by josef.ifi.unizh.ch with SMTP (PP) id <26409-0@josef.ifi.unizh.ch>; Thu, 17 Apr 1997 17:40:09 +0200 Received: from chipmonks.cs.tamu.edu (233@chipmonks.cs.tamu.edu [128.194.146.168]) by cs.tamu.edu (8.8.4/8.8.4) with ESMTP id KAA26691 for ; Thu, 17 Apr 1997 10:40:06 -0500 (CDT) From: Fabrizio Lombardi Received: (from lombardi@localhost) by chipmonks.cs.tamu.edu (8.8.5/8.8.5) id KAA16457 for codesign@ifi.unizh.ch; Thu, 17 Apr 1997 10:38:23 -0500 (CDT) Date: Thu, 17 Apr 1997 10:38:23 -0500 (CDT) Subject: CFP: FPGA - IEEE Design and Test of Computers Message-Id: <199704171538.KAA16457@chipmonks.cs.tamu.edu> To: codesign@ifi.unizh.ch Status: RO X-Status: Call For Papers: FPGA IEEE Design and Test of Computers Special Issue Spring 1998, Volume 15, Number 1 Web Page: http://www.cs.tamu.edu/faculty/lombardi/datsi.htm IEEE Design and Test of Computers seeks original manuscripts for a theme issue on Field Programmable Gate Arrays (FPGAs) scheduled to appear in the first issue of 1998. Articles concerning applied research and practical experience reports are solicited. The topics of interest include, but are not limited to: FPGA Fabrication and Technology. Manufacturing, process control, yield enhancement, and novel architectures for and device technology to support field programmable chips. Exploitation of Field Programmability. Configurable computer architectures, rapid prototyping, programmable interconnect architectures, field configurable memories, programmable I/O systems, and novel implementations. Reliable Online Implementations. Online testing, built-in self-test, concurrent testing, design for rapid testability, latency reduction, fault containment, verification of reprogramming, online reconfiguration approaches, and design for reconfigurability. Synthesis Approaches and Tools. Partitioning, logic minimization and technology mapping, placement and routing, test generation, verification of synthesis, and design for synthesizability. Submitted articles must not have been previously published or currently submitted for publication elsewhere. Authors should submit their original work to the guest editor by May 1, 1997, formatted according to the instructions below. Notification of acceptance will be sent September 1, 1997. Camera-ready copy for accepted papers will be due November 1, 1997. Submit articles by May 1, 1997 to: Prof. Fabrizio Lombardi, Guest Editor Department of Computer Science Phone: (409) 845--5464 Texas A & M University Fax: (409) 847--8578 College Station TX 77843-3112 E-Mail: lombardi@cs.tamu.edu Important dates: May 1, 1997: Submission deadline September 1, 1997: Authors notified of acceptance with requested revisions November 1, 1997: Final copy due to Design & Test Managing Editor Spring 1998: Publication in IEEE Design and Test of Computers Submission requirements: Send six (6) copies of the manuscript, in English, to the guest editor. Manuscripts are not to exceed 35 double-spaced pages, inclusive of figures and tables, in A4 or 8.5 by 11 inches. Type size must be at least 12 point. Each copy of the manuscript must contain a cover page with author contact information (name, postal address, telephone number, and e-mail address) and a 100-word abstract. Manuscripts must be cleared for publication. Accepted manuscripts will be edited for technical content, structure, style, clarity, and grammar. Detailed information for authors can be found at the Computer Society D&T website at http://www.computer.org/pubs/d&t/d&t.htm or in the Spring 1996 issue of Design & Test. From codesign-request@ifi.unizh.ch Fri Apr 18 14:21:29 1997 Return-Path: Received: from clavin.cs.tamu.edu by josef.ifi.unizh.ch with SMTP (PP) id <26418-0@josef.ifi.unizh.ch>; Thu, 17 Apr 1997 17:41:12 +0200 Received: from chipmonks.cs.tamu.edu (233@chipmonks.cs.tamu.edu [128.194.146.168]) by cs.tamu.edu (8.8.4/8.8.4) with ESMTP id KAA26700 for ; Thu, 17 Apr 1997 10:40:23 -0500 (CDT) From: Fabrizio Lombardi Received: (from lombardi@localhost) by chipmonks.cs.tamu.edu (8.8.5/8.8.5) id KAA16466 for codesign@ifi.unizh.ch; Thu, 17 Apr 1997 10:38:43 -0500 (CDT) Date: Thu, 17 Apr 1997 10:38:43 -0500 (CDT) Message-Id: <199704171538.KAA16466@chipmonks.cs.tamu.edu> Subject: 1997 IEEE MTDT Workshop To: codesign@ifi.unizh.ch Status: RO X-Status: ************************************************************************ 1997 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN AND TESTING (MTDT) ************************************************************************ PRELIMINARY TECHNICAL PROGRAM & REGISTRATION FORMS ************************************************************************ August 11-12, 1997 Hilton Hotel And Towers 300 Almaden Blvd, San Jose, California, USA Tel: (408)-287--2100 ************************************************************************ INTRODUCTION TO MTDT 97 You are invited to participate in the 1997 IEEE International Workshop on Memory Technology, Design and Testing. This electronic document includes up-to-date information about the Workshop (Technical Program, Travel Information, etc). Also, please find attached the WORKSHOP REGISTRATION FORM and HOTEL INFORMATION. After filling out the registration form please mail or fax it to guarantee your participation. MTDT 97 is the latest meeting in a series that explores all aspects of memory design, process technologies and testability related topics, such as memory circuit designs, cell structures, fabrication processes, design architectures. The two-day technical program includes 16 paper presentations, one panel session and a keynote address. The paper sessions span many of the key areas in design, test, and technology. Also on the program are sessions on emerging areas that are gaining prominence, such as low power, tools and sensing. We hope that you will find MTDT 97 interesting, thought-provoking, and rewarding. Fabrizio Lombardi General Chair E: lombardi@cs.tamu.edu Thomas Wik Technical Program Chair E: trw@lsil.com Sponsored by: IEEE Computer Society Technical Committee on Test Technology Technical Committee on VLSI In cooperation with: IEEE Solid-State Circuit Society ------------------------------------------------------------------------ 1997 WORKSHOP ON MTDT GENERAL INFORMATION ------------------------------------------------------------------------ All activities require a registration badge for admittance. All participants must pay the appropriate fees. Reduced fees are available to IEEE or Computer Society members on presentation of a valid member number. To register, use the Symposium Registration Form attached to this file. To receive early registration discount rates, your completed Registration Form must be RECEIVED by mail or fax by July 31, 1997. After July 31, register at the higher rates listed in the table below. Technical program registration includes a copy of the Proceedings, (published by IEEE CS Press), the banquet, luncheons and coffee breaks. Lunch and banquet tickets for companions of registered attendees will be available at the registration desk. Extra copies of the Proceedings will be also available at $30 each. REGISTRATION FEES: Early Registration* WORKSHOP IEEE/CS Member $270 Non-members $345 Registration at Hotel WORKSHOP IEEE/CS Member $325 Non-members $400 * discounts available until July 31, 1997 REFUNDS: If you must cancel, advance registration fees will be refunded only upon written request to the Finance Chair postmarked on or before July 15, 1997. A $100 processing fee is charged for each refund. ======================================================================== 1997 WORKSHOP ON MTDT TECHNICAL PROGRAM Monday, August 11th, 1997 ------------------------- 7:30 - 9:00 am Registration ------------------------------------------------------------------------ 9:00 -10:30am PLENARY SESSION WELCOME MESSAGE: F. Lombardi, General Chair KEYNOTE ADDRESS: Matching Memory to the Power of Personal Computers, Richard Foss, MOSAID Technologies Inc., Canada. PROGRAM INTRODUCTION: T. Wik, Program Chair ------------------------------------------------------------------------ 10:30 - 11:00 am BREAK ------------------------------------------------------------------------ 11:00 am - 12:00 pm SESSION 1: ARCHITECTURES. A Low-Cost, High Performance Three-Dimensional Memory Module, A. Glaser, P. Franzon, (North Carolina State University, USA), G. Rinnie, V. Rogers and C. K. Williams (MCNC, USA). High Speed Circuit Techniques in a 150MHz 64M SDRAM, V. Lines, M. Abu-Seido, C. Mar, A. Achyuthan, (MOSAID Technologies Inc., Canada), S. Miyamoto, Y. Murashima and S. Sakuma (OKI Elect. Co., Japan). ------------------------------------------------------------------------ 12:00 - 1:30 pm LUNCH ------------------------------------------------------------------------ 1:30-3:30 pm SESSION 2: FAULT MODELING AND MANUFACTURING. An Analysis of (Linked) Addressed Decoder Faults, A. J. van de Goor and G. N. Gaydadjiev, (Delft University of Technology, The Netherlands). SRAM Yield Estimation in the Early Design Stage, V. Kim and T. Chen, (Colorado State Univeristy, USA). False Write Through and Un-Restored Write Electrical Level Fault Models for SRAMs, R. D. Adams and E. S. Cooley, (Dartmouth College, USA). A Defect-Tolerant DRAM Employing A Hierarchical Redundancy Scheme, Built-In Self-Test and Self-Reconfiguration, D. Niggemeyer, J. Otterstedt and M. Redeker, (Universitat Hannover, Germany). ------------------------------------------------------------------------ 3:30 - 4:00 pm BREAK ------------------------------------------------------------------------ 4:00 - 5:00 pm SESSION 3: TOOLS. Formal Verification of Memory Arrays Using Symbolic Trajectory Evaluation, M. Pandey and R. E. Bryant, (Carnegie Mellon University, USA). A Product Development Flow with Metrics for Memory Designs, S. Hegde, I. P. Pal and K. S. Rao, (Texas Instruments, India). -------------------------------------------------------------------------- 1997 WORKSHOP ON MTDT TECHNICAL PROGRAM Tuesday, August 12, 1997 ------------------------ -------------------------------------------------------------------------- 9:00 - 10:00 am SESSION 4: LOW POWER. A Low-Power High Storage Capacity Structure for GaAs MESFET ROM, R. Kanan, B. Hochet, M. Declercq (Swiss Federal Institute of Technology) and A. Guyot (INPG-TIMA, France). Use of Selective Precharge for Low-Power on the Match Lines of Content-Addressable Memories, C. Zukowski and S.-Y. Wang, (Columbia University, USA). ------------------------------------------------------------------------- 10:00 - 10:30 am BREAK ------------------------------------------------------------------------- 10:30 - 12:00 pm PANEL\TUTORIAL ON DRAMs (organized by T. Wik, LSI Logic, USA). -------------------------------------------------------------------------- 12:00 - 1:30 pm LUNCH -------------------------------------------------------------------------- 1:30 - 3:30 pm SESSION 5: TEST. March 3N and March 4N Memory Tests, V. Yarmolik (Belarusian State University), Y. Klimets (Academy of Sciences, Belarus) and S. Demidenko (Singapore Polytechnic). An Open Notation for Memory Tests, A. Offerman and A. J. van de Goor, (Delft University of Technology, The Netherlands). Testing Memory Modules in SRAM-Based Configurable FPGAs, W. K. Huang, F. J. Meyer, N. Park and F. Lombardi, (Texas A&M University, USA). Memory Array Testing Through a Scannable Configuration, S.Yano (NEC Corporation, Japan) and N. Ishiura (Osaka University, Japan). -------------------------------------------------------------------------- 3:30 - 4:00 pm BREAK ------------------------------------------------------------------------- 4:00 - 5:00 pm SESSION 6: SENSING. A High-Speed Parallel Sensing Scheme for Multi-Level Non-Volatile Memories, C. Calligaro, A. Manstretta, G. Torelli, (University of Pavia, Italy) and R. Gastaldi (SGS Thomson,Italy). Differential Built-in Current Sensor (BICS) for Static RAMs: Implementation and Performance, S. M. Menon A. Nymoen (South Dakota School of Mines & Technology, USA). -------------------------------------------------------------------------- 5:00 pm CLOSING REMARKS -------------------------------------------------------------------------- WORKSHOP ORGANIZATION TECHNICAL PROGRAM CHAIR Thomas Wik LSI Logic, MS E-194 1501 McCarthy Blvd Milpitas CA 95035, USA 408/954-4471; trw@lsil.com GENERAL CHAIR Fabrizio Lombardi Computer Science MS 3112 Texas A&M University College Station TX 77843, USA 409/845-5464; fax 847-8578 lombardi@cs.tamu.edu PUBLICITY CHAIR Fred "Jackie" Meyer Computer Science MS 3112 Texas A&M University College Station TX 77843, USA 409/845-1014; fmeyer@cs.tamu.edu FINANCE CHAIR Duncan "Hank" Walker Computer Science MS 3112 Texas A&M University College Station TX 77843, USA 409/862-4387; fax 847-8578 walker@cs.tamu.edu STEERING COMMITTEE Rochit Rajsuman, Chair Equator Technologies, Inc. (408) 260-0599, ext. 337 rajsuman@equator.com Bernard Courtois, INPG/TIMA Grenoble, France Ad J. van de Goor, Delft University of Technology, The Netherlands Yervant Zorian, Logic Vision, Princeton NJ, USA PROGRAM COMMITTEE Abhaya Asthana, Lucent Technologies, Princeton NJ, USA Bruce Cockburn, University of Alberta, Edmonton AB, Canada Mike DePaolis, Lucent Technologies, Princeton NJ, USA Bob Evans, MosAid, San Jose CA, USA E. Fujiwara, Tokyo Institute of Technology, Tokyo, Japan Susanne Griep, Siemens AG, Munchen, Germany S. Horiguchi, Japan Advanced Institute of Science and Technology, Tatsunokuchi, Japan Swee Yong Khim, Texas Instruments, Singapore David Lepejian, HPL, Milpitas CA, USA Yashwant Malaiya, Colorado State University, USA P. Olivo, University of Bologna, Bologna, Italy Ritu Shrivastava, Alliance Semiconductor, San Jose CA, USA ======================================================================== 1997 WORKSHOP ON MTDT **** EARLY REGISTRATION DISCOUNT FORM **** MAIL or FAX form to: Dr. D. H. Walker Finance Chair 1997 W-MTDT Department of Computer Science Texas A&M University College Station TX 77843 USA Tel: (409) 862-4387 Fax: (409) 847-8578 Email: walker@cs.tamu.edu IMPORTANT: Read GENERAL INFORMATION, above, before completing this form. After July 31, register at the Workshop. (Registration-at-Hotel rates will apply.) First Name:____________________________________________ Last Name:_____________________________________________ Company:_______________________________________________ Mail Stop:_____________________________________________ St. Address/Box No.:___________________________________ City:_____________________________ State (US):_________ Zip Code (US):_____________ Country:___________________ Tel:_______________________Fax:________________________ E-mail:____________________IEEE Mmbr No.*:_____________ SPECIAL DIETARY REQUIREMENT: Vegetarian______ Other (specify)_______________________________ DISCOUNT REGISTRATION (available until July 31) TECHNICAL PROGRAM August 11-12 IEEE/CS Member* $270 _____ Non-Member $345 _____ ADDITIONAL Copies of MTDT 97 Proceedings pick up at symposium. Quan.___ @ $30 _____ TOTAL: $_______ * - IEEE/CS member rates are granted only if your current valid member number is filled in above. SEND FULL PAYMENT IN US$ WITH THIS FORM. Use a check drawn on a US bank, or a US bank credit card. PURCHASE ORDERS ARE NOT ACCEPTED. Make checks payable to: 1997 IEEE WORKSHOP ON MTDT. USE YOUR CREDIT CARD IF REGISTERING BY FAX. FOR CREDIT CARD PAYMENT: Check card type: VISA/MASTERCARD____________ AMERICAN EXPRESS___________ CARD NO.:_____________________ Exp. Date:______________ CARDHOLDER SIGNATURE:__________________________________ Advance registration fees will be refunded only on written request, mailed or fax'ed, and received by July 15, 1997. A $100 processing fee is charged for each refund. =========================================================== HOTEL ACCOMMODATION San Jose Hilton Hotel and Tower is located in Down Town San Jose. The Hotel provides courtesy shuttle from San Jose International Airport. HOTEL ADDRESS: 300 Almaden Blvd San Jose, CA 95110 Tel: (408) 287-2100, Fax: (408) 947-4488 Toll Free: 1-800-445-8667 RATES: Singe $125, Double $125 ($15 extra person) Towers Room $25 extra Suite $295 to $650 Participants should reserve the room directly with the hotel using the above numbers. The above discount rates are guaranteed if reservations are made before July 10, 1997. At the time of reservation, the name of the workshop (MTDT-97) must be identified. =========================================================== From codesign-request@ifi.unizh.ch Mon Apr 21 16:26:29 1997 Return-Path: Received: from ms-gw.iee.org.uk by josef.ifi.unizh.ch with SMTP (PP) id <26553-0@josef.ifi.unizh.ch>; Mon, 21 Apr 1997 16:26:07 +0200 From: mswift@iee.org.uk Date: Mon, 21 Apr 1997 15:19:10 +0000 To: codesign@ifi.unizh.ch Subject: Hardware/software co-design MIME-version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-transfer-encoding: quoted-printable X-Mailer: TFS Gateway /222000000/222041186/222002222/222100421/ Message-ID: <"josef.ifi..566:21.03.97.14.26.27"@ifi.unizh.ch> Status: RO X-Status: A Dear Sir, As you may already be aware the Institution of Electrical Engineers is organising the above Vacation School on 13-16 July 1997. I have been given your email address by my Chairman Dr T York, who had been= informed we can obtain an apropriate mailing list from yourself. Please send me details as soon as possible Thanks Michelle Swift Groups Officer Computing and Control Division IEE Divisional Services From codesign-request@ifi.unizh.ch Tue Apr 22 15:46:44 1997 Return-Path: Received: from ms-gw.iee.org.uk by josef.ifi.unizh.ch with SMTP (PP) id <20785-0@josef.ifi.unizh.ch>; Tue, 22 Apr 1997 15:46:21 +0200 From: mswift@iee.org.uk Date: Tue, 22 Apr 1997 14:44:20 +0000 To: codesign@ifi.unizh.ch Subject: Hardware software Co-design MIME-version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-transfer-encoding: quoted-printable X-Mailer: TFS Gateway /222000000/222041186/222002222/222100421/ Message-ID: <"josef.ifi..798:22.03.97.13.46.42"@ifi.unizh.ch> Status: RO X-Status: Dear All, Please find below details for the above mentioned Vacation school. VACATION SCHOOL ON HARDWARE-SOFTWARE CO-DESIGN 13-16 JULY 1997 Professional Group C2 (Hardware and systems engineering) is organising a Vacation School on =95Hardware-software co-design=96 to be held at The Manchester Conference Centre from 14-16 July 1997. The aim of the School is to introduce the concepts, key issues and achievements of hardware-software co-design through a series of lectures, case studies and hands-on demonstrations. Hardware-software co-design seeks to remove the distinction between the two regimes from high level systems design. This is achieved with the help of sophisticated tools which, from a single system specification, will optimise the partitioning of designs to satisfy a number of constraints. Over the past 2 years Professional Group C2 have organised the following 3 excellent Colloquia on co-design under the direction of Dr. Richard Taylor (Hewlett Packard Research Laboratories): 'Partitioning in hardware-software co-designs', 'Verification of hardware-software co-designs' and 'Hardware-software cosynthesis for reconfigurable systems'. Following the recent emergence of first generation systems from the research laboratory a Vacation School on =93co-design=94 is now particularly timely. Introductory lectures will provide an overview of the state-of-the-art technology within the field. The potential economic and performance benefits that may be available through the use of hardware-software co-design, and the key areas of specification, partitioning and simulation will also be addressed during the School. The Vacation School is appropriate for practising engineers, from an industrial or academic background, who have a basic understanding of digital electronics, software and computer engineering. Suitable attendees would be aware of, but not necessarily familiar with, co-design and would like to assess the potential for their own applications. This is a relatively new field with information emerging from a variety of sources. Few courses are available at institutes of higher education and therefore, at present, those with a latent interest must spend considerable time accessing and filtering information for themselves. The primary objective of the School is to provide delegates with vital knowledge that will enable them to efficiently evaluate the potential of hardware-software co-design for their own needs. For further programme and registration details please complete and return the slip below or email: colloquia@iee.org.uk * * * * * * * * * * * Vacation School on Name "Hardware-software co-design=96 Address The Manchester Conference Centre 14-16 July 1997 Please send me ....... copies of the programme and registration form From codesign-request@ifi.unizh.ch Wed Apr 30 09:34:40 1997 Return-Path: Received: from 193.96.24.3 by josef.ifi.unizh.ch with SMTP (PP) id <24433-0@josef.ifi.unizh.ch>; Wed, 30 Apr 1997 09:33:55 +0200 Received: by mail.DBresearch-berlin.de (/\==/\ Smail3.1.28.1) from DBresearch-berlin.de with smtp id ; Wed, 30 Apr 97 09:32 MET DST Received: (vhanx@localhost) by DBresearch-berlin.de (SMI-8.6/8.6.9) id JAA09826; Wed, 30 Apr 1997 09:32:49 +0200 Date: Wed, 30 Apr 1997 09:32:49 +0200 From: vhanx Message-Id: <199704300732.JAA09826@DBresearch-berlin.de> To: codesign@ifi.unizh.ch Subject: CFP - EMMSEC 97 Reply-to: vhanx@dbresearch-berlin.de Status: RO X-Status: ########################################################################## # # # EMMSEC 97 # # European Multimedia, Microprocessor Systems and Electronic Commerce # # Conference and Exhibition # # Florence, Italy # # 3-5 November 1997 # # # ########################################################################## Call for Papers and Exhibition Theme: New technology - new business The scope and emphasis of the seventh annual conference on embedded systems have been adjusted to reflect the wider use of microprocessors and their increasing economic importance. The programme now covers the three areas of microprocessors, multimedia and electronic commerce and the content will be emphasising how these new technologies can generate business ideas and opportunities. As usual there will be several parallel streams, an exhibition and social events including a partners' programme. The conference language is English and abstracts may be for technical papers, issue papers, workshop sessions or panel discussions. Topics can include, but are not restricted to, the following: Applications in electronic commerce, embedded systems and multimedia * Consumer electronics * Culture * Education * Entertainment and Games * Graphics * Health * Industrial control * Internet systems * Motion capture * Network Computing * Publishing * Retail * Smart cards * Telecommunications * Transportation * Virtual reality Hardware, Software and Tools * Design tools for small developers * DVD and new CD-ROM technology * Emerging technologies * Image compression * Portability * Reuse of intellectual property * Standards of interoperability Commercial considerations * Business models * Business trends * Distribution * Electronic Commerce value chain * Intellectual Property Rights * Standards * The regulatory environment * Usability, quality and testing Abstracts for Technical papers, Issue papers, Workshops and Panel discussions Abstracts, should be no more than 300 words, and can be mailed, faxed or emailed please not more than one) before the 15 May 1997 to: EMMSEC 97 c/o Cheshire Henbury P O Box 103, Tamworth House 4 Pumptree Mews, Gawsworth Road Macclesfield, SK11 8UP, UK Telephone: +44 1625 619313 Fax: +44 1625 619 060 email: cheshire_henbury@compuserve.com The abstract heading should state: * Principal author's name and organisation, address, telephone, fax and email * Title of paper In the case of joint authors, communications will be with the first named author who should present the paper. The conference takes place in the attractive city of Florence and the fee is expected to be 500 Ecus. Authors are expected to register for the conference and will qualify for a ten per cent reduction. Publishing schedule Selected technical papers will be professionally published in book form and each delegate will receive a copy of the book on the opening day. This requires the following time scale: * Abstracts submitted before 15 May * Abstracts accepted by the end of May * Draft papers submitted by end of June * The Programme Committee's final comments returned by the end of July * Final papers to be delivered in camera ready format by mid September Exhibition There will be an exhibition of posters and demonstrations covering projects, books software and services. Posters must describe potential industrial benefits and be mainly visual, with any further details in handouts. There is no charge for manned displays but exhibitors must register for the conference and at this stage should submit: * Contact name, address, phone, fax & email * Title of the poster or demonstration * The organisation or consortium represented * Topic description (about 100 words) * Special requirements e.g. electricity and on-line The International Programme Committee Chairman: Marco Bergometti, Giunti Multimedia, (I) Vice Chairman, Luis del Pino, Memondo Graphics, (E) Members: Kari-Pekka Estola, Nokia , (Su) Antonella Fresa, CESVIT, (I) Charles Goldfinger, Global Electronic Finance Management, (B) Giulio Gorla, ITALTEL, (I) Günter Heiner, Daimler Benz, (D) Uros Janko, Mutistream, (D) Paul Kidd, Cheshire Henbury, (UK) Jean-Marie Laporte, OMIMO Matt Lee, ARM, (UK) Franco Maloberti, Universita di Pavia,, (I) Juan Montes, Sony Entertainment, (UK) Silvana Muscella, MTRC-CPR, (I) Antoine Pery, Thomson Mutimedia, (F) Patrick Pype, COWARE, (B) Yves René de Cotret, CEC Jean-Yves, Roger, CEC Bernard Savonet, Les Changeurs, (F) Brian Stanford-Smith, STM, (UK) Wolfgang Strasser, Universtity of Tübingen, (D) From codesign-request@ifi.unizh.ch Thu May 15 19:36:31 1997 Return-Path: Received: from imag.imag.fr by josef.ifi.unizh.ch with SMTP (PP) id <04683-0@josef.ifi.unizh.ch>; Thu, 15 May 1997 19:36:23 +0200 Received: from verdon.imag.fr (verdon.imag.fr [147.171.129.20]) by imag.imag.fr (8.8.1/8.6.9) with ESMTP id TAA27246; Thu, 15 May 1997 19:36:04 +0200 (MET DST) Received: (from jerraya@localhost) by verdon.imag.fr (8.6.11/8.6.9) id TAA19202; Thu, 15 May 1997 19:35:09 +0200 Date: Thu, 15 May 1997 19:35:09 +0200 From: Ahmed Amine Jerraya Message-Id: <199705151735.TAA19202@verdon.imag.fr> X-Mailer: Mail User's Shell (7.2.5 10/14/92) To: isss-people@ics.UCI.EDU, codesign@ifi.unizh.ch Subject: Contribute to the definition of the VHDL successor Status: RO X-Status: Dear collegues, The EDA industry is trying to define the next System Language that will replace VHDL as a standard in the future this is called System Description Language (SLDL). The EDA Industry is organizing a set of meetings for the definition of SLDL. The next meeting will be organized on July 8-11, 1997 in "Il Ciocco", Tuscany, Italy. Attendance is by invitation only. However all participants are requested to give a presentation related to system specifications. If you are interested to participate to the next workshop please let me know or you can request an invitation from ECSI (see below) For more info see: http://www.ecsi.org/ecsi/sldl.html Regards Ahmed ------------------------------------------------------- Second Workshop on System Level Design Language Committee of the EDA Industry Council PTAB CALL FOR PARTICIPATION Organized by ECSI On July 8th - 11th, 1997 In "Il Ciocco", Barga (via Lucca), Tuscany, Italy Sponsoring organization: The Program Technical Advisory Board (PTAB) of the EDA Industry Council The Workshop: Your participating in the Second Workshop on Systems Design Languages is eagerly invited. This three day workshop will be split evenly between presentations of general interest to the systems design community and meetings of the Committee and its Subcommittees. The purpose of the workshop is to: * review the requirements for a systems level design capability, as determined by the meeting of the Committee in San Jose on April 9th and 10th of this year * review the state of the art for potential solutions to those requirements * prepare a set of recommendations to be submitted to the Industry Council as soon as possible =46or the purposes of this effort, a system can include digital hardware, analog hardware, software, and mechanical components. All descriptions of current work are welcome, including existing systems design languages, work on future design languages, formal semantics, working systems description systems, and any other related subjects. Prospective participants are requested to submit a one or two paragraph abstract of their presentation to David Barton (dlb@wash.inmet.com) or Jean Mermet (mermet@imag.fr). The format will be informal, stressing exchange between the participants and attendees. Presentations by slides for overhead projectors is preferred. General presentations will take place on the morning of each of the days of the workshop, with committee and subcommittee meetings taking place in the late afternoon and evening of each day. Attendance: By invitation from ECSI only! How to Apply? Submit your request for invitation to : European CAD Standardization Initiative (ECSI) Parc Equation 2, avenue de Vignate 38610 Gi=E8res, France Phone: +33 (0)4 76 63 49 34 Fax: +33 (0)4 76 42 87 87 E-mail: office@ecsi.alpes-net.fr -- ------------------- PLEASE NOTE THE CHANGEs IN PHONE AND FAX NUMBERS ------ Ahmed Amine JERRAYA, Ph. D | Office: (+33) 476 574 759 ------ System-Level Synthesis Group | Home : (+33) 476 096 014 ------ TIMA/INPG 46 Ave Felix Viallet | Fax : (+33) 476 473 814 ------ F-38031 Grenoble Cedex FRANCE | E_mail: ahmed.jerraya@imag.fr From codesign-request@ifi.unizh.ch Thu May 15 20:45:33 1997 Return-Path: Received: from hudson.wash.inmet.com by josef.ifi.unizh.ch with SMTP (PP) id <06274-0@josef.ifi.unizh.ch>; Thu, 15 May 1997 20:45:12 +0200 Received: (from dlb@localhost) by hudson.wash.inmet.com (8.7.6/8.7.3) id OAA00577; Thu, 15 May 1997 14:42:57 -0400 Date: Thu, 15 May 1997 14:42:57 -0400 Message-Id: <199705151842.OAA00577@hudson.wash.inmet.com> From: David Barton To: Ahmed-Amine.Jerraya@imag.fr CC: isss-people@ics.UCI.EDU, codesign@ifi.unizh.ch In-reply-to: <199705151735.TAA19202@verdon.imag.fr> (message from Ahmed Amine Jerraya on Thu, 15 May 1997 19:35:09 +0200) Subject: Re: Contribute to the definition of the VHDL successor Status: RO X-Status: While I thank Ahmed for his announcement, I have one correction to make. Ahmed Amine Jerraya writes: The EDA industry is trying to define the next System Language that will replace VHDL as a standard in the future this is called System Description Language (SLDL). The SLDL committee is not attempting to replace VHDL. Rather, we are investigating the need for a language to be used at higher levels of abstraction (before a partition between hardware and software has been made, for example) where VHDL begins to break down due to its design as a HARDWARE description language. So we are not replacing VHDL, but devising a language for use where VHDL breaks down. Again, I thank Ahmed for his announcement. Dave Barton <*> dlb@intermetrics.com )0( http://www.intermetrics.com/~dlb From codesign-request@ifi.unizh.ch Mon May 19 01:35:14 1997 Return-Path: Received: from gulf.csc.UVic.CA by josef.ifi.unizh.ch with SMTP (PP) id <16211-0@josef.ifi.unizh.ch>; Mon, 19 May 1997 00:56:37 +0200 Received: from meares.csc.UVic.CA by gulf.csc.UVic.CA (4.1/SMI-4.1-csc.UVic.CA) id AA17252; Sun, 18 May 97 15:56:10 PDT Received: by meares.csc.UVic.CA (4.1/SMI-4.1) id AA20844; Sun, 18 May 97 15:56:08 PDT Date: Sun, 18 May 1997 15:56:07 -0700 (PDT) From: ahafez@meares.csc.UVic.CA To: Codesign_mail_list Subject: Co-design & Industry Message-Id: Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Status: RO X-Status: I wonder whether there is a wide acceptance of Co-design frameworks/tools in the design market, i.e. examples of companies that use them. Thank you. A.H ====================================================================== Ashraf Nabil Hafez Computer Science Department University of Victoria Victoria, B.C. V8W 3P6 Canada Office: (250)-721-8760 Dept. : (250)-721-7209 e-mail: ahafez@gulf.uvic.ca From codesign-request@ifi.unizh.ch Wed May 21 09:46:57 1997 Return-Path: Received: from imag.imag.fr by josef.ifi.unizh.ch with SMTP (PP) id <05619-0@josef.ifi.unizh.ch>; Wed, 21 May 1997 09:46:38 +0200 Received: from verdon.imag.fr (verdon.imag.fr [147.171.129.20]) by imag.imag.fr (8.8.1/8.6.9) with ESMTP id JAA25050; Wed, 21 May 1997 09:46:18 +0200 (MET DST) Received: (from jerraya@localhost) by verdon.imag.fr (8.6.11/8.6.9) id JAA02049; Wed, 21 May 1997 09:45:25 +0200 Date: Wed, 21 May 1997 09:45:25 +0200 From: Ahmed Amine Jerraya Message-Id: <199705210745.JAA02049@verdon.imag.fr> X-Mailer: Mail User's Shell (7.2.5 10/14/92) To: isss-people@ics.UCI.EDU, codesign@ifi.unizh.ch Subject: Re: Contribute to the definition of the VHDL successor Status: RO X-Status: PS: Modification of the WWW page addresse. ------------------------------------------ Dear collegues, The EDA industry is trying to define the next System Language that will sit on top of VHDL in the future this is called System Description Language (SLDL). The EDA Industry is organizing a set of meetings for the definition of SLDL. The next meeting will be organized on July 8-11, 1997 in "Il Ciocco", Tuscany, I taly. If you are interested to participate to the next workshop please let me know or you can request an invitation from ECSI (see below) For more info see: http://www.ecsi.org/ecsi/sld.html Regards Ahmed -- ------------------- PLEASE NOTE THE CHANGEs IN PHONE AND FAX NUMBERS ------ Ahmed Amine JERRAYA, Ph. D | Office: (+33) 476 574 759 ------ System-Level Synthesis Group | Home : (+33) 476 096 014 ------ TIMA/INPG 46 Ave Felix Viallet | Fax : (+33) 476 473 814 ------ F-38031 Grenoble Cedex FRANCE | E_mail: ahmed.jerraya@imag.fr From codesign-request@ifi.unizh.ch Wed May 21 17:59:16 1997 Return-Path: Received: from quay.mail.pipex.net by josef.ifi.unizh.ch with SMTP (PP) id <14640-0@josef.ifi.unizh.ch>; Wed, 21 May 1997 15:45:23 +0200 Received: (qmail 15723 invoked from network); 21 May 1997 13:44:04 -0000 Received: from ampere.iee.org.uk (193.130.181.10) by quay.mail.pipex.net with SMTP; 21 May 1997 13:44:03 -0000 Received: from ms-gw.iee.org.uk by ampere.iee.org.uk (1.38.193.4/MDTG-V Revision: 1.3 ampere.iee.org.uk) id AA27950; Wed, 21 May 1997 14:27:22 +0100 Return-Path: Message-Id: <9705211327.AA27950@ampere.iee.org.uk> From: mswift@iee.org.uk Date: Wed, 21 May 1997 14:39:23 +0000 To: codesign@ifi.unizh.ch Subject: 13-16 July 1997 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Mailer: TFS Gateway /222000000/222041186/222002222/222100421/ Status: RO X-Status: Dear All, Please find below the Hardware/software co-design programme. In order to=20 register for the event you will need to complete a registration form, if yo= u=20 have not already asked for a copy of the programme, please send me your=20 address details. Those of you who have emailed a response including your address will be=20 listed on file. I have not acknowledged receipt of anyone's email message,= =20 unless asked to, due to the volume of messages received. If you need any further information on this event please do not hesitate to= =20 contact me on the following email number mswift@iee.org.uk. Thanks Michelle Swift Groups Officer Vacation School on "HARDWARE-SOFTWARE CO-DESIGN" UMIST, The Manchester Conference Centre, 13-16 July 1997 ORGANISERS The Vacation School has been organised by Professional Groups C2 (Hardware=20 and systems engineering), C1 (Software engineering), J1 (Instrumentation an= d=20 measurement systems) and the British Computer Society Specialist Groups on=20 =93Performance Engineering=94, =93Computer Systems Technologies=94 and =93A= dvanced=20 Programming=94. ORGANISING COMMITTEE The Vacation School has been organised by: Dr Trevor York (UMIST) Chairman Mr M Edwards (UMIST) with the assistance of: Dr R Taylor (Hewlett Packard Research Laboratories) DURATION Registration will take place at 5.00 pm on Sunday, 13 July 1997 and the=20 event will close after lunch on Wednesday, 16 July 1997. VENUE AND ACCOMMODATION The Vacation School will be held at UMIST, the Manchester Conference Centre= ,=20 located on Sackville Street in the heart of Manchester City Centre. The=20 Centre is 400 yards from Piccadilly mainline railway station and 200 yards=20 from Mancunian Way. Train services connect Piccadilly direct to Manchester= =20 airport. Chorlton Coach Station - within 200 yards of the centre - provide= s=20 rapid coach access to all parts of the UK. All accommodation includes en suite facilities. SOCIAL EVENTS The registration fee includes a buffet on the Sunday evening to welcome all= =20 participants, and the School Dinner which will be held in the Weston=20 Restaurant on Tuesday, 15 May 1997. CAR PARK The nearest car park is the Charles Street multi storey car park. It is=20 advisable for guests parking overnight to use the top two levels (Levels L=20= &=20 M) as these are secured overnight. Vouchers to exit the car park may be=20 purchased from the Weston Building Reception at any time before departure a= t=20 special rates of =A33.25 per day and =A35.00 per 24 hour period. AIMS AND SCOPE The aim of the School is to introduce the concepts, key issues and=20 achievements of hardware-software co-design through a series of lectures,=20 case studies and hands-on demonstrations. Hardware-software co-design seeks to remove the distinction between the two= =20 regimes from high level systems design. This is achieved with the help of=20 sophisticated tools which, from a single system specification, will optimis= e=20 the partitioning of designs to satisfy a number of constraints. Over the=20 past 2 years Professional Group C2 have organised the following 3 excellent= =20 Colloquia on co-design under the direction of Dr Richard Taylor (Hewlett=20 Packard Research Laboratories): 'Partitioning in hardware-software=20 co-designs', 'Verification of hardware-software co-designs' and=20 'Hardware-software cosynthesis for reconfigurable systems'. Following the=20 recent emergence of first generation systems from the research laboratory,=20= a=20 Vacation School on =93co-design=94 is now particularly timely. Introductory lectures will provide an overview of the state-of-the-art=20 technology within the field. The potential economic and performance=20 benefits that may be available through the use of hardware-software=20 co-design, and the key areas of specification, partitioning and simulation=20 will also be addressed during the School. The Vacation School is appropriate for practising engineers, from an=20 industrial or academic background, who have a basic understanding of digita= l=20 electronics, software and computer engineering. Suitable attendees would b= e=20 aware of, but not necessarily familiar with, co-design and would like to=20 assess the potential for their own applications. This is a relatively new field with information emerging from a variety of=20 sources. Few courses are available at institutes of higher education and=20 therefore, at present, those with a latent interest must spend considerable= =20 time accessing and filtering information for themselves. The primary=20 objective of the School is to provide delegates with vital knowledge that=20 will enable them to efficiently evaluate the potential of hardware-software= =20 co-design for their own needs. PROGRAMME Sunday, 13 July 1997 5.00 pm Registration 7.00 pm Buffet Supper Monday, 14 July 1997 9.00 am Opening Remarks Trevor York and Martyn Edwards UMIST, UK 9.15 am 'An Overview of Hardware-Software Co-Design' Dr Martyn Edwards UMIST, UK 10.30 am Coffee 11.00 am 'Hardware Technologies for Co-Design' Dr Trevor York UMIST, UK 12.00 pm 'Hardware-Software Co-Synthesis and Reconfigurable Architectures' Mr Ian Page Oxford University Computing Laboratory, UK 1.00 pm Lunch 2.00 pm 'Supervise - Design Methodology and Tools' Mr John Singleton ICL High Performance Systems, UK 3.30 pm Tea 4.00 pm 'MOOSE' Dr Gareth Evans UMIST, UK 5.00 pm 'Hands-On' Demonstrations 7.30 pm Dinner Tuesday, 15 July 1997 9.00 am 'The SGS-Thomson Experience of Using Co-Design for Industrial Applications' Dr Pierre Paulin SGS-Thomson Microelectronics, France 10.30 am Coffee 11.00 am 'The Siemens Experience of Using Co-Design for Industrial Applications' Dr Klaus Buchenrieder Siemens AG, Germany 12.30 pm Lunch 1.30 pm 'Software Acceleration and Hardware Synthesis from C Programs' Dr John Forrest UMIST, UK 2.30 pm 'Formal Methods in Co-Design' Dr Roger Hughes Abstract Hardware, UK 3.30 pm Tea 4.00 pm 'Hardware-Software Partitioning for Real-Time Embedded Systems' Dr Sharon Hu University of Notre Dame, USA 5.00 pm 'Hands-On' Demonstrations 7.30-8.00 pm Drinks Reception Followed by the School Dinner Wednesday, 16 July 1997 9.30 am 'The Future of Co-Design' Dr Richard Taylor Hewlett Packard Research Laboratories, UK 10.30 am Coffee 11.00 am Panel Session : The Future of Co-Design 12.15 pm Closing Remarks 12.30 pm Lunch FEES The fees for the Vacation School are as follows: Residential fee: IEE/BCS/EUREL Member =A3 762.00 (Inc =A3113.49 VAT) Non-Member =A3 886.00 (Inc =A3131.96 VAT) Non-Residential fee: IEE/BCS/EUREL Member =A3 575.00 (Inc =A385.64 VAT) Non-Member =A3 698.00 (Inc =A3103.96 VAT) The residential fee covers bed and breakfast, all other meals and=20 refreshments for the duration of the school, including the School Dinner.=20 The non-residential fee covers all meals and refreshments other than=20 breakfast, including the School Dinner. REGISTRATION Applicants should complete the attached registration form and return it=20 together with remittance, or request for invoice, to: Vacation School Bookings (HSCO) IEE P O Box 96 Stevenage Hertfordshire SG1 2SD to arrive no later than Friday, 4 July 1997. Applications will be accepted strictly in order of receipt of completed=20 registration forms and remittance/invoice request. Reservations CANNOT be=20 made by telephone. VACATION SCHOOL BURSARIES Two bursaries are offered for attendance at each IEE Vacation School to=20 assist members to update/broaden their professional and educational=20 experience. These are intended for IEE members of any class, working in=20 small companies or the academic field who cannot readily find an alternativ= e=20 source of finance towards the cost of their course and residential fees.=20 Further information about these awards can be obtained from the Secretary,= =20 IEE, Savoy Place, London WC2R 0BL, quoting the reference Q(NC). Completed=20 applications should reach the Institution as soon as possible before the=20 start of the Vacation School. EPSRC BURSARIES A limited number of EPSRC bursaries are available for EPSRC-funded research= =20 and CASE students. The bursaries cover all course fees (which includes=20 accommodation and meals) and travel costs. Further information about these= =20 awards can be obtained from Tim Walter, IEE, Savoy Place, London WC2R 0BL=20 (Tel: 0171 240 1871 Ext 2211). CONTINUING PROFESSIONAL DEVELOPMENT The Vacation School qualifies for the IEE Continuing Professional=20 Development scheme. The CPD value of attending the Vacation School is 6.25= =20 T. CANCELLATION In the event of a registrant wishing to cancel, a refund of 75% of the=20 registration fee will be made provided that written notice is received seve= n=20 days prior to the event. From codesign-request@ifi.unizh.ch Thu Jun 12 17:46:17 1997 Return-Path: Received: from clavin.cs.tamu.edu by josef.ifi.unizh.ch with SMTP (PP) id <17026-0@josef.ifi.unizh.ch>; Thu, 12 Jun 1997 17:45:38 +0200 Received: from jetson.cs.tamu.edu (233@jetson [128.194.135.203]) by cs.tamu.edu (8.8.5/8.8.5) with ESMTP id KAA14206 for ; Thu, 12 Jun 1997 10:44:32 -0500 (CDT) From: Fabrizio Lombardi Received: (from lombardi@localhost) by jetson.cs.tamu.edu (8.8.5/8.8.5) id KAA23009 for codesign@ifi.unizh.ch; Thu, 12 Jun 1997 10:45:45 -0500 (CDT) Date: Thu, 12 Jun 1997 10:45:45 -0500 (CDT) Message-Id: <199706121545.KAA23009@jetson.cs.tamu.edu> Subject: 1997 IEEE MTDT Workshop To: codesign@ifi.unizh.ch Status: RO X-Status: ************************************************************************ 1997 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN AND TESTING (MTDT) ************************************************************************ PRELIMINARY TECHNICAL PROGRAM & REGISTRATION FORMS ************************************************************************ August 11-12, 1997 Hilton Hotel And Towers 300 Almaden Blvd, San Jose, California, USA Tel: (408)-287--2100 ************************************************************************ INTRODUCTION TO MTDT 97 You are invited to participate in the 1997 IEEE International Workshop on Memory Technology, Design and Testing. This electronic document includes up-to-date information about the Workshop (Technical Program, Travel Information, etc). Also, please find attached the WORKSHOP REGISTRATION FORM and HOTEL INFORMATION. After filling out the registration form please mail or fax it to guarantee your participation. MTDT 97 is the latest meeting in a series that explores all aspects of memory design, process technologies and testability related topics, such as memory circuit designs, cell structures, fabrication processes, design architectures. The two-day technical program includes 16 paper presentations, one panel session and a keynote address. The paper sessions span many of the key areas in design, test, and technology. Also on the program are sessions on emerging areas that are gaining prominence, such as low power, tools and sensing. We hope that you will find MTDT 97 interesting, thought-provoking, and rewarding. Fabrizio Lombardi General Chair E: lombardi@cs.tamu.edu Thomas Wik Technical Program Chair E: trw@lsil.com Sponsored by: IEEE Computer Society Technical Committee on Test Technology Technical Committee on VLSI In cooperation with: IEEE Solid-State Circuit Society ------------------------------------------------------------------------ 1997 WORKSHOP ON MTDT GENERAL INFORMATION ------------------------------------------------------------------------ All activities require a registration badge for admittance. All participants must pay the appropriate fees. Reduced fees are available to IEEE or Computer Society members on presentation of a valid member number. To register, use the Symposium Registration Form attached to this file. To receive early registration discount rates, your completed Registration Form must be RECEIVED by mail or fax by July 31, 1997. After July 31, register at the higher rates listed in the table below. Technical program registration includes a copy of the Proceedings, (published by IEEE CS Press), the banquet, luncheons and coffee breaks. Lunch and banquet tickets for companions of registered attendees will be available at the registration desk. Extra copies of the Proceedings will be also available at $30 each. REGISTRATION FEES: Early Registration* WORKSHOP IEEE/CS Member $270 Non-members $345 Registration at Hotel WORKSHOP IEEE/CS Member $325 Non-members $400 * discounts available until July 31, 1997 REFUNDS: If you must cancel, advance registration fees will be refunded only upon written request to the Finance Chair postmarked on or before July 15, 1997. A $100 processing fee is charged for each refund. ======================================================================== 1997 WORKSHOP ON MTDT TECHNICAL PROGRAM Monday, August 11th, 1997 ------------------------- 7:30 - 9:00 am Registration ------------------------------------------------------------------------ 9:00 -10:30am PLENARY SESSION WELCOME MESSAGE: F. Lombardi, General Chair KEYNOTE ADDRESS: Matching Memory to the Power of Personal Computers, Richard Foss, MOSAID Technologies Inc., Canada. PROGRAM INTRODUCTION: T. Wik, Program Chair ------------------------------------------------------------------------ 10:30 - 11:00 am BREAK ------------------------------------------------------------------------ 11:00 am - 12:00 pm SESSION 1: ARCHITECTURES. A Low-Cost, High Performance Three-Dimensional Memory Module, A. Glaser, P. Franzon, (North Carolina State University, USA), G. Rinnie, V. Rogers and C. K. Williams (MCNC, USA). High Speed Circuit Techniques in a 150MHz 64M SDRAM, V. Lines, M. Abu-Seido, C. Mar, A. Achyuthan, (MOSAID Technologies Inc., Canada), S. Miyamoto, Y. Murashima and S. Sakuma (OKI Elect. Co., Japan). ------------------------------------------------------------------------ 12:00 - 1:30 pm LUNCH ------------------------------------------------------------------------ 1:30-3:30 pm SESSION 2: FAULT MODELING AND MANUFACTURING. An Analysis of (Linked) Addressed Decoder Faults, A. J. van de Goor and G. N. Gaydadjiev, (Delft University of Technology, The Netherlands). SRAM Yield Estimation in the Early Design Stage, V. Kim and T. Chen, (Colorado State Univeristy, USA). False Write Through and Un-Restored Write Electrical Level Fault Models for SRAMs, R. D. Adams and E. S. Cooley, (Dartmouth College, USA). A Defect-Tolerant DRAM Employing A Hierarchical Redundancy Scheme, Built-In Self-Test and Self-Reconfiguration, D. Niggemeyer, J. Otterstedt and M. Redeker, (Universitat Hannover, Germany). ------------------------------------------------------------------------ 3:30 - 4:00 pm BREAK ------------------------------------------------------------------------ 4:00 - 5:00 pm SESSION 3: TOOLS. Formal Verification of Memory Arrays Using Symbolic Trajectory Evaluation, M. Pandey and R. E. Bryant, (Carnegie Mellon University, USA). A Product Development Flow with Metrics for Memory Designs, S. Hegde, I. P. Pal and K. S. Rao, (Texas Instruments, India). -------------------------------------------------------------------------- 1997 WORKSHOP ON MTDT TECHNICAL PROGRAM Tuesday, August 12, 1997 ------------------------ -------------------------------------------------------------------------- 9:00 - 10:00 am SESSION 4: LOW POWER. A Low-Power High Storage Capacity Structure for GaAs MESFET ROM, R. Kanan, B. Hochet, M. Declercq (Swiss Federal Institute of Technology) and A. Guyot (INPG-TIMA, France). Use of Selective Precharge for Low-Power on the Match Lines of Content-Addressable Memories, C. Zukowski and S.-Y. Wang, (Columbia University, USA). ------------------------------------------------------------------------- 10:00 - 10:30 am BREAK ------------------------------------------------------------------------- 10:30 - 12:00 pm PANEL: Technology, Design and Test of Embedded DRAMs (organized by T. Wik, LSI Logic, USA). -------------------------------------------------------------------------- 12:00 - 1:30 pm LUNCH -------------------------------------------------------------------------- 1:30 - 3:30 pm SESSION 5: TEST. March 3N and March 4N Memory Tests, V. Yarmolik (Belarusian State University), Y. Klimets (Academy of Sciences, Belarus) and S. Demidenko (Singapore Polytechnic). An Open Notation for Memory Tests, A. Offerman and A. J. van de Goor, (Delft University of Technology, The Netherlands). Testing Memory Modules in SRAM-Based Configurable FPGAs, W. K. Huang, F. J. Meyer, N. Park and F. Lombardi, (Texas A&M University, USA). Memory Array Testing Through a Scannable Configuration, S.Yano (NEC Corporation, Japan) and N. Ishiura (Osaka University, Japan). -------------------------------------------------------------------------- 3:30 - 4:00 pm BREAK ------------------------------------------------------------------------- 4:00 - 5:00 pm SESSION 6: SENSING. A High-Speed Parallel Sensing Scheme for Multi-Level Non-Volatile Memories, C. Calligaro, A. Manstretta, G. Torelli, (University of Pavia, Italy) and R. Gastaldi (SGS Thomson,Italy). Differential Built-in Current Sensor (BICS) for Static RAMs: Implementation and Performance, S. M. Menon A. Nymoen (South Dakota School of Mines & Technology, USA). -------------------------------------------------------------------------- 5:00 pm CLOSING REMARKS -------------------------------------------------------------------------- WORKSHOP ORGANIZATION TECHNICAL PROGRAM CHAIR Thomas Wik LSI Logic, MS E-194 1501 McCarthy Blvd Milpitas CA 95035, USA 408/954-4471; trw@lsil.com GENERAL CHAIR Fabrizio Lombardi Computer Science MS 3112 Texas A&M University College Station TX 77843, USA 409/845-5464; fax 847-8578 lombardi@cs.tamu.edu PUBLICITY CHAIR Fred "Jackie" Meyer Computer Science MS 3112 Texas A&M University College Station TX 77843, USA 409/845-1014; fmeyer@cs.tamu.edu FINANCE CHAIR Duncan "Hank" Walker Computer Science MS 3112 Texas A&M University College Station TX 77843, USA 409/862-4387; fax 847-8578 walker@cs.tamu.edu STEERING COMMITTEE Rochit Rajsuman, Chair Equator Technologies, Inc. (408) 260-0599, ext. 337 rajsuman@equator.com Bernard Courtois, INPG/TIMA Grenoble, France Ad J. van de Goor, Delft University of Technology, The Netherlands Yervant Zorian, Logic Vision, Princeton NJ, USA PROGRAM COMMITTEE Abhaya Asthana, Lucent Technologies, Princeton NJ, USA Bruce Cockburn, University of Alberta, Edmonton AB, Canada Mike DePaolis, Lucent Technologies, Princeton NJ, USA Bob Evans, MosAid, San Jose CA, USA E. Fujiwara, Tokyo Institute of Technology, Tokyo, Japan Susanne Griep, Siemens AG, Munchen, Germany S. Horiguchi, Japan Advanced Institute of Science and Technology, Tatsunokuchi, Japan Swee Yong Khim, Texas Instruments, Singapore David Lepejian, HPL, Milpitas CA, USA Yashwant Malaiya, Colorado State University, USA P. Olivo, University of Bologna, Bologna, Italy Ritu Shrivastava, Alliance Semiconductor, San Jose CA, USA ======================================================================== 1997 WORKSHOP ON MTDT **** EARLY REGISTRATION DISCOUNT FORM **** MAIL or FAX form to: Dr. D. H. Walker Finance Chair 1997 W-MTDT Department of Computer Science Texas A&M University College Station TX 77843 USA Tel: (409) 862-4387 Fax: (409) 847-8578 Email: walker@cs.tamu.edu IMPORTANT: Read GENERAL INFORMATION, above, before completing this form. After July 31, register at the Workshop. (Registration-at-Hotel rates will apply.) First Name:____________________________________________ Last Name:_____________________________________________ Company:_______________________________________________ Mail Stop:_____________________________________________ St. Address/Box No.:___________________________________ City:_____________________________ State (US):_________ Zip Code (US):_____________ Country:___________________ Tel:_______________________Fax:________________________ E-mail:____________________IEEE Mmbr No.*:_____________ SPECIAL DIETARY REQUIREMENT: Vegetarian______ Other (specify)_______________________________ DISCOUNT REGISTRATION (available until July 31) TECHNICAL PROGRAM August 11-12 IEEE/CS Member* $270 _____ Non-Member $345 _____ ADDITIONAL Copies of MTDT 97 Proceedings pick up at symposium. Quan.___ @ $30 _____ TOTAL: $_______ * - IEEE/CS member rates are granted only if your current valid member number is filled in above. SEND FULL PAYMENT IN US$ WITH THIS FORM. Use a check drawn on a US bank, or a US bank credit card. PURCHASE ORDERS ARE NOT ACCEPTED. Make checks payable to: 1997 IEEE WORKSHOP ON MTDT. USE YOUR CREDIT CARD IF REGISTERING BY FAX. FOR CREDIT CARD PAYMENT: Check card type: VISA/MASTERCARD____________ AMERICAN EXPRESS___________ CARD NO.:_____________________ Exp. Date:______________ CARDHOLDER SIGNATURE:__________________________________ Advance registration fees will be refunded only on written request, mailed or fax'ed, and received by July 15, 1997. A $100 processing fee is charged for each refund. =========================================================== HOTEL ACCOMMODATION San Jose Hilton Hotel and Tower is located in Down Town San Jose. The Hotel provides courtesy shuttle from San Jose International Airport. HOTEL ADDRESS: 300 Almaden Blvd San Jose, CA 95110 Tel: (408) 287-2100, Fax: (408) 947-4488 Toll Free: 1-800-445-8667 RATES: Singe $125, Double $125 ($15 extra person) Towers Room $25 extra Suite $295 to $650 Participants should reserve the room directly with the hotel using the above numbers. The above discount rates are guaranteed if reservations are made before July 10, 1997. At the time of reservation, the name of the workshop (MTDT-97) must be identified. =========================================================== From codesign-request@ifi.unizh.ch Wed Jun 25 15:56:15 1997 Return-Path: Received: from ms-gw.iee.org.uk by josef.ifi.unizh.ch with SMTP (PP) id <00343-0@josef.ifi.unizh.ch>; Wed, 25 Jun 1997 15:56:05 +0200 From: mswift@iee.org.uk Date: Wed, 25 Jun 1997 14:53:06 +0000 To: codesign@ifi.unizh.ch Subject: HARDWARE-SOFTWARE CO-DESIGN X-Mailer: TFS Gateway /222000000/222041186/222002222/222100421/ Message-ID: <"josef.ifi..348:25.05.97.13.56.13"@ifi.unizh.ch> Status: RO X-Status: Dear All, Many of you replied to my message concerning the above Vacation School due to be held on the 13-16 July 1997 at UMIST, and should have by now received a programme and registration form. So far the registrations are low and unless I receive more forms or postive responses we will be looking at cancelling the event. ANYONE WHO IS INTERESTED IN ATTENDING OR HAS SENT THEIR REGISTRATION FORM TO THEIR FINANCE DEPT FOR APPROVAL PLEASE LET ME KNOW BY RETURN EMAIL AT THE ADDRESSES BELOW. I am also interested to hear other reasons for not attending the event Please send any reponses to the following email addresses: mswift@iee.org.uk and mbarrett@iee.org.uk. Many thanks Michelle swift From codesign-request@ifi.unizh.ch Mon Jun 30 15:09:16 1997 Return-Path: Received: from ms-gw.iee.org.uk by josef.ifi.unizh.ch with SMTP (PP) id <28969-0@josef.ifi.unizh.ch>; Mon, 30 Jun 1997 15:08:57 +0200 From: mswift@iee.org.uk Date: Mon, 30 Jun 1997 14:07:55 +0000 To: codesign@ifi.unizh.ch Subject: Hardware-software co-design X-Mailer: TFS Gateway /222000000/222041186/222002222/222100421/ Message-ID: <"josef.ifi..980:30.05.97.13.09.15"@ifi.unizh.ch> Status: RO X-Status: Dear All, We have had to cancel the above event which was due to take place on 13-16 July 1997, due to low registrations. In order to help us analise the reasons behind the cancellation, I would appreciate any response concerning the timing, location, content of the programme etc. I am looking forward to receiving your response. Many Thanks Michelle Swift Groups Officer IEE Divisional Services From codesign-request@ifi.unizh.ch Wed Jul 9 22:54:20 1997 Return-Path: Received: from imecgate.imec.be by josef.ifi.unizh.ch with SMTP (PP) id <29830-0@josef.ifi.unizh.ch>; Wed, 9 Jul 1997 22:09:30 +0200 Received: from unimec.imec.be (unimec) by imecgate.imec.be (5.65c/IDA-1.4.4-IMEC) id AA27184d; Wed, 9 Jul 1997 22:00:26 +0200 Original-Received: by unimec.imec.be Wed, 9 Jul 1997 22:00:23 +0200 PP-warning: Illegal Received field on preceding line From: Francky Catthoor Date: Wed, 9 Jul 1997 21:59:01 +0200 Message-Id: <199707091959.AA295058341@lobelia.imec.be> Original-Received: by lobelia.imec.be Wed, 9 Jul 1997 21:59:01 +0200 PP-warning: Illegal Received field on preceding line To: isss97@imec.be Subject: updated ISSS'97 advance programme Status: RO X-Status: Dear colleague, as you are active in the general area of system and architectural design and synthesis issues, you are probably interested to obtain the more detailed advance program of the ISSS'97 conference which will take place in Belgium on Sept.17-19. *** Please note the change in the registration information below. *** This year's program is again very exciting with 6 interesting invited speakers on topics covering formal verification, education for deep submicron age, compilers for embedded processors, (embedded) DRAM memories, system-level codesign in industry, and real-time software system methodologies. In addition to 18 high-quality papers, we also have 2 exciting panels and the traditional discussion topics where all the participants contribute. That mix should make ISSS interesting for both academic and industrial attendees. A web site has been installed with much more information still: http://www.imec.be/isss97/ There you can check for the latest ISSS'97 related info. We are looking forward to receiving your advance registration by August 8, 1997. *** Please register in time so that you can make use of the discount. *** Regards, Francky Catthoor (Program Chair-man) ------------------------------------------------------ 10TH INTERNATIONAL SYMPOSIUM ON SYSTEM SYNTHESIS (ISSS) ------------------------------------------------------ Antwerp, Belgium, September 17-19, 1997 ADVANCE PROGRAM ------------------------------------------------------ Sponsored by the IEEE Computer Society DATC and the ACM SIGDA (http://www.imec.be/isss97/) ***************** Important Dates ***************** Advance Registration Deadline : August 8, 1997 Hotel Reservation Deadline : August 15, 1997 On-Site Registration : September 16-17, 1997 ********** About ISSS ********** ISSS is a major international forum presenting emerging techniques for the system-level design and synthesis of computing systems. Having begun as the International Workshop on High-Level Synthesis in the mid-80's, it attracts leading design automation professionals from around the world. The growing acceptance of commercial synthesis tools, and the unified view of both hardware and software that such tools enable, have led to the symposium expanding to now cover system-level synthesis, hardware/software codesign, programmable (multi-)processor-based design, architectural and high-level synthesis, system-design experience and methodologies, embedded and real-time system software, synthesis for low power and testability and verifiability ISSS'97 is the 10th in this very successful series of symposia. It features 6 invited tutorial talks by leading industrial (Dr. Frank Gielen, Alcatel-Telecom; Dr. Roelof Salters, Philips; Dr. Richard Taylor, HP Labs) and academic experts (Prof. Hugo De Man, Prof. Gerry Musgrave, Prof. Alex Nicolau) on very timely and interesting topics related but not overlapping with the other ISSS activities. In addition, 2 panel sessions are organized on topics of active interest for the future of our community. ISSS'97 also features 18 high-quality papers selected from over 60 submissions. Paper presentations will consist of 20 minute talks followed by poster sessions, allowing ample time for discussion and interaction. On the first evening, a social event is planned. **************** Antwerp, Belgium **************** The symposium's location, Antwerp, is a city with a glorious past. Hometown of world famous artists who created here a unique pageant of history. Someone wandering round in Antwerp at the beginning of the 17th century would soon run into the best-known painters, sculptors, instrument makers and printers. Rubens worked together with Jordaens, van Dijck, Jan Bruegel and Erasmus II Quellinus, who illustrated books that were printed by Balthazar Moretus. All of these masters were at home in Antwerp. The Antwerp museums and churches are all richly endowed. Antwerp is art. Antwerp, a city with a rich and glorious present. The port: a whirlpool of activity. A diamond sector that has given the city a name and fame; the place to buy diamonds. The Diamond Museum explains the whole process, from mining to brilliant jewelry. The Antwerp Zoo is world famous. Antwerp, a bustling and hospitable metropolis. With terraces, pubs and restaurants, museums, movies, theatre, dance, music and modern art, a large city on a small scale. It is easily accessible by air (Brussels airport is 30 minutes away), train and car. ****************** Technical Program ****************** --------------------------- Tuesday, September 16, 1997 --------------------------- 18:00 - 20:00 Registration 19:00 - 21:00 Reception ----------------------------- Wednesday, September 17, 1997 ----------------------------- 8:30-12:00 Registration 9:00 Opening Session & Invited Talk ----------------------------- o Opening & Welcoming remarks Frank Vahid, UC Riverside, CA, USA o "Formal Verification: The Enabling or the Handicapping Process?" Gerry Musgrave, Brunel University, UK 10:30 Session 1 : Formal specification and validation ----------------------------------------------- Chair: Lev Markov, Mentor Graphics, Wayland MA, USA 1.1 Quick Conservative Causality Analysis Ellen Sentovich, Cadence Berkeley Labs, CA, USA 1.2 An Efficient Representation for Formal Synthesis Christian Blumenroehr, Dirk Eisenbiegler, Univ. Karlsruhe, Germany 1.3 Derivation of Formal Representations from Process-based Specification and Implementation Models Steven Vercauteren, Diederik Verkest, IMEC, Belgium Bill Lin, U.C. San Diego CA, USA 12:00 Lunch 13:30 Panel Discussion ---------------- "Where is Fast Prototyping Heading ?" Organizer: Rudy Lauwereins, Univ. of Leuven, Belgium Panel Members: Nick Kanopoulos, DCT, Research Triangle Park, North Carolina, USA Rudy Lauwereins, Univ. of Leuven, Belgium Ian Page, University of Oxford, Oxford, UK Peter Pirsch, Univ. of Hannover, Germany Stefaan Note, Philips ITCL, Leuven, Belgium Kees Vissers, Philips Natlab, Eindhoven, The Netherlands 15:00 Session 2 : Fast prototyping and code generation ------------------------------------------------ Chair: Kees Vissers, Philips Research, The Netherlands 2.1 Prototyping of the Receiver Unit for a Broadband Access Network Axel Hein, Josef Dalcolmo, Patrick Le Corre, Rudy Lauwereins, Marleen Ade, Jean Peperstraete, Univ. of Leuven, Belgium 2.2 Constraint Analysis for DSP Code Generation Bart Mesman, Marino Strik, Adwin Timmer, Jef van Meerbergen, Philips Research, The Netherlands Jochen Jess, Eindhoven Univ. of Technology, The Netherlands 2.3 An Efficient Model for DSP Code Generation: Performance, Code Size, Estimated Energy Cathy Gebotys, Univ. of Waterloo, Ontario, Canada 16:30 Invited Talk ------------ "Education for the Deep Submicron Age : Business as Usual?" Hugo De Man, Univ. of Leuven and IMEC, Belgium 17:30 Social event: guided beer tour in Antwerp ---------------------------- Thursday, September 18, 1997 ---------------------------- 8:30 Invited Talk ------------ "True State-of-the-art Compilers: Instruction-level Parallelism and Speculation Exploitation" Alexandru Nicolau, U.C.Irvine, CA, USA 9:30 Session 3 : Novel compilation and optimization issues ----------------------------------------------------- Chair: Rolf Ernst, Technical Univ. Braunschweig, Germany 3.1 Embedded System Synthesis by Timing Constraint Solving Krzysztof Kuchcinski, Linkoeping Univ., Sweden 3.2 Reducing the Complexity of ILP Formulations for Synthesis Anne Mignotte, Olivier Peyran, Ecole Normale Superieure de Lyon, France 3.3 A New Optimization Technique for Improving Resource Exploitation and Critical Path Minimization Birger Landwehr, Peter Marwedel, Univ. of Dortmund, Germany 11:00 Focus Group ----------- Workshop discussions involving all attendees 12:00 Lunch 13:30 Invited Talk ------------ "Embedded Memories and Embedded Logic" Roelof Salters, Philips Research, The Netherlands 14:30 Session 4 : Memory management issues ------------------------------------ Chair: Paul Lippens, Philips Research, The Netherlands 4.1 Fast and Extensive System-level Memory Exploration for ATM Applications Peter Slock, Sven Wuytack, Francky Catthoor, IMEC, Belgium Gjalt de Jong, Alcatel Telecom, Belgium 4.2 Optimization of the Background Memory Utilization by Partitioning Uwe Eckhardt, Technical Univ. Dresden, Germany 4.3 Architectural Exploration and Optimization of Local Memory in Embedded Systems, Preeti Panda, Nikil Dutt, Alexandru Nicolau, U.C.Irvine CA, USA 16:00 Panel Discussion ---------------- How will Memory Issues Impact Synthesis for Embedded Systems-on-Silicon? Organizer: Nikil Dutt, U.C.Irvine CA, USA Panel Members: Paul Lippens, Philips, The Netherlands Vijay Nagasamy, VSIS, USA Roelof Salters, Philips, The Netherlands Norbert Wehn, Siemens, Germany Sven Wuytack, IMEC, Belgium 18:30 Banquet (with Dan Gajski, UC Irvine as dinner speaker) -------------------------- Friday, September 19, 1997 -------------------------- 8:30 Invited Talk ------------ "System-level Codesign : A New Industrial Revolution" Richard Taylor, Hewlett-Packard Labs, Bristol, UK 9:30 Session 5 : System-Level Synthesis and Design --------------------------------------------- Chair: Sanjiv Narayan, Ambit Design Systems, CA, USA 5.1 Optimization Method for Broadband Modem FIR Filter Design using Common Subexpression Elimination, Robert Pasko, Daniela Durackova, Slovak Technical Univ, Slovakia Patrick Schaumont, Veerle Derudder, IMEC, Belgium 5.2 Port Calling: A Transformation for Reducing I/O during Multi-Package Functional Partitioning, Frank Vahid, UC Riverside, CA, USA 5.3 A Scheduling and Pipelining Algorithm for Hardware/Software Systems Smita Bakshi, Daniel Gajski, U.C.Irvine CA, USA 11:00 Focus Group ----------- Continuation 12:00 Lunch 13:30 Invited Talk ------------ "SDL Methodology for Real-Time Software Systems" Frank Gielen, Alcatel Telecom, Belgium 14:30 Session 6 : HW/SW specification and debugging --------------------------------------------- Chair: Bob Walker, Kent State Univ., OH, USA 6.1 Co-Emulation and Debugging of HW/SW-Systems Gernot Koch, Udo Kebschull, Wolfgang Rosenstiel, Univ. Karlsruhe, Germany 6.2 Synthesising Controllers from Real-Time Specifications Henning Dierks, Univ. of Oldenburg, Germany 6.3 A Source-level Dynamic Analysis Methodology and Tool for High-level Synthesis Chih-Tung Chen, Kayhan Kucukcakar, Motorola Inc., Tempe AZ, USA 16:00 Future Directions and Closing 17:00 Symposium Ends ******************** Hotel Information ******************** Make reservations directly with the Park Lane Hotel, Antwerp, mentioning ISSS'97 to obtain the special low rates. Rates are guaranteed until August 26, 1997 after which reservations will be based on availability. Address: -------- Park Lane Hotel Van Eycklei 34, 2018 Antwerp, Belgium http://www.parklane.be/parklane/ e-mail: info@parklane.be Tel: +32 (3) 285 85 85 Fax: +32 (3) 285 85 86 Rates: ------ 4950 BFr (about $140 with current conversion rate) This includes breakfast and tax and all hotel services The same price applies for single or double occupancy *************************** Registration Information *************************** To register, please fill in the registration form and arrange a direct payment (free of any bank charges) on the account number: 005-4359248-60, mentioning ISSS97 p/a IMEC. The SWIFT code is: CGAKBEBB. The bank is: ASLK, Naamse steenweg 163, 3001 Leuven Belgium. Mail the completed form to: Annemie Stas, ISSS'97 IMEC Kapeldreef 75, 3001 Leuven, Belgium Alternatively (preferably not) you can enclose the appropriate fee in the form of a check (payable to "ISSS'97") in US dollars which can be drawn on a Belgian bank (again without charges to us). The advance registration fee must be received by August 8, 1997. Written requests for refunds should be made prior to this date. After September 1, 1997, all registrations will be processed only at the conference site. Registrations cannot be accepted over phone, fax, email, or through credit-cards. The conference fee includes all social events, lunches and breaks. For further information, contact Annemie Stas at annemie@imec.be Tel: +32 (16) 281-200; Fax: +32-16-281-515 For students, a number or travel fellowships are available (of about 300$), sponsored by Alcatel Telecom, Antwerp. Information is (and will be) made available at the ISSS'97 web page under registration. If you wish to apply for these fellowships, please send or e-mail a letter of request with motivation of why you need support to Francky Catthoor at catthoor@imec.be, IMEC, Kapeldreef 75, 3001 Leuven, Belgium ********************** Symposium Proceedings ********************** The symposium proceedings will be published by IEEE CS Press but will also be available from ACM. Extra copies of the proceedings can be ordered from: Customer Service Department IEEE Computer Society Press 10662 Los Vaqueros Circle P.O. Box 3014 Los Alamitos, California 90720 Tel: (714) 821-8380 Fax: (714) 821-4641 Email: cs.books@computer.org ------------------------- cut here -------------------------------- ISSS'97 Registration Form *************************** By August 8 1997 After August 8, 1997 ----------------- -------------------- ACM/IEEE Members $ 330 $ 400 Non-Members $ 420 $ 490 Full-time Students $ 300 $ 330 Name : __________________________________ Affiliation : __________________________________ Address : __________________________________ __________________________________ __________________________________ Phone : ___________________ Fax : ___________________ Email : ___________________ Special needs : _________________ Total Amount Enclosed : US $ ____________ (or transferred to the above mentioned account) ACM/IEEE Membership # : _________________ (reqd. if registering at ACM/IEEE rates) ------------------------- cut here -------------------------------- *********************** Organizing Committee *********************** General Chair: Frank Vahid, UC Riverside Program Chair: Francky Catthoor, IMEC Publications Chair: Edwin Sha, Univ. Notre Dame Publicity Chair: Diederik Verkest, IMEC Panels Chair: Rudy Lauwereins, Univ. of Leuven Past Chair: Ahmed Jerraya, TIMA-CNRS, Grenoble Finance Chair: Annemie Stas, IMEC Technical Program Committee --------------------------- Marleen Ade, Univ. of Leuven Gaetano Borriello, Univ. Washington Raul Camposano, Synopsys Nikil Dutt, UC Irvine Rolf Ernst, Tech. Univ. Braunschweig Daniel Gajski, UC Irvine Cathy Gebotys, Univ. Waterloo Yu-Chin Hsu, Avant! Kayhan Kucukcakar, Motorola Fadi Kurdahi, UC Irvine Steve YL Lin, Tsing Hua Univ. Paul Lippens, Philips Jan Madsen, Tech. Univ. Denmark Lev Markov, Mentor Graphics Peter Marwedel, Univ. Dortmund Vijay Nagasamy, VSIS Inc. Yukihiro Nakamura, Kyoto Univ. Sanjiv Narayan, Ambit Design Systems Kevin O'Brien, Leda Pierre Paulin, SGS-Thomson Wolfgang Rosenstiel, Univ. Tubingen, FZI Edwin Sha, Univ. Notre Dame Leon Stok, IBM Donald Thomas, CMU Kazutoshi Wakabayashi, NEC Robert Walker, Kent State Univ. Wayne Wolf, Princeton ------------------------------------------------------------------------------- ** Sponsored by the IEEE Computer Society (DATC) and the ACM SIGDA ** ------------------------------------------------------------------------------- From codesign-request@ifi.unizh.ch Tue Jul 15 18:22:41 1997 Return-Path: Received: from david.siemens.de by josef.ifi.unizh.ch with SMTP (PP) id <20801-0@josef.ifi.unizh.ch>; Tue, 15 Jul 1997 18:06:34 +0200 Received: from salomon.mchp.siemens.de (salomon.siemens.de [139.23.33.13]) by david.siemens.de (8.8.6/8.8.5) with ESMTP id SAA08001 for ; Tue, 15 Jul 1997 18:06:25 +0200 (MDT) Received: from webster.hl.siemens.de (webster.hl.siemens.de [190.1.13.40]) by salomon.mchp.siemens.de (8.8.6/8.8.5) with ESMTP id SAA26990 for ; Tue, 15 Jul 1997 18:06:25 +0200 (MDT) Received: from christl.hl.siemens.de (root@christl.hl.siemens.de [190.1.29.130]) by webster.hl.siemens.de (8.7.4/8.7.3) with ESMTP id SAA17557 for ; Tue, 15 Jul 1997 18:05:56 +0200 (MET DST) Received: from oasis (connell@oasis [190.1.24.187]) by christl.hl.siemens.de (8.8.5/8.8.5) with ESMTP id SAA26168 for ; Tue, 15 Jul 1997 18:05:50 +0200 (MET DST) Sender: jon.connell@hl.siemens.de Message-ID: <33CB9FDD.CD5EFABA@hl.siemens.de> Date: Tue, 15 Jul 1997 18:05:49 +0200 From: Jon Connell Organization: Siemens HL, Microcomputer ICs X-Mailer: Mozilla 4.01b6C [en] (X11; I; SunOS 5.5.1 sun4u) MIME-Version: 1.0 To: codesign@ifi.unizh.ch Subject: HW/SW Cosimulation expertise wanted X-Priority: 3 (Normal) Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Status: RO X-Status: We are currently looking to develop a HW/SW cosimulation environment based on GDI and a standard HDL simulator interface. Our goal is to support any GDI debug instrument which is compatible with our microprocessor model running the software for the cosimulation, and any HDL simulator which simulates the hardware part. Since we have little experience in this area, we are looking for experts in cosimulation who may be able to help up build a professional environment. One major technical hurdle is the control of the HDL simulator from the GDI debug instrument (a user "running" software will expect the HDL simulator to restart without automatically). -- Hacking's just another word for nothing left to kludge. E-Mail : Jon.Connell@hl.siemens.de WWW : http://homepages.munich.netsurf.de/Jonathan.Connell/ Fax : +49 89 636-82692 | Tel : +49 89 636-82687 From pilz@ifi.unizh.ch Tue Jul 22 18:27:51 1997 Status: RO X-Status: Return-Path: Received: from cad.fla.fujitsu.com by josef.ifi.unizh.ch with SMTP (PP) id <17846-0@josef.ifi.unizh.ch>; Tue, 22 Jul 1997 18:27:29 +0200 Received: from brain.fla.fujitsu.com (brain.fla.fujitsu.com [133.164.58.130]) by cad.fla.fujitsu.com (8.8.6/8.8.6) with SMTP id JAA25174 for ; Tue, 22 Jul 1997 09:27:06 -0700 (PDT) Received: by brain.fla.fujitsu.com (4.1/SMI-4.1) id AA04192; Tue, 22 Jul 97 09:24:28 PDT Message-Id: <9707221624.AA04192@brain.fla.fujitsu.com> To: codesign@ifi.unizh.ch Subject: CFP: HLDVT97 Reply-To: fujita@fla.fujitsu.com From: fujita@fla.fujitsu.com (Masahiro Fujita) Date: Tue, 22 Jul 97 09:24:27 -0700 Sender: fujita@fla.fujitsu.com IEEE International High Level Design Validation and Test Workshop http://www-cse.ucsd.edu/groups/hldvt97 The Claremont Resort & Spa, Oakland, California Nov. 14-15, 1997 Call For Participation The Second IEEE International High Level Design Validation and Test Workshop aims to stimulate research in test and validation methodolo- gies for ICs and systems specified using high level descriptions, where high level refers to register-transfer, behavioral, and system level specifications. The goal of the workshop is to provide an infor- mal forum, bringing together designers and test and verification researchers working in validating, debugging, and testing designs, in an effort to address high level design validation and test issues con- currently. Major topics include, but are not limited to, the follow- ing: High Level Design Validation Hardware/Software Co-Validation High Level Design Error Modeling High Level DFT/Synthesis for Test High Level Test Bench Generation High Level ATPG/Fault Simulation Testing Core Based Designs Validation of Microprocessors Hardware/Software Co-Testing Design Error Debug & Diagnosis The Program Committee invites authors to submit an extended summary comprising 1000 words describing original, unpublished recent work. Clearly describe the nature of the work, explain its significance, highlight novel features, and describe its current status. On the title page, please indicate: title, name and affiliations of all authors, and suggested topics. Also identify a contact author and include a complete mailing address, phone number, fax number and E- mail address. Panel proposals are also invited. Submit seven copies of proposals by mail or a Postscript version via E-mail. Submissions are due no later than August 1, 1997. Submit all paper proposals to: For general information, contact: Sujit Dey, Program Chair Prab Varma, General Chair NEC USA Duet Technologies Inc. 4 Independence Way 2833 Junction Ave., #100 Princeton, NJ 08540 San Jose, CA 95134 T: 609-951-2973, F: 609-951-2499 T: 408-432-9200, F: 408-432-0907 E-mail: dey@ccrl.nj.nec.com E-mail: prab@duettech.com Authors will be notified of the disposition of their papers by September 15, 1997. The submission of a proposal will be considered evidence that upon acceptance the author(s) will present the paper at the workshop. Authors of accepted papers may submit a full version of their paper by October 15, 1997 for inclusion in an informal digest of papers, which will be distributed only to attendees of the workshop. The Second International High Level Design Validation and Test Workshop is sponsored by the IEEE Computer Society Test Technology Technical Committee and the IEEE Computer Society Design Automation Technical Committee. HLDVT'97 Steering Committee General Chair P. Varma Duet Technologies Inc. Vice-General Chair P. Marwedel U. Dortmund Program Chair S.Dey NEC USA Finance Chair A. Orailoglu UC San Diego Publicity Chair M. Fujita Fujitsu Labs Proceedings Chair R.Raina Motorola Inc. European Liaison B.Courtois TIMA Asian Liaison H.Yasuura Kyushu University Member At Large V.Nagaswamy VSI Program Committee (to include) M. Abadir - Motorola J. Abraham - U of Texas T. Ambler - U of Texas B. Bennetts - LogicVision R. Bergamaschi - IBM S. Bhatia - Duet Technologies F. Brglez - NCSU K-T. Cheng - UCSB H. Date - ISIT R. Gupta - UCI A.Jerraya - TIMA J. Jess - Eindhoven Univ R. Karri - Lucent Bell Labs D. Ku - Escalade L. Lavagno - Poli. di Torino/ Cadence Berkeley Labs M. Lee - Avant! J. Lu - National Semiconductors J-P. Masbou - Intel E.J. McCluskey - Stanford Univ T. Nakata - Fujitsu C. Papachristou - CWRU C. Pixley - Motorola I. Pomeranz - U of Iowa M. Potkonjak - UCLA P. Prinetto - Poli di Torino J. Rajski - Mentor Graphics W. Rosenstiel - Tuebingen Univ B. Rouzeyre - LIRMM R. Roy - Intel A. Takahara - NTT Y. Zorian - LogicVision From pilz@ifi.unizh.ch Sun Jul 27 23:05:28 1997 Status: RO X-Status: Return-Path: Received: from clavin.cs.tamu.edu by josef.ifi.unizh.ch with SMTP (PP) id <11025-0@josef.ifi.unizh.ch>; Sun, 27 Jul 1997 23:05:19 +0200 Received: from jetson.cs.tamu.edu (233@jetson [128.194.135.203]) by cs.tamu.edu (8.8.5/8.8.5) with ESMTP id QAA24274 for ; Sun, 27 Jul 1997 16:04:03 -0500 (CDT) From: Fabrizio Lombardi Subject: MTDT'97 Received: (from lombardi@localhost) by jetson.cs.tamu.edu (8.8.5/8.8.5) id QAA14511 for codesign@ifi.unizh.ch; Sun, 27 Jul 1997 16:05:57 -0500 (CDT) Date: Sun, 27 Jul 1997 16:05:57 -0500 (CDT) Message-Id: <199707272105.QAA14511@jetson.cs.tamu.edu> To: codesign@ifi.unizh.ch ************************************************************************ 1997 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN AND TESTING (MTDT) ************************************************************************ PRELIMINARY TECHNICAL PROGRAM & REGISTRATION FORMS ************************************************************************ August 11-12, 1997 Hilton Hotel And Towers 300 Almaden Blvd, San Jose, California, USA Tel: (408)-287--2100 ************************************************************************ INTRODUCTION TO MTDT 97 You are invited to participate in the 1997 IEEE International Workshop on Memory Technology, Design and Testing. This electronic document includes up-to-date information about the Workshop (Technical Program, Travel Information, etc). Also, please find attached the WORKSHOP REGISTRATION FORM and HOTEL INFORMATION. After filling out the registration form please mail or fax it to guarantee your participation. MTDT 97 is the latest meeting in a series that explores all aspects of memory design, process technologies and testability related topics, such as memory circuit designs, cell structures, fabrication processes, design architectures. The two-day technical program includes 16 paper presentations, one panel session and a keynote address. The paper sessions span many of the key areas in design, test, and technology. Also on the program are sessions on emerging areas that are gaining prominence, such as low power, tools and sensing. We hope that you will find MTDT 97 interesting, thought-provoking, and rewarding. Fabrizio Lombardi General Chair E: lombardi@cs.tamu.edu Thomas Wik Technical Program Chair E: trw@lsil.com Sponsored by: IEEE Computer Society Technical Committee on Test Technology Technical Committee on VLSI In cooperation with: IEEE Solid-State Circuit Society ------------------------------------------------------------------------ 1997 WORKSHOP ON MTDT GENERAL INFORMATION ------------------------------------------------------------------------ All activities require a registration badge for admittance. All participants must pay the appropriate fees. Reduced fees are available to IEEE or Computer Society members on presentation of a valid member number. To register, use the Symposium Registration Form attached to this file. To receive early registration discount rates, your completed Registration Form must be RECEIVED by mail or fax by July 31, 1997. After July 31, register at the higher rates listed in the table below. Technical program registration includes a copy of the Proceedings, (published by IEEE CS Press), the banquet, luncheons and coffee breaks. Lunch and banquet tickets for companions of registered attendees will be available at the registration desk. Extra copies of the Proceedings will be also available at $30 each. REGISTRATION FEES: Early Registration* WORKSHOP IEEE/CS Member $270 Non-members $345 Registration at Hotel WORKSHOP IEEE/CS Member $325 Non-members $400 * discounts available until July 31, 1997 REFUNDS: If you must cancel, advance registration fees will be refunded only upon written request to the Finance Chair postmarked on or before July 15, 1997. A $100 processing fee is charged for each refund. ======================================================================== 1997 WORKSHOP ON MTDT TECHNICAL PROGRAM Monday, August 11th, 1997 ------------------------- 7:30 - 9:00 am Registration ------------------------------------------------------------------------ 9:00 -10:30am PLENARY SESSION WELCOME MESSAGE: F. Lombardi, General Chair KEYNOTE ADDRESS: Matching Memory to the Power of Personal Computers, Richard Foss, MOSAID Technologies Inc., Canada. PROGRAM INTRODUCTION: T. Wik, Program Chair ------------------------------------------------------------------------ 10:30 - 11:00 am BREAK ------------------------------------------------------------------------ 11:00 am - 12:00 pm SESSION 1: ARCHITECTURES. A Low-Cost, High Performance Three-Dimensional Memory Module, A. Glaser, P. Franzon, (North Carolina State University, USA), G. Rinnie, V. Rogers and C. K. Williams (MCNC, USA). High Speed Circuit Techniques in a 150MHz 64M SDRAM, V. Lines, M. Abu-Seido, C. Mar, A. Achyuthan, (MOSAID Technologies Inc., Canada), S. Miyamoto, Y. Murashima and S. Sakuma (OKI Elect. Co., Japan). ------------------------------------------------------------------------ 12:00 - 1:30 pm LUNCH ------------------------------------------------------------------------ 1:30-3:30 pm SESSION 2: FAULT MODELING AND MANUFACTURING. An Analysis of (Linked) Addressed Decoder Faults, A. J. van de Goor and G. N. Gaydadjiev, (Delft University of Technology, The Netherlands). SRAM Yield Estimation in the Early Design Stage, V. Kim and T. Chen, (Colorado State Univeristy, USA). False Write Through and Un-Restored Write Electrical Level Fault Models for SRAMs, R. D. Adams and E. S. Cooley, (Dartmouth College, USA). A Defect-Tolerant DRAM Employing A Hierarchical Redundancy Scheme, Built-In Self-Test and Self-Reconfiguration, D. Niggemeyer, J. Otterstedt and M. Redeker, (Universitat Hannover, Germany). ------------------------------------------------------------------------ 3:30 - 4:00 pm BREAK ------------------------------------------------------------------------ 4:00 - 5:00 pm SESSION 3: TOOLS. Formal Verification of Memory Arrays Using Symbolic Trajectory Evaluation, M. Pandey and R. E. Bryant, (Carnegie Mellon University, USA). A Product Development Flow with Metrics for Memory Designs, S. Hegde, I. P. Pal and K. S. Rao, (Texas Instruments, India). -------------------------------------------------------------------------- 1997 WORKSHOP ON MTDT TECHNICAL PROGRAM Tuesday, August 12, 1997 ------------------------ -------------------------------------------------------------------------- 9:00 - 10:00 am SESSION 4: LOW POWER. A Low-Power High Storage Capacity Structure for GaAs MESFET ROM, R. Kanan, B. Hochet, M. Declercq (Swiss Federal Institute of Technology) and A. Guyot (INPG-TIMA, France). Use of Selective Precharge for Low-Power on the Match Lines of Content-Addressable Memories, C. Zukowski and S.-Y. Wang, (Columbia University, USA). ------------------------------------------------------------------------- 10:00 - 10:30 am BREAK ------------------------------------------------------------------------- 10:30 - 12:00 pm PANEL: Technology, Design and Test of Embedded DRAMs (organized by T. Wik, LSI Logic, USA). -------------------------------------------------------------------------- 12:00 - 1:30 pm LUNCH -------------------------------------------------------------------------- 1:30 - 3:30 pm SESSION 5: TEST. March 3N and March 4N Memory Tests, V. Yarmolik (Belarusian State University), Y. Klimets (Academy of Sciences, Belarus) and S. Demidenko (Singapore Polytechnic). An Open Notation for Memory Tests, A. Offerman and A. J. van de Goor, (Delft University of Technology, The Netherlands). Testing Memory Modules in SRAM-Based Configurable FPGAs, W. K. Huang, F. J. Meyer, N. Park and F. Lombardi, (Texas A&M University, USA). Memory Array Testing Through a Scannable Configuration, S.Yano (NEC Corporation, Japan) and N. Ishiura (Osaka University, Japan). -------------------------------------------------------------------------- 3:30 - 4:00 pm BREAK ------------------------------------------------------------------------- 4:00 - 5:00 pm SESSION 6: SENSING. A High-Speed Parallel Sensing Scheme for Multi-Level Non-Volatile Memories, C. Calligaro, A. Manstretta, G. Torelli, (University of Pavia, Italy) and R. Gastaldi (SGS Thomson,Italy). Differential Built-in Current Sensor (BICS) for Static RAMs: Implementation and Performance, S. M. Menon A. Nymoen (South Dakota School of Mines & Technology, USA). -------------------------------------------------------------------------- 5:00 pm CLOSING REMARKS -------------------------------------------------------------------------- WORKSHOP ORGANIZATION TECHNICAL PROGRAM CHAIR Thomas Wik LSI Logic, MS E-194 1501 McCarthy Blvd Milpitas CA 95035, USA 408/954-4471; trw@lsil.com GENERAL CHAIR Fabrizio Lombardi Computer Science MS 3112 Texas A&M University College Station TX 77843, USA 409/845-5464; fax 847-8578 lombardi@cs.tamu.edu PUBLICITY CHAIR Fred "Jackie" Meyer Computer Science MS 3112 Texas A&M University College Station TX 77843, USA 409/845-1014; fmeyer@cs.tamu.edu FINANCE CHAIR Duncan "Hank" Walker Computer Science MS 3112 Texas A&M University College Station TX 77843, USA 409/862-4387; fax 847-8578 walker@cs.tamu.edu STEERING COMMITTEE Rochit Rajsuman, Chair Equator Technologies, Inc. (408) 260-0599, ext. 337 rajsuman@equator.com Bernard Courtois, INPG/TIMA Grenoble, France Ad J. van de Goor, Delft University of Technology, The Netherlands Yervant Zorian, Logic Vision, Princeton NJ, USA PROGRAM COMMITTEE Abhaya Asthana, Lucent Technologies, Princeton NJ, USA Bruce Cockburn, University of Alberta, Edmonton AB, Canada Mike DePaolis, Lucent Technologies, Princeton NJ, USA Bob Evans, MosAid, San Jose CA, USA E. Fujiwara, Tokyo Institute of Technology, Tokyo, Japan Susanne Griep, Siemens AG, Munchen, Germany S. Horiguchi, Japan Advanced Institute of Science and Technology, Tatsunokuchi, Japan Swee Yong Khim, Texas Instruments, Singapore David Lepejian, HPL, Milpitas CA, USA Yashwant Malaiya, Colorado State University, USA P. Olivo, University of Bologna, Bologna, Italy Ritu Shrivastava, Alliance Semiconductor, San Jose CA, USA ======================================================================== 1997 WORKSHOP ON MTDT **** EARLY REGISTRATION DISCOUNT FORM **** MAIL or FAX form to: Dr. D. H. Walker Finance Chair 1997 W-MTDT Department of Computer Science Texas A&M University College Station TX 77843 USA Tel: (409) 862-4387 Fax: (409) 847-8578 Email: walker@cs.tamu.edu IMPORTANT: Read GENERAL INFORMATION, above, before completing this form. After July 31, register at the Workshop. (Registration-at-Hotel rates will apply.) First Name:____________________________________________ Last Name:_____________________________________________ Company:_______________________________________________ Mail Stop:_____________________________________________ St. Address/Box No.:___________________________________ City:_____________________________ State (US):_________ Zip Code (US):_____________ Country:___________________ Tel:_______________________Fax:________________________ E-mail:____________________IEEE Mmbr No.*:_____________ SPECIAL DIETARY REQUIREMENT: Vegetarian______ Other (specify)_______________________________ DISCOUNT REGISTRATION (available until July 31) TECHNICAL PROGRAM August 11-12 IEEE/CS Member* $270 _____ Non-Member $345 _____ ADDITIONAL Copies of MTDT 97 Proceedings pick up at symposium. Quan.___ @ $30 _____ TOTAL: $_______ * - IEEE/CS member rates are granted only if your current valid member number is filled in above. SEND FULL PAYMENT IN US$ WITH THIS FORM. Use a check drawn on a US bank, or a US bank credit card. PURCHASE ORDERS ARE NOT ACCEPTED. Make checks payable to: 1997 IEEE WORKSHOP ON MTDT. USE YOUR CREDIT CARD IF REGISTERING BY FAX. FOR CREDIT CARD PAYMENT: Check card type: VISA/MASTERCARD____________ AMERICAN EXPRESS___________ CARD NO.:_____________________ Exp. Date:______________ CARDHOLDER SIGNATURE:__________________________________ Advance registration fees will be refunded only on written request, mailed or fax'ed, and received by July 15, 1997. A $100 processing fee is charged for each refund. =========================================================== HOTEL ACCOMMODATION San Jose Hilton Hotel and Tower is located in Down Town San Jose. The Hotel provides courtesy shuttle from San Jose International Airport. HOTEL ADDRESS: 300 Almaden Blvd San Jose, CA 95110 Tel: (408) 287-2100, Fax: (408) 947-4488 Toll Free: 1-800-445-8667 RATES: Singe $125, Double $125 ($15 extra person) Towers Room $25 extra Suite $295 to $650 Participants should reserve the room directly with the hotel using the above numbers. The above discount rates are guaranteed if reservations are made before July 10, 1997. At the time of reservation, the name of the workshop (MTDT-97) must be identified. =========================================================== From codesign-request@ifi.unizh.ch Thu Aug 7 00:14:17 1997 Return-Path: Received: from imecgate.imec.be by josef.ifi.unizh.ch with SMTP (PP) id <23083-0@josef.ifi.unizh.ch>; Wed, 6 Aug 1997 23:32:34 +0200 Received: from unimec.imec.be (unimec) by imecgate.imec.be (5.65c/IDA-1.4.4-IMEC) id AA12877d; Wed, 6 Aug 1997 23:24:36 +0200 Original-Received: by unimec.imec.be Wed, 6 Aug 1997 23:24:34 +0200 PP-warning: Illegal Received field on preceding line From: Francky Catthoor Date: Wed, 6 Aug 1997 23:23:14 +0200 Message-Id: <199708062123.AA135212594@ambiorix.imec.be> Original-Received: by ambiorix.imec.be Wed, 6 Aug 1997 23:23:14 +0200 PP-warning: Illegal Received field on preceding line To: isss97@imec.be Subject: ISSS97 Status: RO X-Status: Dear colleague, the deadline for cheap registration (Aug.8) at ISSS is approaching rapidly! Note also that we have travel grants available for Ph.D. students. This year's program is again very exciting with 6 interesting invited speakers on topics covering formal verification, education for deep submicron age, compilers for embedded processors, (embedded) DRAM memories, system-level codesign in industry, and real-time software system methodologies. In addition to 18 high-quality papers, we also have 2 exciting panels, an entertaining banquet speech, and the traditional discussion topics where all the participants contribute. That mix should make ISSS interesting for both academic and industrial attendees. A web site has been installed with much more information still: http://www.imec.be/isss97/ There you can check for the latest ISSS'97 related info. We are looking forward to receiving your advance registration by August 8, 1997. *** Please register in time so that you can make use of the discount. *** Regards, Francky Catthoor (Program Chair-man) ------------------------------------------------------ 10TH INTERNATIONAL SYMPOSIUM ON SYSTEM SYNTHESIS (ISSS) ------------------------------------------------------ Antwerp, Belgium, September 17-19, 1997 ADVANCE PROGRAM ------------------------------------------------------ Sponsored by the IEEE Computer Society DATC and the ACM SIGDA (http://www.imec.be/isss97/) ***************** Important Dates ***************** Advance Registration Deadline : August 8, 1997 Hotel Reservation Deadline : August 15, 1997 On-Site Registration : September 16-17, 1997 ********** About ISSS ********** ISSS is a major international forum presenting emerging techniques for the system-level design and synthesis of computing systems. Having begun as the International Workshop on High-Level Synthesis in the mid-80's, it attracts leading design automation professionals from around the world. The growing acceptance of commercial synthesis tools, and the unified view of both hardware and software that such tools enable, have led to the symposium expanding to now cover system-level synthesis, hardware/software codesign, programmable (multi-)processor-based design, architectural and high-level synthesis, system-design experience and methodologies, embedded and real-time system software, synthesis for low power and testability and verifiability ISSS'97 is the 10th in this very successful series of symposia. It features 6 invited tutorial talks by leading industrial (Dr. Frank Gielen, Alcatel-Telecom; Dr. Roelof Salters, Philips; Dr. Richard Taylor, HP Labs) and academic experts (Prof. Hugo De Man, Prof. Gerry Musgrave, Prof. Alex Nicolau) on very timely and interesting topics related but not overlapping with the other ISSS activities. In addition, 2 panel sessions are organized on topics of active interest for the future of our community. ISSS'97 also features 18 high-quality papers selected from over 60 submissions. Paper presentations will consist of 20 minute talks followed by poster sessions, allowing ample time for discussion and interaction. On the first evening, a social event is planned. **************** Antwerp, Belgium **************** The symposium's location, Antwerp, is a city with a glorious past. Hometown of world famous artists who created here a unique pageant of history. Someone wandering round in Antwerp at the beginning of the 17th century would soon run into the best-known painters, sculptors, instrument makers and printers. Rubens worked together with Jordaens, van Dijck, Jan Bruegel and Erasmus II Quellinus, who illustrated books that were printed by Balthazar Moretus. All of these masters were at home in Antwerp. The Antwerp museums and churches are all richly endowed. Antwerp is art. Antwerp, a city with a rich and glorious present. The port: a whirlpool of activity. A diamond sector that has given the city a name and fame; the place to buy diamonds. The Diamond Museum explains the whole process, from mining to brilliant jewelry. The Antwerp Zoo is world famous. Antwerp, a bustling and hospitable metropolis. With terraces, pubs and restaurants, museums, movies, theatre, dance, music and modern art, a large city on a small scale. It is easily accessible by air (Brussels airport is 30 minutes away), train and car. ****************** Technical Program ****************** --------------------------- Tuesday, September 16, 1997 --------------------------- 18:00 - 20:00 Registration 19:00 - 21:00 Reception ----------------------------- Wednesday, September 17, 1997 ----------------------------- 8:30-12:00 Registration 9:00 Opening Session & Invited Talk ----------------------------- o Opening & Welcoming remarks Frank Vahid, UC Riverside, CA, USA o "Formal Verification: The Enabling or the Handicapping Process?" Gerry Musgrave, Brunel University, UK 10:30 Session 1 : Formal specification and validation ----------------------------------------------- Chair: Lev Markov, Mentor Graphics, Wayland MA, USA 1.1 Quick Conservative Causality Analysis Ellen Sentovich, Cadence Berkeley Labs, CA, USA 1.2 An Efficient Representation for Formal Synthesis Christian Blumenroehr, Dirk Eisenbiegler, Univ. Karlsruhe, Germany 1.3 Derivation of Formal Representations from Process-based Specification and Implementation Models Steven Vercauteren, Diederik Verkest, IMEC, Belgium Gjalt de Jong, Alcatel Telecom, Belgium Bill Lin, U.C. San Diego CA, USA 12:00 Lunch 13:30 Panel Discussion ---------------- "Where is Fast Prototyping Heading ?" Organizer: Rudy Lauwereins, Univ. of Leuven, Belgium Panel Members: Nick Kanopoulos, DCT, Research Triangle Park, North Carolina, USA Rudy Lauwereins, Univ. of Leuven, Belgium Ian Page, University of Oxford, Oxford, UK Peter Pirsch, Univ. of Hannover, Germany Stefaan Note, Philips ITCL, Leuven, Belgium Kees Vissers, Philips Natlab, Eindhoven, The Netherlands 15:00 Session 2 : Fast prototyping and code generation ------------------------------------------------ Chair: Kees Vissers, Philips Research, The Netherlands 2.1 Prototyping of the Receiver Unit for a Broadband Access Network Axel Hein, Josef Dalcolmo, Patrick Le Corre, Rudy Lauwereins, Marleen Ade, Univ. of Leuven, Belgium 2.2 Constraint Analysis for DSP Code Generation Bart Mesman, Marino Strik, Adwin Timmer, Jef van Meerbergen, Philips Research, The Netherlands Jochen Jess, Eindhoven Univ. of Technology, The Netherlands 2.3 An Efficient Model for DSP Code Generation: Performance, Code Size, Estimated Energy Cathy Gebotys, Univ. of Waterloo, Ontario, Canada 16:30 Invited Talk ------------ "Education for the Deep Submicron Age : Business as Usual?" Hugo De Man, Univ. of Leuven and IMEC, Belgium 17:30 Social event: guided beer tour in Antwerp ---------------------------- Thursday, September 18, 1997 ---------------------------- 8:30 Invited Talk ------------ "True State-of-the-art Compilers: Instruction-level Parallelism and Speculation Exploitation" Alexandru Nicolau, U.C.Irvine, CA, USA 9:30 Session 3 : Novel compilation and optimization issues ----------------------------------------------------- Chair: Rolf Ernst, Technical Univ. Braunschweig, Germany 3.1 Embedded System Synthesis by Timing Constraint Solving Krzysztof Kuchcinski, Linkoeping Univ., Sweden 3.2 Reducing the Complexity of ILP Formulations for Synthesis Anne Mignotte, Olivier Peyran, Ecole Normale Superieure de Lyon, France 3.3 A New Optimization Technique for Improving Resource Exploitation and Critical Path Minimization Birger Landwehr, Peter Marwedel, Univ. of Dortmund, Germany 11:00 Focus Group ----------- Workshop discussions involving all attendees 12:00 Lunch 13:30 Invited Talk ------------ "Embedded Memories and Embedded Logic" Roelof Salters, Philips Research, The Netherlands 14:30 Session 4 : Memory management issues ------------------------------------ Chair: Paul Lippens, Philips Research, The Netherlands 4.1 Fast and Extensive System-level Memory Exploration for ATM Applications Peter Slock, Sven Wuytack, Francky Catthoor, IMEC, Belgium Gjalt de Jong, Alcatel Telecom, Belgium 4.2 Optimization of the Background Memory Utilization by Partitioning Uwe Eckhardt, Renate Merker, Technical Univ. Dresden, Germany 4.3 Architectural Exploration and Optimization of Local Memory in Embedded Systems, Preeti Panda, Nikil Dutt, Alexandru Nicolau, U.C.Irvine CA, USA 16:00 Panel Discussion ---------------- How will Memory Issues Impact Synthesis for Embedded Systems-on-Silicon? Organizer: Nikil Dutt, U.C.Irvine CA, USA Panel Members: Paul Lippens, Philips, The Netherlands Vijay Nagasamy, VSIS, USA Roelof Salters, Philips, The Netherlands Norbert Wehn, Siemens, Germany Sven Wuytack, IMEC, Belgium 18:30 Banquet with dinner talk: ``How to succeed in CAD'', Dan Gajski, UC Irvine -------------------------- Friday, September 19, 1997 -------------------------- 8:30 Invited Talk ------------ "System-level Codesign : A New Industrial Revolution" Richard Taylor, Hewlett-Packard Labs, Bristol, UK 9:30 Session 5 : System-Level Synthesis and Design --------------------------------------------- Chair: Sanjiv Narayan, Ambit Design Systems, CA, USA 5.1 Optimization Method for Broadband Modem FIR Filter Design using Common Subexpression Elimination, Robert Pasko, Daniela Durackova, Slovak Technical Univ, Slovakia Patrick Schaumont, Veerle Derudder, IMEC, Belgium 5.2 Port Calling: A Transformation for Reducing I/O during Multi-Package Functional Partitioning, Frank Vahid, UC Riverside, CA, USA 5.3 A Scheduling and Pipelining Algorithm for Hardware/Software Systems Smita Bakshi, Daniel Gajski, U.C.Irvine CA, USA 11:00 Focus Group ----------- Continuation 12:00 Lunch 13:30 Invited Talk ------------ "SDL Methodology for Real-Time Software Systems" Frank Gielen, Alcatel Telecom, Belgium 14:30 Session 6 : HW/SW specification and debugging --------------------------------------------- Chair: Bob Walker, Kent State Univ., OH, USA 6.1 Co-Emulation and Debugging of HW/SW-Systems Gernot Koch, Udo Kebschull, Wolfgang Rosenstiel, Univ. Karlsruhe, Germany 6.2 Synthesising Controllers from Real-Time Specifications Henning Dierks, Univ. of Oldenburg, Germany 6.3 A Source-level Dynamic Analysis Methodology and Tool for High-level Synthesis Chih-Tung Chen, Kayhan Kucukcakar, Motorola Inc., Tempe AZ, USA 16:00 Future Directions and Closing 17:00 Symposium Ends ******************** Hotel Information ******************** Make reservations directly with the Park Lane Hotel, Antwerp, mentioning ISSS'97 to obtain the special low rates. Rates are guaranteed until August 26, 1997 after which reservations will be based on availability. Address: -------- Park Lane Hotel Van Eycklei 34, 2018 Antwerp, Belgium http://www.parklane.be/parklane/ e-mail: info@parklane.be Tel: +32 (3) 285 85 85 Fax: +32 (3) 285 85 86 Rates: ------ 4950 BFr (about $140 with current conversion rate) This includes breakfast and tax and all hotel services The same price applies for single or double occupancy *************************** Registration Information *************************** To register, please fill in the registration form and arrange a direct payment (free of any bank charges) on the account number: 005-4359248-60, mentioning ISSS97 p/a IMEC. The SWIFT code is: CGAKBEBB. The bank is: ASLK, Naamse steenweg 163, 3001 Leuven Belgium. If you cannot arrange it free of charges from your bank, make certain that you transfer 14$ extra on top of the rates mentioned below (this is the average charge which our bank will remove). Mail the completed form to: Annemie Stas, ISSS'97 IMEC Kapeldreef 75, 3001 Leuven, Belgium Alternatively (preferably not) you can enclose the appropriate fee in the form of a check (payable to "ISSS'97") in US dollars which can be drawn on a Belgian bank. In this case, you should add 17$ extra to compensate for the costs which the bank charges us to cash it. The advance registration fee must be received by August 8, 1997. Written requests for refunds should be made prior to this date. After September 1, 1997, all registrations will be processed only at the conference site. Registrations cannot be accepted over phone, fax, email, or through credit-cards. The conference fee includes all social events, lunches and breaks. For further information, contact Annemie Stas at annemie@imec.be Tel: +32 (16) 281-200; Fax: +32-16-281-515 For students, a number or travel fellowships are available (of about 300$), sponsored by Alcatel Telecom, Antwerp. Information is (and will be) made available at the ISSS'97 web page under registration. If you wish to apply for these fellowships, please send or e-mail a letter of request with motivation of why you need support to Francky Catthoor at catthoor@imec.be, IMEC, Kapeldreef 75, 3001 Leuven, Belgium ********************** Symposium Proceedings ********************** The symposium proceedings will be published by IEEE CS Press but will also be available from ACM. Extra copies of the proceedings can be ordered from: Customer Service Department IEEE Computer Society Press 10662 Los Vaqueros Circle P.O. Box 3014 Los Alamitos, California 90720 Tel: (714) 821-8380 Fax: (714) 821-4641 Email: cs.books@computer.org ------------------------- cut here -------------------------------- ISSS'97 Registration Form *************************** By August 8 1997 After August 8, 1997 ----------------- -------------------- ACM/IEEE Members $ 330 $ 400 Non-Members $ 420 $ 490 Full-time Students $ 300 $ 330 Name : __________________________________ Affiliation : __________________________________ Address : __________________________________ __________________________________ __________________________________ Phone : ___________________ Fax : ___________________ Email : ___________________ Special needs : _________________ Total Amount Enclosed : US $ ____________ (or transferred to the above mentioned account) ACM/IEEE Membership # : _________________ (reqd. if registering at ACM/IEEE rates) ------------------------- cut here -------------------------------- *********************** Organizing Committee *********************** General Chair: Frank Vahid, UC Riverside Program Chair: Francky Catthoor, IMEC Publications Chair: Edwin Sha, Univ. Notre Dame Publicity Chair: Diederik Verkest, IMEC Panels Chair: Rudy Lauwereins, Univ. of Leuven Past Chair: Ahmed Jerraya, TIMA-CNRS, Grenoble Finance Chair: Annemie Stas, IMEC Technical Program Committee --------------------------- Marleen Ade, Univ. of Leuven Gaetano Borriello, Univ. Washington Raul Camposano, Synopsys Nikil Dutt, UC Irvine Rolf Ernst, Tech. Univ. Braunschweig Daniel Gajski, UC Irvine Cathy Gebotys, Univ. Waterloo Yu-Chin Hsu, Avant! Kayhan Kucukcakar, Motorola Fadi Kurdahi, UC Irvine Steve YL Lin, Tsing Hua Univ. Paul Lippens, Philips Jan Madsen, Tech. Univ. Denmark Lev Markov, Mentor Graphics Peter Marwedel, Univ. Dortmund Vijay Nagasamy, VSIS Inc. Yukihiro Nakamura, Kyoto Univ. Sanjiv Narayan, Ambit Design Systems Kevin O'Brien, Leda Pierre Paulin, SGS-Thomson Wolfgang Rosenstiel, Univ. Tubingen, FZI Edwin Sha, Univ. Notre Dame Leon Stok, IBM Donald Thomas, CMU Kazutoshi Wakabayashi, NEC Robert Walker, Kent State Univ. Wayne Wolf, Princeton ------------------------------------------------------------------------------- ** Sponsored by the IEEE Computer Society (DATC) and the ACM SIGDA ** ------------------------------------------------------------------------------- From codesign-request@ifi.unizh.ch Wed Aug 20 12:47:40 1997 Return-Path: Received: from imag.imag.fr by josef.ifi.unizh.ch with SMTP (PP) id <04092-0@josef.ifi.unizh.ch>; Wed, 20 Aug 1997 12:47:28 +0200 Received: from verdon.imag.fr (verdon.imag.fr [147.171.129.20]) by imag.imag.fr (8.8.1/8.8.5) with ESMTP id MAA27343; Wed, 20 Aug 1997 12:47:07 +0200 (MET DST) Received: (from jerraya@localhost) by verdon.imag.fr (8.6.11/8.6.9) id MAA12125; Wed, 20 Aug 1997 12:46:19 +0200 Date: Wed, 20 Aug 1997 12:46:19 +0200 From: Ahmed Amine Jerraya Message-Id: <199708201046.MAA12125@verdon.imag.fr> X-Mailer: Mail User's Shell (7.2.5 10/14/92) To: isss-people@ics.uci.edu, codesign@ifi.unizh.ch, codesign@vhdl.org Subject: CODES/CASHE'98 Status: RO X-Status: PRELIMINARY CALL FOR PARTICIPATION 6th International Workshop on Hardware/Software Co-Design Codes/CASHE '98 Seattle, Washington - 15-18 March 1998 Sponsored by (pending) : IEEE Computer Society, IEEE CAS, IFIP 10.5, ACM/SIGDA, ACM/SIGSOFT. Electronic Submission by: 16 December 1996 Notyfication by : 20 January 1997 The Codes/CASHE (Computer Aided Software/Hardware Engineering) workshop is the major international forum for the presentation and exchange of ideas in this field. It covers all aspects of the specification, design, construction, and verification of embedded systems that include functionality mapped to both hardware and software components. Presentations and discussions address theoretical aspects, design methods, tools, and case studies. The meeting is structured so as to promote active discussion between all participants in an informal setting. This is accomplished via short oral presentations of accepted papers combined with poster sessions to provide the opportunity to investigate and discuss the ideas in depth. Group discussions will be selected based on submitted proposals and/or based on the interests of the participants. In order to focus on new research directions and on-going research, submissions to the workshop are due only three (3) months before the meeting and should be sent electronically according to the directions on the reverse side of this call. Submissions for the combined oral presentation and poster should be no longer than 5 pages. These same materials will be provided to the participants in the form of a proceedings (there will not be time to ask authors to submit a revised copy). In addition, submitters may also provide a URL for additional information related to their work or project residing on their web sites. The web site for the meeting will include the URLs provided by all accepted presentations in the final program. Publication of presentations in the proceedings is voluntary. The authors of accepted papers will be asked to submit slides two weeks before the workshop, so that they can be made available to the attendees. Proposals for group discussions are also highly welcome and should take the form of no more than 2 pages highlighting the problem to be addressed in the discussion, the motivation for the topic with suggestions for problems or issues to be addressed, and a potential discussion moderator or panel. To allow preparation for group discussions, the accepted discussion proposals will be made available to attendees via the workshop web sites in conjuction with the final program. Areas of interest include, but are not limited to: 1. Computer-aided techniques for HW/SW co-design Specification languages and modeling techniques, design representations, simulation and validation, formal verification, emulation and physical prototyping, synthesis approaches, system-level design. 2. Target architectures Distributed and multiprocessor architectures for embedded systems, HW/SW interfaces and communication methods, heterogeneous system design, flexible architectures, embedded system design, case studies. 3. Software for HW/SW co-design Software development environments, real-time operating systems, distributed systems, process scheduling and other concurrency management techniques, software synthesis approaches, portability of specifications, system integration, testbenches and testing, retargetable compilation. 4. System development process Concurrent engineering, design re-use, design space exploration, design process management, partitioning, estimation, device libraries, and component models. SUBMISSION PROCEDURE The submission procedure is to send an electronic mail message based on the following template: Subject: CODES98 submission Submission-type: {paper or group-discussion} Related-URL: {a URL pointing to related work} Include-in-proceedings: {YES or NO} Number-of-pages: {total number of pages in the postscript file below} Keywords: {up to 3 key words or phrases describing the work} {uuencoded postscript file} to codes98@polv2k.polito.it by 7 December 1997. The receipt of the message will be immediately acknowledged electronically. Notification of acceptance will be sent to the same e-mail address from which the submission was sent by 20 January 1998. WORKSHOP INFORMATION Workshop web sites in North America and Europe are: http://www.cs.washington.edu/research/codes98/ http://polimage.polito.it/codes98/ Check the web sites regularly for workshop announcements and logistics information. For further information or clarifications send e-mail to: codes98@cs.washington.edu. General Chair Program Co-chairs Gaetano Borriello Ahmed Amine Jerraya Luciano Lavagno Dept. of Computer System Level Synthesis Group Dipartimento di Elettronica Science and Engineering University of Washington TIMA Laboratory Politecnico di Torino Box 352350 46 Avenue Felix Viallet Corso Duca degli Abruzzi 24 Seattle, WA 98195-2350 [USA] F-38031 Grenoble Cedex, FRANCE I-10129, Torino, ITALY Tel: +1 (206) 685-9432 Tel: +33 476 574 759 Tel: +39 11 564-4150 Fax: +1 (206) 543-2969 Fax: +33 476 473 814 Fax: +39 11 564-4099 Email:gaetano@cs.washington.edu Email:ahmed.jerraya@imag.fr Email:lavagno@polito.it Technical Program Committee Brian Bailey, Mentor Graphics, USA Jim Beck, Delco, USA Tarek Ben-Ismail, HP Labs, Bristol, UK Ivo Bolsens, IMEC, B Gaetano Borriello, Univ. of Washington, USA Joseph Buck, Synopsys, USA Raul Camposano, Synopsys, USA Carlos Delgado-Kloos, University of Madrid, E Giovanni De Micheli, Stanford University, USA Martyn Edwards, University of Manchester (UMIST), UK Rolf Ernst, University of Braunschweig, D Thomas Fuhrman, General Motors, USA Daniel Gajski, Univ. of Calif. at Irvine, USA Rajesh Gupta, Univ. of Calif. at Irvine, USA Ahmed Jerraya, TIMA Laboratory, Grenoble, F Timothy Kam, INTEL Oregon, USA Kurt Keutzer, Synopsys, USA Sanjaya Kumar, Honeywell, USA Philip Koopman, Carnegie-Mellon Univ., USA Luciano Lavagno, Politecnico di Torino, I Jan Madsen, Technical Univ. of Denmark, DK Franz Rammig, C-Lab, University of Paderborn, D Wolfgang Rosenstiel, Univ. of Tubingen, D James Rowson, Cadence, USA Alberto Sangiovanni-Vincentelli, Miguel Santana, SGS-Thompson, F UC Berkeley, USA Donatella Sciuto, Politecnico di Milano, I Don Thomas, Carnegie-Mellon University, USA Frank Vahid, Univ. of Calif. at Riverside, USA Kees Vissers, Philips, NL Wayne Wolf, Princeton University, USA Hiroto Yasuura, Kyushu University, Japan -- ------------------- PLEASE NOTE THE CHANGEs IN PHONE AND FAX NUMBERS ------ Ahmed Amine JERRAYA, Ph. D | Office: (+33) 476 574 759 ------ System-Level Synthesis Group | Home : (+33) 476 096 014 ------ TIMA/INPG 46 Ave Felix Viallet | Fax : (+33) 476 473 814 ------ F-38031 Grenoble Cedex FRANCE | E_mail: ahmed.jerraya@imag.fr From codesign-request@ifi.unizh.ch Thu Aug 21 21:41:36 1997 Return-Path: Received: from imag.imag.fr by josef.ifi.unizh.ch with SMTP (PP) id <11467-0@josef.ifi.unizh.ch>; Thu, 21 Aug 1997 21:41:28 +0200 Received: from verdon.imag.fr (verdon.imag.fr [147.171.129.20]) by imag.imag.fr (8.8.1/8.8.5) with ESMTP id VAA20797; Thu, 21 Aug 1997 21:41:01 +0200 (MET DST) Received: (from jerraya@localhost) by verdon.imag.fr (8.6.11/8.6.9) id VAA28844; Thu, 21 Aug 1997 21:40:17 +0200 Date: Thu, 21 Aug 1997 21:40:17 +0200 From: Ahmed Amine Jerraya Message-Id: <199708211940.VAA28844@verdon.imag.fr> In-Reply-To: Ahmed Amine Jerraya's message of Aug 20, 12:46pm X-Mailer: Mail User's Shell (7.2.5 10/14/92) To: Ahmed Amine Jerraya , isss-people@ics.uci.edu, codesign@ifi.unizh.ch, codesign@vhdl.org Subject: Re: CODES/CASHE'98 Status: RO X-Status: Dear Collegues, Please note that Deadlines for CODES/CASHE are: Electronic Submission by: 16 December 1997 (and not 1996) Notyfication by : 20 January 1998 (and not 1997) Regards Ahmed -- ------------------- PLEASE NOTE THE CHANGEs IN PHONE AND FAX NUMBERS ------ Ahmed Amine JERRAYA, Ph. D | Office: (+33) 476 574 759 ------ System-Level Synthesis Group | Home : (+33) 476 096 014 ------ TIMA/INPG 46 Ave Felix Viallet | Fax : (+33) 476 473 814 ------ F-38031 Grenoble Cedex FRANCE | E_mail: ahmed.jerraya@imag.fr From codesign-request@ifi.unizh.ch Tue Sep 16 10:31:48 1997 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <10769-0@josef.ifi.unizh.ch>; Tue, 16 Sep 1997 10:31:39 +0200 Return-Path: X-Received: from clavin.cs.tamu.edu by josef.ifi.unizh.ch with SMTP (PP) id <24058-0@josef.ifi.unizh.ch>; Mon, 15 Sep 1997 17:56:34 +0200 X-Received: from chipmonks.cs.tamu.edu (233@chipmonks [128.194.146.168]) by cs.tamu.edu (8.8.7/8.8.7) with ESMTP id KAA08719 for ; Mon, 15 Sep 1997 10:54:18 -0500 (CDT) From: Fabrizio Lombardi X-Received: (from lombardi@localhost) by chipmonks.cs.tamu.edu (8.8.7/8.8.7) id KAA28451 for codesign@ifi.unizh.ch; Mon, 15 Sep 1997 10:53:35 -0500 (CDT) Date: Mon, 15 Sep 1997 10:53:35 -0500 (CDT) Message-Id: <199709151553.KAA28451@chipmonks.cs.tamu.edu> To: codesign@ifi.unizh.ch Subject: Call for Papers ReSent-Date: Tue, 16 Sep 1997 10:25:39 +0200 (MET DST) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Message-ID: Status: RO X-Status: Call for Papers Annual IEEE Workshop on Fault-Tolerant Parallel and Distributed Systems April 1, 1998, Delta Orlando Resort Orlando, Florida USA Held in conjunction with the 12th International Parallel Processing Symposium (http://netcom1.bu.edu/FTPDS98_workshop.html) March 30 - April 3, 1998 Workshop Chairman: Dimiter Avresky, Boston University Workshop Vice-Chairman: David R. Kaeli, Northeastern University Theme Increasingly large parallel computing systems provide unique challenges to the researchers in dependable computing, especially because of the high failure rates intrinsic to these systems. While commercial and scientific companies share the need for massive throughput and low latency, dependability of service is also a concern. In addition to providing uninterrupted service, commercial systems must be free from data corruption. Achieving dependability in highly scalable parallel and distributed systems poses a considerable challenge. As the number of components increases, so does the probability of a component failure. Therefore, improved fault-tolerant technology is required for high scalable parallel and distributed systems. The goal of this workshop is to provide a forum for researchers and practitioners to discuss issues related to these issues of fault-tolerant parallel and distributed systems. All aspects of design, theory and realization of parallel and distributed systems are of interest. Topics of interest include, but are not limited to: - Dependable Distributed Systems - Fault-tolerance in clusters of workstations - Fault-tolerant interconnection networks - Reconfigurable fault-tolerant parallel and distributed systems - Fault-tolerant parallel programming - Scalable fault-tolerant architectures and algorithms - Fault injection in parallel and distributed systems - Dependability evaluation of fault-tolerant parallel and distributed systems Program Committee: J. Bruck, Caltech, USA S. Budkowski, INT, France B. Ciciani, University of Roma, Italy F. Cristian U.C. San Diego, USA A. Goyal IBM Watson Research Center, USA J. Hayes University of Michigan, Ann Arbor, USA R. Horst, Tandem Computers Inc., USA M. Karpovsky, Boston University, USA H. Levendel, Lucent Tech., Bell Labs Innovations, USA Q. Li, Santa Clara University, CA, USA F. Lombardi, Texas A&M, USA E. Maehle, University of Lubeck, Germany K. Makki, University of Nevada, Las Vegas, USA M. Malek, Humboldt University, Germany A. Nordsieck, Boeing, USA J.Hauser, Sun Microsystems, USA N. Pissinou, CACS, USE, USA M. Raynal, IRISA, France R. Riter, Boeing, USA B. Smith, IBM Watson Research Center, USA K. Siu, MIT, USA K. Trivedi, Duke University, USA J. Wu, University of Florida, USA The workshop is sponsored by the IEEE Computer Society Techical Committee on Parallel Processing. For further information, please contact one of the following: D. R. Avresky Dept. of El. and Computer Eng. Boston University 8, Saint Mary's st. Boston, MA 02215 phone: (617)- 353-9850 fax:(617)- 353-6440 e-mail : avresky@bu.edu D. R. Kaeli Dept. of El. and Comp. Eng. Northeastern University Boston, MA 02115 phone: (617)-373-5413 fax: (617) -373-8970 email: kaeli@ece.neu.edu To submit papers, send six copies of a manuscript (at most 20 pages long including figures and references) desribing original unpublished research to D.R.Avresky by October 1, 1997. The authors of selected papers will be invited by November 15, 1997 to submit papers. The papers will be published by the IEEE Computer Society. Camera-ready papers due by December 15, 1997. For more information , see the FTPDS98 homepage at : http://netcom1.bu.edu/FTPDS98_workshop.html From codesign-request@ifi.unizh.ch Tue Sep 16 10:46:21 1997 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <10804-0@josef.ifi.unizh.ch>; Tue, 16 Sep 1997 10:32:44 +0200 Return-Path: X-Received: from epsilon.ece.nwu.edu by josef.ifi.unizh.ch with SMTP (PP) id <06530-0@josef.ifi.unizh.ch>; Tue, 16 Sep 1997 06:10:13 +0200 X-Received: (from daemon@localhost) by epsilon.ece.nwu.edu (8.8.5/8.8.3) id RAA18808 for ; Mon, 15 Sep 1997 17:11:26 -0500 (CDT) X-Received: from seattle.ece.nwu.edu(129.105.5.174) by epsilon.ece.nwu.edu via smap (V2.0beta) id xma018802; Mon, 15 Sep 97 17:11:08 -0500 X-Received: (from hauck@localhost) by seattle.ece.nwu.edu (8.8.5/8.8.3) id RAA12486 for fpga97; Mon, 15 Sep 1997 17:11:08 -0500 (CDT) Date: Mon, 15 Sep 1997 17:11:08 -0500 (CDT) From: Scott Alan Hauck Message-Id: <199709152211.RAA12486@seattle.ece.nwu.edu> To: fpga97@seattle.ece.nwu.edu Subject: FPGA'98: Papers due 9/26 ReSent-Date: Tue, 16 Sep 1997 10:26:39 +0200 (MET DST) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Message-ID: Status: RO X-Status: FPGA `98 Call for Papers 1998 Sixth ACM International Symposium on Field-Programmable Gate Arrays DoubleTree Hotel, Monterey, California February 22-25, 1998 http://www.ece.nwu.edu/~hauck/fpga98 ========================================================== As Field-Programmable Gate Arrays become more essential to the design of digital systems there is increased pressure to improve their performance, density and automatic design. This symposium follows the largest ever gathering of this kind last year in Monterey at FPGA `97. For FPGA `98, we are once again soliciting submissions describing novel research and development in one or more of the following (or similar related) areas of interest: FPGA architecture: logic block & routing architectures, I/O structures and circuits, new commercial architectures. CAD for FPGAs: placement, routing, logic optimization, technology mapping, system level partitioning, testing and verification. Interactions: between CAD, architecture, applications, and programming technology. Fast prototyping: for System level design, Multi-Chip Modules. Applications: use of FPGAs in novel circuits, as emulators and compiled accelerators. Field-programmable interconnect chips and devices (FPIC/FPID.) FPGA-based compute engines. Field-programmable analog arrays. ========================================================== Authors should submit 20 copies of their paper (12 pages maximum) by September 26, 1997. Notification of acceptance will be sent by December 1, 1997. The authors of the accepted papers will be required to submit the final camera ready copy by December 15, 1997. A proceedings of the accepted papers will be published by ACM, and included in the ACM/SIGDA CD-ROM publications. All submissions should be sent to: Sinan Kaptanoglu FPGA `98 Actel Corporation 955 East Arques Avenue, Sunnyvale, CA 94086 USA e-mail:sinan@actel.com phone: (408) 522-4319 fax: (408) 522-8041 ========================================================== General Chair: Jason Cong, UCLA, Financial Chair: Carl Ebeling, U. of Washington, Program Chair: Sinan Kaptanoglu, Actel, Publicity Chair: Scott Hauck, Northwestern U. ============================ Technical Program Committee: ============================ Michael Butts, Quickturn Jason Cong, UCLA Eugene Ding, Lucent Carl Ebeling, U. of Washington Scott Hauck, Northwestern U. Dwight Hill, Synopsys Brad Hutchings, BYU Sinan Kaptanoglu, Actel David Lewis, U. of Toronto Fabrizio Lombardi, Texas A&M Jonathan Rose, U. of Toronto Rob Rutenbar, CMU Malgorzata Marek-Sadowska, UCSB Gabriele Saucier, IMAG Martine Schlag, UCSC Tim Southgate, Altera Steve Trimberger, Xilinx John Wawrzynek, UCB Martin Wong, UT at Austin ============================================================================ Sponsored by ACM SIGDA, with support from Actel, Xilinx, Altera, and Lucent. ============================================================================ From codesign-request@ifi.unizh.ch Wed Sep 17 09:11:22 1997 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <09667-0@josef.ifi.unizh.ch>; Wed, 17 Sep 1997 09:11:03 +0200 Return-Path: <@uklirb.informatik.uni-kl.de:abakus@informatik.uni-kl.de> X-Received: from news.uni-kl.de by josef.ifi.unizh.ch with SMTP (PP) id <21518-0@josef.ifi.unizh.ch>; Tue, 16 Sep 1997 16:37:32 +0200 X-Received: from uklirb.informatik.uni-kl.de by news.uni-kl.de id gp20862; 16 Sep 97 16:37 MET DST X-Received: from irz1.informatik.uni-kl.de by uklirb.informatik.uni-kl.de id aa12871; 16 Sep 97 16:31 MET DST X-Received: by irz1.informatik.uni-kl.de (SMI-8.6/SMI-SVR4) id QAA15719; Tue, 16 Sep 1997 16:31:46 +0200 From: AG Hartenstein-UNI KL-FRG Message-Id: <199709161431.QAA15719@irz1.informatik.uni-kl.de> Subject: CfP: Reconfigurable Architectures Workshop RAW-98 To: pilz@ifi.unizh.ch Date: Tue, 16 Sep 1997 16:31:46 +0200 (MET DST) X-Mailer: ELM [version 2.4 PL24] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit ReSent-Date: Wed, 17 Sep 1997 09:05:01 +0200 (MET DST) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Message-ID: Status: O X-Status: ------------------------------------------------------------------------------ R e c o n f i g u r a b l e A r c h i t e c t u r e s C A L L F O R P A P E R S 5th Reconfigurable Architectures Workshop (RAW-98) March 30, 1998, Orlando, Florida, USA to be held in conjunction with 12th International Parallel Processing Symposium (IPPS-97) and 9th Symposium on Parallel and Distributed Processing (SPDP-98) (Sponsored by IEEE Technical Committee on Parallel Processing) http://www.ippsxx.org/ipps98/index.html Workshop Co-Chairs: Peter M. Athanas, Virginia Tech Reiner W. Hartenstein, University of Kaiserslautern This workshop is the 5th one in a series held at Cancun, Mexico (1994), Santa Barbara, California (1995), Honolulu, Hawaii (1996) and Geneva, Switzerland (1997). RAW-98 is part of the first merged Symposium IPPS/SPDP 1998, being held March 30 - April 3, 1998 at Delta Orlando Ressort, Orlando, Florida, USA. RAW-98 will be held at March 30, the first day of IPPS/SPDP-98. RAW-98 is one of the 12 specialized workshops held at the first or last day of IPPS/SPDP-98. See http://xputers.informatik.uni-kl.de/RAW/RAW98.html Goals and Visions of the Workshop The recent decade has witnessed enormous technological advances, a deeper appreciation of the power of the use of reconfigurable technology platforms, and a better understanding of computing in time and in space. The methodology of reconfigurable circuits and systems is evolving from a tinkertoy approach to an: Innovative Parallel Computing Paradigm. The building of reconfigurable systems can only be achieved by building on the experience in different areas, and close interaction between them to identify and solve the remaining problems. The primary objective of this workshop is to provide opportunity for creative interaction between researchers actively involved in the fabrication, design, applications and enabling technologies of reconfigurable architectures. Scope of the Workshop The workshop will feature several sessions of submitted paper presentations and proceedings will be available at the symposium and by public ftp. Authors are invited to submit manuscripts which demonstrate original and on-going research in areas of Reconfigurable Architectures, implementations, algorithms and applications. The topics of interest include, but are not limited to: Reconfigurable Systems + Reconfiguration Models + Implementations + Systems Complexity + Scalable Programmable Logic - Architectures - Technology - CAD tools - Applications + Evolvable and Adaptable Systems + Reconfigurable Custom Computing Machines + Reconfigurable Accelerators and their Applications Applications + Problem Solving Paradigms + Image Processing + Geographic Information Systems + Graphics and Animation + Algorithms (arithmetic/geometric/graph/numerical/randomised) + Industrial applications and experiences Bridging the Gap + Software to Hardware Migration for Speed-up + Run Time to Compile Time Migration for Speed-up + Hardware/Software Co-Design using reconfigurable devices + Profiling and Hardware / Software Partitioning + New Paradigms and Basic Research Aspects Development Tools and Methods + High-level Development Support + Reconfiguration from Programming Language Sources + Innovative Compilation Techniques + Adapting Parallelizing Compilation Techniques for Structural Programming + Benchmarks for Reconfigurable Hardware Curricula + introducing structural programming in CS curricula + introducing reconfigurable architectures and technology platforms in CS&E curricula + lab courses integrating structural and procedural programming + educational experiences on reconfigurable systems + experiences in hardware / software co-education Join the Paradigm Switch! We are witnessing the beginning of a paradigm change. Hardware has become soft. A second world of programming joins the traditional procedural programming: the world of structural programming. In the long term this will revolutionize the entire computing science. The mainly procedurally oriented traditional computing science will end up in a duality of computing in time and computing in space. The crystalization point of this overlap is already here. It is the area of systolic array synthesis, where time and space appear within the same formula, and, which provides first mappings between both worlds. (Systolic arrays stress computing in space, because the locality of an operation in a particular PE is a central concept. In classical parallel computing (except SIMD and similar) locality is not interesting, since processors have addresses.) This is just the beginning. You are encouraged to submit your cool ideas, your hot implementations, and your exciting visions - to accelerate this march to new horizons. Bridging the Gap Until recently the populations of the R&D scene of parallel computing or high performance computing on one side, and the scenes dealing with reconfigurable hardware platforms have been non-overlapping. But both populations have the same goal: high performance by parallelism. Until recently calls for papers and participants on reconfigurable platforms, systems, and applications attracted only hardware experts. Most of them practice hardware / software co-design: linking structurally programmed accelerator hardware to traditional software running on a procedurally programmed host system. But high performance people, supercomputing people, parallel computing people, etc. went only to their own conferences. Until recently only a few of them had heard anything about FPGAs and other reconfigurable platforms and how to use them for speed-up. The time has come to bridge that gap: we need your help. Program Committee + Peter Athanas, Virginia Tech (USA) + Don Bouldin, University of Tennessee (USA) + Klaus Buchenrieder, Siemens Research (D) + Steven Casselman, Virtual Computer Corp. (USA) + Pak Chan, University of California Santa Cruz (USA) + Bernard Courtois, Univ. Grenoble (F) + Hossam Elgindy, Univ. of Newcastle (AUS) + Rolf Ernst, Univ. Braunschweig (D) + Masahiro Fujita, Fujitsu Labs. (USA) + Manfred Glesner , TH Darmstadt (D) + John Gray, Xilinx Corp. (UK) + Reiner Hartenstein, Univ. Kaiserslautern (D) + John McHenry, National Security Agency (USA) + Toshiaki Miyazaki, NTT Laboratories (JP) + Brent Nelson, Brigham Young Univ. (USA) + Viktor Prasanna, Univ. of Southern California (USA) + Hartmut Schmeck, Univ. Karlsruhe (D) + Herman Schmitt, Carnegie Mellon Univ. (USA) + Michal Servit, Techn. Univ. Prague (CR) + Takayuki Yanagawa, NEC, Tokyo (JP) + Hiroto Yasuura, Kyushu University (JP) Submitting Papers All papers will be reviewed. Electronic submissions (in postscript format) are encouraged and should be sent to: hartenst@rhrk.uni-kl.de and abakus@informatik.uni-kl.de (please, use both, simultaneously). Please make sure that your submission is viewable with ghostscript and printable on European A4 size paper. The workshop proceedings will be published by a professional publisher, taking care of ISBN number and Library of Congress catalog number. Important Dates: Manuscripts due November 15, 1997. Notification of review decisions December 19, 1997. Final version due January 23, 1998. For Further Information, please contact any of the workshop co-chairs: Peter M. Athanas Virginia Polytechnic Institute and State University The Bradley Dept. of Electr. and Comp. Eng. Blacksburg, VA 24061-0111 E-mail: athanas@vt.edu Reiner W. Hartenstein Universitaet Kaiserslautern (Germany) E-mail: hartenst@rhrk.uni-kl.de and abakus@informatik.uni-kl.de (please, use both, simultaneously), FAX: +49 631 205 2640 and +49 7251 14823 (please, use both, simultaneously) From codesign-request@ifi.unizh.ch Wed Sep 17 09:17:12 1997 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <09659-0@josef.ifi.unizh.ch>; Wed, 17 Sep 1997 09:10:50 +0200 Return-Path: X-Received: from pol88b.polito.it by josef.ifi.unizh.ch with SMTP (PP) id <00505-0@josef.ifi.unizh.ch>; Tue, 16 Sep 1997 22:20:03 +0200 X-Received: from chiusella.polito.it.polito.it (chiusella.polito.it) by polito.it (PMDF V4.2-15 #3020) id <01INQ15AWGLCHST10H@polito.it>; Tue, 16 Sep 1997 20:07:41 GMT+1 X-Received: by chiusella.polito.it.polito.it (4.1/SMI-4.1) id AA00211; Tue, 16 Sep 97 20:09:19 +0200 Date: Tue, 16 Sep 1997 20:09:19 +0200 From: tttc@chiusella.polito.it (Paolo Prinetto) Subject: IEEE TTTC - 16TH IEEE VLSI TEST SYMPOSIUM : Call for papers To: pilz@ifi.unizh.ch Message-id: <9709161809.AA00211@chiusella.polito.it.polito.it> X-Envelope-to: pilz@ifi.unizh.ch Content-transfer-encoding: 7BIT Apparently-To: PILZ Markus ReSent-Date: Wed, 17 Sep 1997 09:04:49 +0200 (MET DST) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Message-ID: Status: RO X-Status: %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % IEEE Computer Society % Test Technology Technical Committee % % % .... FOR YOUR INFORMATION.... % % A free service of the Technical Meeting Group % % % This message contains public information, only, and % the receiver is allowed, and invited, to copy it and % distribute it further. % % % For more information contact % or visit http://www.computer.org/tab/tttc/ % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% Dear Colleague, Enclosed please find the Call-for-Papers for the 1998 IEEE VLSI Test Symposium. We invite you to contribute to the Symposium's Technical Program. Kindly forward this announcement to your interested colleagues and prospective contributors. Please note that the deadline for submission of paper and panel proposals this year is October 10, 1997, which is significantly earlier than last year. Kindly mark your calendars and plan accordingly. We look forward to your submissions and continued participation in the IEEE VLSI Test Symposium. Sincerely, VTS 1998 Steering Committee ========================================================================= CALL FOR PAPERS 16TH IEEE VLSI TEST SYMPOSIUM Hyatt Regency Monterey, Monterey, California April 26 - April 30, 1998 WWW site: http://www.computer.org/tab/tttc/meetings/vts/home.html IEEE VLSI Test Symposium explores emerging trends and novel concepts in testing of circuits and systems. The major topics include, but are not limited to, the following: . Analog and RF Testing . IDDQ Testing . Automatic Test Generation . Mixed Signal Test . Built-In Self-Test (BIST) . Multi-Chip Module Test . Delay Testing . On-Line Testing . Design for Testability . Quality and Reliability . Design Verification/Validation . Self-Checking Circuits . Diagnosis and Debugging . Synthesis for Testability . Embedded Core Testing . System Test . Fault Modeling & Simulation . System-on-Chip Test . Fault Tolerant Architectures . Thermal Testing The Program Committee invites authors to submit original, unpublished paper proposals (full papers or extended summaries) and panel proposals. Clearly describe the nature of the work, explain its significance, highlight novel features, and describe its current status. On the title page, please include: name, affiliation, mailing address, phone number, fax number, and E-mail address of all authors, an abstract of 50 words, and suggested topics. Identify a contact author. To submit a paper, please do the following: 1. Complete an Electronic Paper Submission Form to obtain a registration number for your paper. Include the registration number with your submission. 2. Including the registration number, please submit in ONE of the following two formats only (No FAX submissions please): * 12 copies of hard-copy submissions by postal mail to the Program Chair; * PostScript or PDF submission via ftp using WWW at http://www.computer.org/tab/tttc/meetings/vts/home.html Submissions are due no later than October 10, 1997. For general information, contact: Submit paper proposals to: Rob Roy, General Chair Michael Nicolaidis, Program Chair Intel Corp., MS: JFT-102 TIMA 5300 Elam Young Pkwy 46 Avenue Felix VIALLET Hillsboro OR 97124-6497 38031 Grenoble Cedex, FRANCE T: 503-264-3738, F: 503-264-9359 T: +33-476-57-4619, F: +33-476-47-3814 E: robroy@ichips.intel.com E: vts98@imag.fr Authors will be notified of the disposition of their papers by December 26, 1997. The submission of a proposal will be considered evidence that upon acceptance the author(s) will present the paper at the symposium and will submit a final paper for inclusion in the proceedings no later than February 6, 1998. VTS'98 will present a Best Paper Award and a Best Panel Award, based on the evaluations of reviewers, attendees, and an invited panel of judges. Also, a selected set of papers from VTS'98 will appear in a Special Issue of JETTA. VLSI Test Symposium is sponsored by the IEEE Computer Society Test Technology Technical Committee and the IEEE Philadelphia Section. ********************************************************************** GENERAL CHAIR R. Roy - Intel PROGRAM CHAIR M. Nicolaidis - TIMA PAST CHAIR Y. Zorian - LogicVision VICE GENERAL CHAIRS W. Debany - Air Force Res. Lab A. Singh - Auburn U VICE PROGRAM CHAIRS S. Chakravarty - SUNY A. Ivanov - U of Brit. Columbia PANELS H-J. Wunderlich - U of Stuttgart PUBLICITY B. Kaminska - OPMAXX PUBLICATIONS S. Dey - NEC USA TUTORIALS J. Figueras - U Poli Catalunya AUDIO-VISUAL J. Monzel - IBM FINANCE F. J. Ferguson - UC Santa Cruz LOCAL ARRANGEMENTS S. Radcliffe - NEW Beginnings PROGRAM COMMITTEE : M. Abadir - Motorola J.A. Abraham - U of Texas M. Abramovici - Lucent Bell Labs S. Adham - Nortel V.D. Agrawal - Lucent Bell Labs B. Becker - U of Freiburg S. Blanton - Carnegie-Mellon U M. Breuer - U of Southern Cal. G. Carlsson - Ericsson A. Chatterjee - Georgia Tech. K.T. Cheng - UC Santa Barbara B. Courtois - TIMA M. d'Abreu - Level One Comm. W.K. Fuchs - Purdue U H. Fujiwara - NAIST M. Goessel - U of Potsdam J.P. Hayes - U of Michigan N. Jha - Princeton U K. Kinoshita - Osaka U A. Kuchukian - Armenian NAS C. Landrault - U Montpellier II A. Majumdar - Viewlogic W. Maly - Carnegie-Mellon U P. Maxwell - Hewlett Packard E.J. McCluskey - Stanford U B. Nadeau-Dostie - LogicVision A. Orailoglu - UC San Diego P. Pal Chaudhuri - Intel A. Paschalis - NCSR Demokritos J.H. Patel - U of Illinois I. Pomeranz - U of Iowa T. Powell - Texas Instruments D. Pradhan - Texas A&M U P. Prinetto - Poli di Torino A. Raghunathan - NEC USA J. Rajski - Mentor Graphics E. Rudnick - U of Illinois R. Segers - Philips E. Sogomonyan - Russian NAS S. Sunter - LogicVision M. Soma - U of Washington S. Tragoudas - Southern Illinois U A.J. van de Goor - Delft U T.W. Williams - IBM ADVISORY BOARD: D. Graham - inTest N. Kornfield - Widener U M. Modi - Naval Air War. Cnt W. Radcliffe - IBM P. Varma - Duet Technologies Y. Zorian - LogicVision IEEE VLSI Test Symposium P. O. Box 629 Hollidaysburg, PA 16648, USA Tel: +1 814 941-4669 Fax: +1 814 941-4668 Email: EdDor@aol.com From codesign-request@ifi.unizh.ch Sun Sep 21 10:39:14 1997 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch with SMTP (PP) id <12810-0@josef.ifi.unizh.ch>; Sun, 21 Sep 1997 10:39:06 +0200 Return-Path: X-Received: from slip129-37-118-202.nc.us.ibm.net by josef.ifi.unizh.ch with SMTP (PP) id <09995-0@josef.ifi.unizh.ch>; Sun, 21 Sep 1997 01:14:31 +0200 X-Received: from tclin (tclin@localhost [127.0.0.1]) by tclin.async.vt.edu (8.6.12/8.6.9) with SMTP id TAA00338; Sat, 20 Sep 1997 19:17:42 -0400 Sender: tclin@tclin.async.vt.edu Message-ID: <34245994.E414BB0@ibm.net> Date: Sat, 20 Sep 1997 19:17:40 -0400 From: Ta-Cheng Lin Organization: IBM microelectronics X-Mailer: Mozilla 2.01 (X11; I; Linux 1.2.12 i586) MIME-Version: 1.0 To: codesign@ifi.unizh.ch CC: isss-people@ics.uci.edu, codesign@vhdl.org Subject: ISSS proceedings Content-Type: text/plain; charset=big5 Content-Transfer-Encoding: 7bit ReSent-Date: Sun, 21 Sep 1997 10:33:01 +0200 (MET DST) ReSent-From: Markus Pilz ReSent-To: codesign@ifi.unizh.ch ReSent-Message-ID: Status: RO X-Status: Hello All: I would like to compile some papers that are published in International symposium of system snynthesis. ACM only have '95(8th) for sale. Where can I get the otheres? The years I am interested in are 95, 96, and 97. Thanks TC Lin From codesign-request@ifi.unizh.ch Thu Oct 30 10:24:00 1997 Return-Path: Received: from imag.imag.fr by josef.ifi.unizh.ch with SMTP (PP) id <01358-0@josef.ifi.unizh.ch>; Thu, 30 Oct 1997 10:23:45 +0100 Received: from verdon.imag.fr (verdon.imag.fr [147.171.129.20]) by imag.imag.fr (8.8.5/8.8.5) with ESMTP id KAA10783; Thu, 30 Oct 1997 10:23:39 +0100 (MET) Received: (from jerraya@localhost) by verdon.imag.fr (8.6.11/8.6.9) id KAA10447; Thu, 30 Oct 1997 10:23:49 +0100 Date: Thu, 30 Oct 1997 10:23:49 +0100 From: Ahmed Amine Jerraya Message-Id: <199710300923.KAA10447@verdon.imag.fr> X-Mailer: Mail User's Shell (7.2.5 10/14/92) To: isss-people@ics.UCI.EDU, codesign@ifi.unizh.ch Subject: Codes/CASHE '98: Call for Papers Status: RO X-Status: CALL FOR PARTICIPATION 6th International Workshop on Hardware/Software Co-Design Codes/CASHE '98 Seattle, Washington - 15-18 March 1998 Sponsored by (pending) : IEEE Computer Society, IEEE CAS, IFIP 10.5, ACM/SIGDA, ACM/SIGSOFT. Electronic Submission by: 07 December 1997 Notyfication by : 20 January 1998 The Codes/CASHE (Computer Aided Software/Hardware Engineering) workshop is the major international forum for the presentation and exchange of ideas in this field. It covers all aspects of the specification, design, construction, and verification of embedded systems that include functionality mapped to both hardware and software components. Presentations and discussions address theoretical aspects, design methods, tools, and case studies. The meeting is structured so as to promote active discussion between all participants in an informal setting. This is accomplished via short oral presentations of accepted papers combined with poster sessions to provide the opportunity to investigate and discuss the ideas in depth. Group discussions will be selected based on submitted proposals and/or based on the interests of the participants. In order to focus on new research directions and on-going research, submissions to the workshop are due only three (3) months before the meeting and should be sent electronically according to the directions on the reverse side of this call. Submissions for the combined oral presentation and poster should be no longer than 5 pages. These same materials will be provided to the participants in the form of a proceedings (there will not be time to ask authors to submit a revised copy). In addition, submitters may also provide a URL for additional information related to their work or project residing on their web sites. The web site for the meeting will include the URLs provided by all accepted presentations in the final program. Publication of presentations in the proceedings is voluntary. The authors of accepted papers will be asked to submit slides two weeks before the workshop, so that they can be made available to the attendees. Proposals for group discussions are also highly welcome and should take the form of no more than 2 pages highlighting the problem to be addressed in the discussion, the motivation for the topic with suggestions for problems or issues to be addressed, and a potential discussion moderator or panel. To allow preparation for group discussions, the accepted discussion proposals will be made available to attendees via the workshop web sites in conjuction with the final program. Areas of interest include, but are not limited to: 1. Computer-aided techniques for HW/SW co-design Specification languages and modeling techniques, design representations, simulation and validation, formal verification, emulation and physical prototyping, synthesis approaches, system-level design. 2. Target architectures Distributed and multiprocessor architectures for embedded systems, HW/SW interfaces and communication methods, heterogeneous system design, flexible architectures, embedded system design, case studies. 3. Software for HW/SW co-design Software development environments, real-time operating systems, distributed systems, process scheduling and other concurrency management techniques, software synthesis approaches, portability of specifications, system integration, testbenches and testing, retargetable compilation. 4. System development process Concurrent engineering, design re-use, design space exploration, design process management, partitioning, estimation, device libraries, and component models. SUBMISSION PROCEDURE The submission procedure is to send an electronic mail message based on the following template: Subject: CODES98 submission Submission-type: {paper or group-discussion} Related-URL: {a URL pointing to related work} Include-in-proceedings: {YES or NO} Number-of-pages: {total number of pages in the postscript file below} Keywords: {up to 3 key words or phrases describing the work} {uuencoded postscript file} to codes98@polv2k.polito.it by 7 December 1997. The receipt of the message will be immediately acknowledged electronically. Notification of acceptance will be sent to the same e-mail address from which the submission was sent by 20 January 1998. WORKSHOP INFORMATION Workshop web sites in North America and Europe are: http://www.cs.washington.edu/research/codes98/ http://polimage.polito.it/codes98/ Check the web sites regularly for workshop announcements and logistics information. For further information or clarifications send e-mail to: codes98@cs.washington.edu. General Chair Program Co-chairs Gaetano Borriello Ahmed Amine Jerraya Luciano Lavagno Dept. of Computer System Level Synthesis Group Dipartimento di Elettronica Science and Engineering University of Washington TIMA Laboratory Politecnico di Torino Box 352350 46 Avenue Felix Viallet Corso Duca degli Abruzzi 24 Seattle, WA 98195-2350 [USA] F-38031 Grenoble Cedex, FRANCE I-10129, Torino, ITALY Tel: +1 (206) 685-9432 Tel: +33 476 574 759 Tel: +39 11 564-4150 Fax: +1 (206) 543-2969 Fax: +33 476 473 814 Fax: +39 11 564-4099 Email:gaetano@cs.washington.edu Email:ahmed.jerraya@imag.fr Email:lavagno@polito.it Technical Program Committee Brian Bailey, Mentor Graphics, USA Jim Beck, Delco, USA Tarek Ben-Ismail, HP Labs, Bristol, UK Ivo Bolsens, IMEC, B Gaetano Borriello, Univ. of Washington, USA Joseph Buck, Synopsys, USA Raul Camposano, Synopsys, USA Carlos Delgado-Kloos, University of Madrid, E Giovanni De Micheli, Stanford University, USA Martyn Edwards, University of Manchester (UMIST), UK Rolf Ernst, University of Braunschweig, D Thomas Fuhrman, General Motors, USA Daniel Gajski, Univ. of Calif. at Irvine, USA Rajesh Gupta, Univ. of Calif. at Irvine, USA Ahmed Jerraya, TIMA Laboratory, Grenoble, F Timothy Kam, INTEL Oregon, USA Kurt Keutzer, Synopsys, USA Sanjaya Kumar, Honeywell, USA Philip Koopman, Carnegie-Mellon Univ., USA Luciano Lavagno, Politecnico di Torino, I Jan Madsen, Technical Univ. of Denmark, DK Franz Rammig, C-Lab, University of Paderborn, D Wolfgang Rosenstiel, Univ. of Tubingen, D James Rowson, Cadence, USA Alberto Sangiovanni-Vincentelli, Miguel Santana, SGS-Thompson, F UC Berkeley, USA Donatella Sciuto, Politecnico di Milano, I Don Thomas, Carnegie-Mellon University, USA Frank Vahid, Univ. of Calif. at Riverside, USA Kees Vissers, Philips, NL Wayne Wolf, Princeton University, USA Hiroto Yasuura, Kyushu University, Japan -- ------------------- PLEASE NOTE THE CHANGEs IN PHONE AND FAX NUMBERS ------ Ahmed Amine JERRAYA, Ph. D | Office: (+33) 476 574 759 ------ System-Level Synthesis Group | Home : (+33) 476 096 014 ------ TIMA/INPG 46 Ave Felix Viallet | Fax : (+33) 476 473 814 ------ F-38031 Grenoble Cedex FRANCE | E_mail: ahmed.jerraya@imag.fr From codesign-request@ifi.unizh.ch Mon Nov 3 20:10:49 1997 Return-Path: Received: from chronos.synopsys.com by josef.ifi.unizh.ch with SMTP (PP) id <23008-0@josef.ifi.unizh.ch>; Mon, 3 Nov 1997 20:09:36 +0100 Received: from atropos.synopsys.com by chronos.synopsys.com with SMTP id AA22326 (5.65c/IDA-1.4.4 for ); Mon, 3 Nov 1997 11:09:59 -0800 Received: from kunkel-lap (dhcp-146-225-33-191.synopsys.com [146.225.33.191]) by atropos.synopsys.com (8.6.9/8.6.9) with SMTP id LAA00294; Mon, 3 Nov 1997 11:10:00 -0800 Message-Id: <345E2162.37A2@synopsys.com> Date: Mon, 03 Nov 1997 11:09:22 -0800 From: Joachim Kunkel Reply-To: kunkel@synopsys.com Organization: Synopsys, Inc. X-Mailer: Mozilla 3.0 (WinNT; I) Mime-Version: 1.0 To: vsidwgsld@vsi.org, ic-sld@si2.org, codesign@ifi.unizh.ch Subject: CALL FOR PAPERS - Design Automation for Embedded Systems Content-Type: multipart/mixed; boundary="------------73CE6238393" X-Keywords: X-UID: 20 Status: RO X-Status: This is a multi-part message in MIME format. --------------73CE6238393 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Please feel free to forward this call for papers to interested colleagues. Joachim Kunkel --------------------------------------------------------------------------- > > CALL FOR PAPERS > > Kluwer Academic Publishing > > Design Automation for Embedded Systems > > Special Issue > > SYSTEM LEVEL DESIGN TOOLS IN INDUSTRY > > Guest Editor: Joachim Kunkel > > System Level Design Tools have increasingly become an integral part of > System to Silicon design flows. This is particularly true in the area > of complex digital signal processing and reactive systems. > > The focus of this special issue will be on the role of System Level > Design Tools in established industrial design flows, as oposed to > presenting newest break throughs in the area of System Level Design > Tools. Each contribution will present a real design case, the design > methodology followed and its associated tool flow. The benefits from > using System Level Design Tools will be discussed and an outlook on > what is seen as the next major step in the industrial adoption of > System Level Design Tools will be given. > > Although familiarity of the readers of this special issue with System > Level Design Tools can not be assumed, contributions should not > emphasise tool features and their underlying technology, but the > design activity itself and how it is supported by these class of > tools. > > ---------------------------------------------------------------------- > > Submit papers to Publication schedule > > Joachim Kunkel Final submission date December 31, 1997 > Synopsys, Inc. Provisional acceptance March 31, 1998 > 700 East Middlefield Rd. Delivery of final paper April 30, 1998 > Mountain View, CA 94043 Publication 2nd half 1998 > USA > > phone : +1 (650) 694 1844 > e-mail: kunkel@synopsys.com > > ---------------------------------------------------------------------- > > Check out http://www.wkap.nl/kaphtml.htm/IFAHOME for information for > authors. --------------73CE6238393 Content-Type: text/html; charset=us-ascii; name="CallforPapers.html" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="CallforPapers.html" Content-Base: "file:///C|/WINNT/Profiles/kunkel/Deskt op/CallforPapers.html" CALL FOR PAPERS - Design Automation for Embedded Systems

CALL FOR PAPERS

Kluwer Academic Publishing

Design Automation for Embedded Systems

Special Issue

SYSTEM LEVEL DESIGN TOOLS IN INDUSTRY

Guest Editor: Joachim Kunkel

System Level Design Tools have increasingly become an integral part of System to Silicon design flows. This is particularly true in the area of complex digital signal processing and reactive systems.

The focus of this special issue will be on the role of System Level Design Tools in established industrial design flows, as oposed to presenting newest break throughs in the area of System Level Design Tools. Each contribution will present a real design case, the design methodology followed and its associated tool flow. The benefits from using System Level Design Tools will be discussed and an outlook on what is seen as the next major step in the industrial adoption of System Level Design Tools will be given.

Although familiarity of the readers of this special issue with System Level Design Tools can not be assumed, contributions should not emphasise tool features and their underlying technology, but the design activity itself and how it is supported by these class of tools.



Submit papers to Publication schedule
Joachim Kunkel
Synopsys, Inc.
700 East Middlefield Road
Mountain View, CA 94043-4033
USA

phone : +1 (650) 694 1844
e-mail: kunkel@synopsys.com 		Final submission date
Provisional acceptance
Delivery of final paper
Publication


 December 31st, 1997
March 31st, 1998
April 30th, 1998
2nd half 1998


Check out http://www.wkap.nl/kaphtml.htm/IFAHOME for information for authors. --------------73CE6238393-- From codesign-request@ifi.unizh.ch Wed Nov 19 11:55:29 1997 Return-Path: Received: from ercc.snu.ac.kr by josef.ifi.unizh.ch with SMTP (PP) id <28196-0@josef.ifi.unizh.ch>; Wed, 19 Nov 1997 11:54:46 +0100 Received: from poppy.snu.ac.kr.snu.ac.kr by ercc (SMI-8.6/SMI-SVR4) id TAA15687; Wed, 19 Nov 1997 19:52:12 +0900 Received: from ercc.snu.ac.kr (enya) by poppy.snu.ac.kr.snu.ac.kr (4.1/SMI-4.1) id AA23147; Wed, 19 Nov 97 19:55:00 KST Message-Id: <3472C565.2B6E45DA@poppy.snu.ac.kr> Date: Wed, 19 Nov 1997 19:54:29 +0900 From: Jinhwan Jeon X-Mailer: Mozilla 4.0 [en] (Win95; I) Mime-Version: 1.0 To: codesign@ifi.unizh.ch Subject: APCHDL'98 Call for papers X-Priority: 3 (Normal) Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Status: RO X-Status: >> The Fifth Asia Pacific Conference on Hardware Description Languages << Seoul, Korea July 8 - 10, 1998 APCHDL'98 ------------------------------------------------------------------------ **** CALL For PAPERS **** * General Information The Asia Pacific Conference on Hardware Description Languages (APCHDL) provides a forum for the presentation of advances in hardware description languages and the related areas. Following the previous conferences in this series held in Australia, Japan, India, and Taiwan, respectively, the fifth conference will be held in Seoul, Korea, July 8-10, 1998. * Topics Prospective authors are invited to submit extended abstracts presenting original work on the topics including, but not limited to, the following: 1. Hardware Description Languages 2. System Specification and Modeling 3. Simulation/Verification 4. Hardware-Software Codesign 5. High-Level Synthesis 6. Logic Synthesis 7. Analog and Mixed Signal Design 8. Testing and DFT * Submission Information Submissions should include a cover sheet containing paper title, paper category (pick numbers from the above list or describe), authors' names and affiliations , contact author's postal address, phone and FAX numbers, and E-mail address. Please submit 4 copies of 2000 word extended abstract or a Postscript version via E-mail. Once accepted, authors will be asked to prepare a four-to-six page camera-ready paper for the conference proceedings. Submissions should be sent to: APCHDL98 Technical Program Co-Chairs c/o School of Electrical Engineering Seoul National University Shinlim-dong, Kwanak-gu, Seoul 151-742, Korea Tel: +82-2-880-6768, Fax: +82-2-882-4656 E-mail: apchdl98@poppy.snu.ac.kr * Authors' Schedule Deadline for submission of extended abstracts February 16, 1998 Notification of acceptance May 1, 1998 Deadline for submission of camera-ready papers June 15, 1998 ------------------------------------------------------------------------ *** Organizing Committee *** * General Chair Younggap You Chungbuk National University ygyou@cbucc.chungbuk.ac.kr * Technical Program Co-Chair Sun Young Hwang Sogang University hwang@ccs.sogang.ac.kr * Technical Program Co-Chair Kiyoung Choi Seoul National University kchoi@azalea.snu.ac.kr * Finance Chair Myung Hoon Sunwoo Ajou University sunwoo@madang.ajou.ac.kr * Local Arrangement Chair Soonhoi Ha Seoul National University sha@iris.snu.ac.kr * Publications Chair Sang-Chul Kim Hankuk University of Foreign Studies kimsa@maincc.hufs.ac.kr * Publicity Chair Seung-Ho Hwang Korea Advanced Institute of Science and Technology shwang@ee.kaist.ac.kr * Tutorial Chair Hyunchul Shin HanYang University shin@hyunp2.hanyang.ac.kr * Steering Committee Chair Young Uk Yu Seodu Logic, Inc. yuyu@seodu.co.kr * For Up-To-Date Information : http://poppy.snu.ac.kr/apchdl98 ------------------------------------------------------------------------ *** Program Committee *** Dominique Borrione - IMAG/ARTEMIS Raul Camposano - Synopsys Joong Hwee Cho - Inchon U Yunmo Chung - Kyunghee U Luc Claesen - IMEC Bernard Courtois - TIMA Lab Nikil Dutt - UC Irvine Rolf Ernst - TU Braunschweig Winfried Hahn - U Passau Graham Hellestrand - UNSW Ahmed Hemani - KTH Ahmed Jerraya - TIMA/INPG Jing-Yang Jou - Chiao Tung U Hilary Kahn - U Manchester Bill Lin - UCSD Youn-Long Lin - Tsing Hua U Yusuke Matsunaga - Fujitsu Jean Mermet - UJF Takashi Nanya - TIT Sri Parameswaran - U Queensland Inhag Park - ETRI Chong Suck Rim - Sogang U Gabriele Saucier - INPG Masatoshi Sekine - Toshiba Sunil Sherlekar - Silicon Automation Sys. Alec Stanculescu - Fintronic Eugenio Villar - U Cantabria Flavio Wagner - UFRGS Chung-Hao Wu - Tsing Hua U Hiroto Yasuura - Kyushu U ------------------------------------------------------------------------ Sponsored by IFIP WG 10.5 (pending) and Co-Sponsored by IEEE Korea Council From codesign-request@ifi.unizh.ch Wed Nov 26 06:14:20 1997 Return-Path: Received: from ercc.snu.ac.kr by josef.ifi.unizh.ch with SMTP (PP) id <22571-0@josef.ifi.unizh.ch>; Wed, 26 Nov 1997 06:14:04 +0100 Received: from poppy.snu.ac.kr.snu.ac.kr by ercc (SMI-8.6/SMI-SVR4) id OAA04091; Wed, 26 Nov 1997 14:11:33 +0900 Received: by poppy.snu.ac.kr.snu.ac.kr (4.1/SMI-4.1) id AA16410; Wed, 26 Nov 97 14:14:27 KST From: jeonjinh@poppy.snu.ac.kr (JinHwan Jeon) Message-Id: <9711260514.AA16410@poppy.snu.ac.kr.snu.ac.kr> Subject: APCHDL'98 Call for Papers To: codesign@ifi.unizh.ch (codesign mailing list) Date: Wed, 26 Nov 1997 14:14:26 +0900 (KST) X-Mailer: ELM [version 2.4 PL21-h3] Content-Type: text Status: RO X-Status: >> The Fifth Asia Pacific Conference on Hardware Description Languages << Seoul, Korea July 8 - 10, 1998 APCHDL'98 ------------------------------------------------------------------------ **** CALL For PAPERS **** * General Information The Asia Pacific Conference on Hardware Description Languages (APCHDL) provides a forum for the presentation of advances in hardware description languages and the related areas. Following the previous conferences in this series held in Australia, Japan, India, and Taiwan, respectively, the fifth conference will be held in Seoul, Korea, July 8-10, 1998. * Topics Prospective authors are invited to submit extended abstracts presenting original work on the topics including, but not limited to, the following: 1. Hardware Description Languages 2. System Specification and Modeling 3. Simulation/Verification 4. Hardware-Software Codesign 5. High-Level Synthesis 6. Logic Synthesis 7. Analog and Mixed Signal Design 8. Testing and DFT * Submission Information Submissions should include a cover sheet containing paper title, paper category (pick numbers from the above list or describe), authors' names and affiliations , contact author's postal address, phone and FAX numbers, and E-mail address. Please submit 4 copies of 2000 word extended abstract or a Postscript version via E-mail. Once accepted, authors will be asked to prepare a four-to-six page camera-ready paper for the conference proceedings. Submissions should be sent to: APCHDL98 Technical Program Co-Chairs c/o School of Electrical Engineering Seoul National University Shinlim-dong, Kwanak-gu, Seoul 151-742, Korea Tel: +82-2-880-6768, Fax: +82-2-882-4656 E-mail: apchdl98@poppy.snu.ac.kr * Authors' Schedule Deadline for submission of extended abstracts February 16, 1998 Notification of acceptance May 1, 1998 Deadline for submission of camera-ready papers June 15, 1998 ------------------------------------------------------------------------ *** Organizing Committee *** * General Chair Younggap You Chungbuk National University ygyou@cbucc.chungbuk.ac.kr * Technical Program Co-Chair Sun Young Hwang Sogang University hwang@ccs.sogang.ac.kr * Technical Program Co-Chair Kiyoung Choi Seoul National University kchoi@azalea.snu.ac.kr * Finance Chair Myung Hoon Sunwoo Ajou University sunwoo@madang.ajou.ac.kr * Local Arrangement Chair Soonhoi Ha Seoul National University sha@iris.snu.ac.kr * Publications Chair Sang-Chul Kim Hankuk University of Foreign Studies kimsa@maincc.hufs.ac.kr * Publicity Chair Seung-Ho Hwang Korea Advanced Institute of Science and Technology shwang@ee.kaist.ac.kr * Tutorial Chair Hyunchul Shin HanYang University shin@hyunp2.hanyang.ac.kr * Steering Committee Chair Young Uk Yu Seodu Logic, Inc. yuyu@seodu.co.kr * For Up-To-Date Information : http://poppy.snu.ac.kr/apchdl98 ------------------------------------------------------------------------ *** Program Committee *** Dominique Borrione - TIMA/UJF Raul Camposano - Synopsys Joong Hwee Cho - Inchon U Yunmo Chung - Kyunghee U Luc Claesen - IMEC Bernard Courtois - TIMA Lab Nikil Dutt - UC Irvine Rolf Ernst - TU Braunschweig Winfried Hahn - U Passau Graham Hellestrand - UNSW Ahmed Hemani - KTH Ahmed Jerraya - TIMA/INPG Jing-Yang Jou - Chiao Tung U Hilary Kahn - U Manchester Bill Lin - UCSD Youn-Long Lin - Tsing Hua U Yusuke Matsunaga - Fujitsu Jean Mermet - UJF Takashi Nanya - TIT Sri Parameswaran - U Queensland Inhag Park - ETRI Chong Suck Rim - Sogang U Gabriele Saucier - INPG Masatoshi Sekine - Toshiba Sunil Sherlekar - Silicon Automation Sys. Alec Stanculescu - Fintronic Eugenio Villar - U Cantabria Flavio Wagner - UFRGS Chung-Hao Wu - Tsing Hua U Hiroto Yasuura - Kyushu U ------------------------------------------------------------------------ Sponsored by IFIP WG 10.5 (pending) and Co-Sponsored by IEEE Korea Council From codesign-request@ifi.unizh.ch Mon Dec 8 16:20:27 1997 Return-Path: Received: from news.uni-kl.de by josef.ifi.unizh.ch with SMTP (PP) id <26089-0@josef.ifi.unizh.ch>; Mon, 8 Dec 1997 16:20:18 +0100 Received: from uklirb.informatik.uni-kl.de by news.uni-kl.de id ak18687; 8 Dec 97 16:19 MET Received: from irz1.informatik.uni-kl.de by uklirb.informatik.uni-kl.de id aa03640; 8 Dec 97 16:18 MET Received: by irz1.informatik.uni-kl.de (SMI-8.6/SMI-SVR4) id QAA28576; Mon, 8 Dec 1997 16:18:00 +0100 From: AG Hartenstein-UNI KL-FRG Message-Id: <199712081518.QAA28576@irz1.informatik.uni-kl.de> Subject: FPL-98: Call for Papers To: codesign@ifi.unizh.ch Date: Mon, 8 Dec 1997 16:17:59 +0100 (MET) X-Mailer: ELM [version 2.4 PL24] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Status: RO X-Status: ******************************************************************************* * We apologize, if you receive this message more than once. * This message contains public information, and the receiver is allowed and * invited to copy it and distribute it further. * For more information about the contents of this message, contact: * abakus@informatik.uni-kl.de ******************************************************************************* _|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_| _| _| _| _| _| _|_|_|_| _|_|_|_| _| _| _|_|_|_| _|_|_|_| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _|_|_| _|_|_|_| _| _|_|_|_| _|_|_|_| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _|_|_|_| _|_|_|_| _|_|_|_| _| _| _| _| _| _|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_| F P L '98 E I G H T H I N T E R N A T I O N A L W O R K S H O P on FIELD PROGRAMMABLE LOGIC AND APPLICATIONS _|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_| _| _| _| August 31 - September 2, 1998 (Monday - Wednesday) _| _| _| _| Tallinn Technical University , Estonia _| _| _| _| http://www.ttu.ee/fpl98 _| _| _| _|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_| C A L L F O R P A P E R S _|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_| _| _| _| Paper Deadline March 7, 1998 _| _| _| _|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_| AIM: FROM TINKERTOY TO PARALLEL COMPUTING PARADIGM The methodology of reconfigurable circuits and systems is evolving from tinkertoy approach to an: Innovative Parallel Computing Paradigm which combines computing in time with computing in space. The aim of this workshop is to bring together workers from throughout the world for a wide ranging discussion of all forms of field programmable logic, particularly field programmable gate arrays and complex programmable logic devices, and their applications. It is intended to discuss the increasing range of device types, industrial applications, advanced design tool development, research applications, novel system architectures and educational experiences. The workshop will include regular presentations, posters and discussion sessions, and it is expected that most of the delegates will wish to make some contribution to one or more of these. The workshop is the eighth in a series of workshops which were held in Oxford (1991, 1993 and 1995), Vienna (1992), Prague (1994), Darmstadt (1996) and London (1997). CALL FOR CONTRIBUTIONS Contributions are invited for regular presentation, poster and discussion sessions. Prospective authors are invited to submit an abstract of at least 500 words or a full paper of about 10 pages by 7 March 1998 to the Program Chairman. Please send also your full correspondence address, including e-mail, and fax, and a list of (at most) 5 one-line statements that best encapsulate the essence of your proposed contribution. Submissions by e-mail to: abakus@informatik.uni-kl.de in postscript format (ghostscript-compatible) are highly encouraged. Notification of acceptance will be posted by 15 May 1998 and final papers must be received by 15 June 1998 to guarantee distribution at the workshop. The workshop proceedings will be published by Springer. For the publication of accepted papers, an electronic as well as a camera-ready version of the paper and the registration of at least one author will be required. Potential exhibitors and tutorial presenters are also invited to contact the Program Chairman. The official conference language as well as the language of submissions and accepted papers will be English. SCOPE Workshop topics include, but are not restricted to: - Novel device, machine and system architectures - New software and hardware development tools - Run-time reconfigurable and partially reconfigurable designs - High-level design and compilation research - Industrial applications and experiences - Trade-offs between devices, architectures and technologies - Benchmarking and profiling - Applications from a wide variety of areas - Reconfigurable custom computing machines - Hardware/Software Co-Design using field programmable devices - Evolvable and adaptable systems - ASIC emulators, hardware modellers and compiled accelerators - Fault modelling, testability methods and reliability issues - Educational experiences and opportunities - Reconfigurable accelerators and their applications - Speed-up effects - survey and analysis - Testing of reconfigurable circuits GENERAL CHAIRMAN Prof. Andres Keevallik Tallinn Technical University Raja 15 Tallinn EE-0026 Estonia Phone: +372-6104440 Fax: +372-6202246 email: akeev@cc.ttu.ee http://www.ttu.ee/fpl98 PROGRAM CHAIRMAN Prof. Reiner W. Hartenstein University of Kaiserslautern P. O. Box 3049 D-67653 Kaiserslautern Germany Phone: +49 631 205-2606 Fax: +49 631 205-2640 email: hartenst@rhrk.uni-kl.de http://xputers.informatik.uni-kl.de/FPL/index_fpl.html PROGRAM COMMITTEE Doug Amos, Altera, UK Peter Athanas, Virginia Tech, USA Samary Baranov, Ben Gurion U. Negev,Israel Stephen Brown, U. of Toronto, CA Klaus Buchenrieder, Siemens AG, FRG Steven Casselman, VCC, USA Bernard Courtois, INPG, Grenoble, France Carl Ebeling, U. of Washington, USA Norbert Fristacky, Slovak Technical U., SK Manfred Glesner, TH Darmstadt, FRG John Gray, Xilinx, UK Herbert Gruenbacher, Vienna U., Austria Reiner Hartenstein, U. of Kaiserslautern, FRG Brad Hutchings, Brigham Young U., UAS Udo Kebschull, U. of Tuebingen, FRG Andres Keevallik, Tallinn Technical U., Estonia Wayne Luk, Imperial College, UK Patrick Lysaght, U. of Strathclyde, Scotland Toshiaki Miyazaki, NTT Laboratories, Japan Will Moore, Oxford U., UK Wolfgang Nebel, U. of Oldenburg, FRG Paolo Prinetto, Politecnico di Torino, Italy Jonathan Rose, U. of Toronto, Canada Zoran Salcic, U. of Auckland, New Zealand Michal Servit, Czech T. U., Czech Republic Marc Shand, Digital Systems Research Center, USA Steve Trimberger, Xilinx, USA LOCAL DETAILS The workshop will be held from 1st to 3rd September, 1998 at the National Library of Estonia near the center of Tallinn, the capital of the Republic of Estonia. Tallinn lies in the Northern Europe, in the northeast of the Baltic sea region. The good geographical location of Tallinn has favored its becoming an important harbor and a center of industry and trade. The workshop is organized by Tallinn Technical University which is situated about 5 km from the center of city. FURTHER INFORMATION AND REGISTRATION All the latest information about FPL'98 as well as registration info can be accessed via a WWW-page. The URL for this document is: http://www.ttu.ee/fpl98 From codesign-request@ifi.unizh.ch Wed Dec 17 07:54:24 1997 Return-Path: Received: from 140.114.87.70 by josef.ifi.unizh.ch with SMTP (PP) id <07026-0@josef.ifi.unizh.ch>; Wed, 17 Dec 1997 07:53:53 +0100 Received: (from isss98@localhost) by cs.nthu.edu.tw (thcs.2/cs20) id OAA25475 for codesign@ifi.unizh.ch; Wed, 17 Dec 1997 14:49:30 +0800 (CST) From: isss98 Message-Id: <199712170649.OAA25475@cs.nthu.edu.tw> Subject: ISSS98 Call for Papers To: codesign@ifi.unizh.ch Date: Wed, 17 Dec 1997 14:49:30 +0800 (CST) X-Mailer: ELM [version 2.4ME+ PL34C (25)] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Status: RO X-Status: I apologize if you receive multiple copies of this message or if you don't want to be in the mailing list. If you don't want to be in the mailing list, please send a mail to isss98@cs.nthu.edu.tw. Thanks. ****************************************************************************** ISSS'98 1ST CALL FOR PAPERS 11th INTERNATIONAL SYMPOSIUM ON SYSTEM SYNTHESIS Hsinchu, Taiwan, R.O.C., December 2-4, 1998 ****************************************************************************** ISSS'98 is the 11th in a very successful series of symposia oriented towards design automation professionals. At the symposium the latest results in emerging system design and synthesis technologies are presented. Original technical papers on, but not limited to, the following topics are invited: System-level synthesis: Partitioning, transformations, design reuse, quality measure, estimation, specification languages and models, intermediate forms, embedded processor synthesis. Hardware-software co-design: Hardware/software tradeoffs, interfaces and communications, co-simulation, co-emulation and co-synthesis, embedded system architectures, system exploration, system testbench development, design automation for rapid system prototyping. Programmable (multi-) processor-based design and synthesis: ASIPs, code generation, instruction-set specification, design and simulation, high-level code transformations. System design experience and methodologies: Application-specific parallel/distributed systems, industrial telecom, robotics, vision, video, audio and speech processing systems, formalized design methodology, process management. Embedded and real-time system software: Software development, constraint specification, process scheduling, real-time operating systems, distributed systems. High-level and architectural synthesis: Datapath, control, memory, and interface synthesis from behavioral specifications, clocking/timing optimization, physical design models for high-level tradeoffs, hardware accelerators/coprocessors. Synthesis for low power, testability and verifiability in the above areas. --------------------------------------------------------------------------- Submitted papers should be 6 pages or less in IEEE 2-column style (10pt), as close as possible to the final content. They should clearly specify contributions and results, and include a separate cover page with the following: paper title, complete name, address, telephone, fax, and email address of each author, identification of the corresponding author, and the category (numbered 1-7 above) most closely matching the paper's content. Papers exceeding the page limit will be returned to the authors. Submissions simultaneously sent to other forums will not be considered. The symposium proceedings will be published by the IEEE Computer Society Press. Everyone is strongly encouraged to submit the paper and cover page electronically as explained on our web page (http://www.cs.nthu.edu.tw/~isss98/ under the "Call for papers/submission instructions"). If you do not have access to a web browser you may also send the uuencoded gzipped (standard) Postscript paper and separate cover page (in ASCII format) to the email address ``isss98@cs.nthu.edu.tw''. If electronic submission is infeasible, 8 copies of the paper should be send along with the cover page to the Program Chair at the following address: Allen C.-H. Wu, ISSS'98 Computer Science Department Tsing Hua University Hsinchu, Taiwan 30043 Tel: 886-3-5715131 ext 3517 Fax: 886-3-5723694 Email: chunghaw@cs.nthu.edu.tw, isss98@cs.nthu.edu.tw =========================================================================== Author's schedule: Submission deadline: April 5, 1998 Notification of Acceptance: June 5, 1998 Camera-ready copies: July 5, 1998 ============================================================================ Steering Committee: General Chair: Francky Catthoor, IMEC Honorary Chair: C. L. Liu, Tsing Hua University Program Chair: Allen C.-H. Wu, Tsing Hua University Publications Chair: Liang-Gee Chen. Taiwan University Panels Chair: Nikil Dutt, University of California, Irvine Publicity Co-Chairs: Jyuo-Min Shyu, Industrial Technology Research Institute Ing-Jer Huang, Sun Yat-Sen University Finance Chair: Wen-Zen Shen, Chiao Tung University Local Arrangement Chair Steve Y.-L. Lin, Tsing Hua University Past Chair: Frank Vahid, University of California, Riverside ============================================================================ Technical program committee: Marleen Ade, K.U. Leuven Gaetano Borriello, Univ. Washington Raul Camposano, Synopsys Nikil Dutt, U.C. Irvine Rolf Ernst, Tech. Univ. Braunschweig Masahiro Fujita, Fujitsu Daniel Gajski, U.C. Irvine Cathy Gebotys, Univ. Waterloo Yu-Chin Hsu, Avant! Ahmed A. Jerraya, TIMA Kayhan Kucukcakar, Motorola Fadi Kurdahi, U.C. Irvine Steve Y.L. Lin, Tsing Hua Univ. Paul Lippens, Philips Jan Madsen, Tech. Univ. Denmark Lev Markov, Mentor Graphics Peter Marwedel, Univ. Dortmund Vijay Nagasamy, VSIS Inc. Yukihiro Nakamura, Kyoto Univ. Sanjiv Narayan, Ambit Design Systems Kevin O'brien, Leda B. Ramakrishna (Bob) Rau, HP Labs. Wolfgang Rosenstiel, Univ. Tubingen, FZI Edwin Sha, Univ. Notre Dame Leon Stok, IBM Donald Thomas, CMU Diederik Verkest, IMEC Kazutoshi Wakabayashi, NEC Robert Walker, Kent State Univ. Wayne Wolf, Princeton Hiroto Yasuura, Kyushu Univ. ****************************************************************************** Check the WWW at ``http://www.cs.nthu.edu.tw/~isss98/'' for the latest ISSS'98 related information. Sponsored by ACM SIGDA (Approval Pending), National Science Council of R.O.C. (Approval Pending), and Ministry of Education, R.O.C. (Approval Pending). ******************************************************************************