From codesign-request@ifi.unizh.ch Fri Jan 5 14:33:31 1996 Return-Path: Received: from netserv1.free.net by josef.ifi.unizh.ch with SMTP (PP) id <12116-0@josef.ifi.unizh.ch>; Fri, 5 Jan 1996 14:30:04 +0100 Received: from apmsun.mpei.ac.ru by netserv1.free.net (8.6.12/6) with SMTP id QAA18652 for ; Fri, 5 Jan 1996 16:27:44 +0300 Received: from srv-m.mpei.ac.ru by apmsun.mpei.ac.ru (5.0/SMI-SVR4) id AA05137; Fri, 5 Jan 1996 16:30:10 +0400 Received: by srv-m.mpei.ac.ru (5.x/SMI-SVR4) id AA03397; Fri, 5 Jan 1996 16:29:35 +0200 Message-Id: <9601051429.AA03397@srv-m.mpei.ac.ru> To: isss-request@ics.UCI.EDU, isss-people@ics.UCI.EDU, codesign@ifi.unizh.ch Subject: Email address update Date: Fri, 05 Jan 1996 From: Victor Toporkov Content-Type: text content-length: 188 Status: RO Dear Sirs, Please update my e-mail address to topvv@srv-m.mpei.ac.ru Thank you. Victor Toporkov ---------------------------------------------------------------------------- From codesign-request@ifi.unizh.ch Mon Jan 8 16:55:56 1996 Return-Path: Received: from peanuts.Informatik.Uni-Tuebingen.De by josef.ifi.unizh.ch with SMTP (PP) id <24208-0@josef.ifi.unizh.ch>; Mon, 8 Jan 1996 16:27:45 +0100 Received: from pigpen (pigpen [134.2.14.7]) by peanuts.Informatik.Uni-Tuebingen.De (8.6.12/8.6.12) with SMTP id QAA12659 for ; Mon, 8 Jan 1996 16:27:07 +0100 Message-Id: <199601081527.QAA12659@peanuts.Informatik.Uni-Tuebingen.De> X-Authentication-Warning: peanuts.informatik.uni-tuebingen.de: Host pigpen didn't use HELO protocol X-Mailer: exmh version 1.6.4 10/10/95 To: codesign@ifi.unizh.ch Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Date: Mon, 08 Jan 1996 16:27:06 +0100 From: Wolfgang Rosenstiel Status: RO ANNOUNCEMENT =================================================== Final Workshop of the Codesign Basic Research Action (COBRA) ESPRIT - Project April 29-30, 1996 Grassau, Germany =================================================== The workshop is supported by ESPRIT (8135, COBRA-Project) and organized in cooperation with IFIP WG 10.5 Special Interest Group SIG-CODES. This open workshop will present the results of the COBRA project and provide a basis for a technical discussion of new topics in hardware-software codesign. The goal for the ESPRIT-project COBRA was to develop models, design methods, and tools which allow designers to work, analyze, and experiment with high-level specifications of the design, with no commitment as to what should be realized as software (e.g. microprocessor code) and what should become hardware (e.g. ASIC, FPGA). The workshop itself will consist of mainly two parts. On the first day invited speakers from industry and academia will give an overview of the status and the needs in hardware-software codesign. The COBRA project members will give an overview of their major results on the topics: - Specification languages - target architectures - hardware software partitioning - verification - prototyping including especially a quantitative analysis of the hardware software codesign process demonstrated by several practical examples. On the second day the COBRA-partners will mainly demonstrate the achieved results. The following demonstrations will take place: - Specification and partitioning within the LOTOS-Codesign environment (University of Madrid) - State reachability analysis of SA/VHDL specifications (VTT) - Hardware-software codesign based on C++ (University of Tuebingen, FZI) - IRTISD Integrated Realtime System Development environment (FZI) - Hardware-software partitioning in a multiprocess environment (University of Braunschweig) - Hardware verification (Technical University of Denmark) - Prototyping and emulation (Siemens, University of Tuebingen) Location and Travel Info ============================================================================ The workshop will be held at: Sporthotel Achental Mietenkammer Strasse 65 D-83224 Grassau/Chiemgau Tel.: +49 8641 4010 Fax.: +49 8641 1758 Grassau is located about 100 km south-east of Munich between lake Chiemsee and the Alps. Travel by air: The best way from Munich airport to Grassau is to take the airport bus (leaving every 20min) to Munich main station (time about 30-40min, ca. DM 15,- one way, ca. DM 25,- return ticket), and to use the train from there to Prien or Uebersee (see also Travel by train). Travel by train: Take a train from Munich main station to Prien or to Uebersee. There take a taxi to the Sporthotel Achental (Prien to Grassau: 25km; Uebersee to Grassau 7km) Travel by car: Take the Autobahn A8 from Munich to Salzburg, direction Salzburg. Take the exit "Feldwies/Uebersee", direction Uebersee and Grassau. You will find the hotel on the right hand side of the road before entering Grassau. Reservation, Cost, and Additional Information =========================================================================== Please send the filled registration form not later than March 15th, 1996 to: Forschungszentrum Informatik z. Hd. Diana Reiter Haid-und-Neu-Strasse 10-14 D-76131 Karlsruhe or register directly at the hotel. The cost for the workshop is: Participation including lunch and breaks: DM 55,- Participation and hotel accommodation April 29th to April 30th (one night), including all meals and breaks: DM 187,- Additional night April 28th to April 29th including all meals: DM 187,- Further information: Telephone call, fax or e-mail: W. Rosenstiel University of Tuebingen Email: rosen@peanuts.informatik.uni-tuebingen.de or http://www.fzi.de/esm/cobra_ws.html Registration Form ============================================================================== I will attend the final workshop of the COBRA project Name: _________________________________________________ Affiliation: _________________________________________________ Phone/Fax: _________________________________________________ Address: _________________________________________________ _________________________________________________ _________________________________________________ ( ) I will attend the COBRA workshop (DM 55,- including one lunch and breaks, only if not combined with overnight stay at the hotel) ( ) I don't need hotel accommodation or I will contact the hotel directly ( ) I will need hotel accommodation from April 29th to April 30th (DM 187,- including all meals and breaks) ( ) I will need additional hotel accommodation from April 28th to April 29th (+ DM 187,- incl. all meals and breaks) Date: ____________________________ Signed: _________________________________ From @DBSTU1.RZ.TU-BS.DE:Ernst@ida.ing.tu-bs.de Mon Jan 15 14:39:16 1996 Return-Path: <@DBSTU1.RZ.TU-BS.DE:Ernst@ida.ing.tu-bs.de> Received: from dbstu1.rz.tu-bs.de by josef.ifi.unizh.ch with SMTP (PP) id <15991-0@josef.ifi.unizh.ch>; Mon, 15 Jan 1996 14:38:44 +0100 Received: from rzab0.rz.tu-bs.de by DBSTU1.RZ.TU-BS.DE (IBM VM SMTP V2R2) with TCP; Mon, 15 Jan 96 14:15:02 MEZ Received: from ida.ing.tu-bs.de (horaz.ida.ing.tu-bs.de) by rzab0.rz.tu-bs.de with SMTP (1.37.109.15/15.6) id AA038811579; Mon, 15 Jan 1996 14:13:00 +0100 Received: by vergil.ida.ing.tu-bs.de (4.1/SMI-4.1) id AA01528; Mon, 15 Jan 96 14:12:42 +0100 Date: Mon, 15 Jan 96 14:12:42 +0100 From: Ernst@ida.ing.tu-bs.de (Prof Ernst) Message-Id: <9601151312.AA01528@vergil.ida.ing.tu-bs.de> To: codesign-request@ifi.unizh.ch Subject: Workshop on HW/SW Co-Design Status: RO _____________________________________________________________________ WORKSHOP PROGRAM & REGISTRATION INFORMATION 4th International Workshop on Hardware/Software Co-design Codes/CASHE '96 Pittsburgh, Pennsylvania, U.S.A. Sheraton at Station Square March 18-20, 1996 Joint sponsorship ACM SIGDA, ACM SIGSOFT, IEEE CS, IEEE CAS, IFIP 10.5 _______________________________________________________________________ The increasing complexity of electronic systems requires a closer link between hardware and software development. In recent years, computer aided HW/SW co-design has developed into a new research focus in academia and industry. The Codes/CASHE (Computer Aided SW/HW Engineering) workshop is the major international forum for the presentation and exchange of ideas and advanced work, and for the identification of new rewsearch topics in this field. It addresses theoretical aspects, methods, and tools for computer aided HW/SW co-design. The workshop will consist of short oral presentations combined with poster sessions, and of group discussions on selected topics. This e-mail includes the advance program and registration information. This information may also be found on the Worldwide Web at: http://www.ece.cmu.edu/afs/ece/usr/thomas/codes.html Overview The workshop puts emphasis on discussions and open sessions rather than on conference-style presentations. The 18 selected papers are presented in 5 paper sessions which start with a 10 minute oral introduction of each paper followed by a poster discussion of all papers of a session. The proposed topics of the parallel group discussions are announced on the workshop web page together with a short introduction by the moderators. This gives everybody the opportunity to prepare for the discussions. We can still add topics. Just send an email to the program chair together with a short statement on the motivation and an outline on what should be discussed. The proposers will be asked to moderate the sessions. The results of the group discussions will be summarized in the workshop web page. Two complementary session forms allow every workshop participant to present recent work or ideas. All participants can bring a poster to the open poster session. After the workshop, we will list the titles of the posters in the workshop web page and set a pointer to the authors. The "rump" session at the end of the workshop is a plenary session divided in 5 minute slots which are assigned to anybody who wants to make a short statement on any co-design related topic which people should take home to think about, possibly some problems or new aspects which came up during the workshop or just reflections on workshop contents. If there is enough material we could include a summary of the session in the web page. Schedule Sunday, March 17: 18:00 - 19:00 Registration 19:00 - 21:00 Reception Monday, March 18: 8:00 - 9:00 Registration and Continental Breakfast 9:00 - 9:15 Welcome and Opening 9:15 - 10:30 Paper Session 1: Transformation Based Co-Design and Communication Synthesis "Embedded Architecture Co-Synthesis and System Integration" Steven Vercauteren, Bill Lin, Hugo De Man, IMEC, Leuven, Belgium "A Multi-Level Transformation Approach to HW/SW Codesign: A Case Study" Tommy King-Yin Cheung, Graham R. Hellestrand, Prasert Kanthamanon, VLSI and Systems Technology Laboratory, School of Computer Science and Engineering, University of New South Wales, Australia "Fully Parallel Hardware/Software Codesign for Multi-Dimensional DSP Applications" Michael Sheliga, Nelson Luiz Passos, Edwin Hsing-Mean Sha, Department of Computer Science and Engineering, University of Notre Dame 10:30 - 10:45 Coffee break 10:45 - 12:15 Paper Session 2: Estimation Techniques "A Co-Design Methodology Based on the Specification Language LOTOS" C. Carreras, J.C. Lspez, M.L. Lspez, C. Delgado-Kloos, N. Martmnez, L. Sanchez Universidad Politicnica de Madrid, Spain "Speed-Up Estimation for HW/SW-Systems" Wolfram Hardt, University of Paderborn, Germany; Wolfgang Rosenstiel, University of Tubingen, Germany "A Framework for Interactive Timing Constraint Analysis of Embedded Systems" Rajesh K. Gupta, Department of Computer Science, University of Illinois at Urbana-Champaign "The Interplay of Run-Time Estimation and Granularity in HW/SW Partitioning" Jorg Henkel, Rolf Ernst, Technische Universitat Braunschweig, Germany 12:15 - 13:30 Lunch 13:30 - 15:30 Panel on the RASSP-Program Organizer: Anthony J. Gadient, Advanced Technology Group, SCRA, Charleston 15:30 - 15:45 Coffee Break 15:45 - 17:30 Invited Talk: TBA Dinner on your own. Tuesday, March 19 8:00 - 9:00 Continental Breakfast 9:00 - 10:30 Paper session 3: Partitioning and Clustering "Partitioning and Exploration Stategies in the TOSCA Co-Design Flow" A. Balboni, ITLTEL_SIT, Castelletto di Settimo, Italy W. Fornaciari, CEFRIEL and Politecnico di Milano, Italy D. Sciuto, Politecnico di Milano, Italy "Process Partitioning for Distributed Embedded Systems" Junwei Hou, Wayne H. Wolf Department of Electrical Engineering, Princeton University "Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine" Reiner W. Hartenstein, Jorgen Becker, Rainer Kress University of Kaiserslautern, Germany "PACE: A Dynamic Programming Algorithm for Hardware/Software Partitioning" Peter Voigt Knudsen, Jan Madsen Department of Computer Science, Technical University of Denmark, Lyngby 10:30 - 10:45 Coffee break 10:45 - 12:00 Paper session 4: Case studies "A Model for the Coanalysis of Hardware and Software Architectures" Fred Rose, Todd Carpenter, John Shackleton, Todd Steeves, Honeywell Technology Center, Minneapolis "A Case Study in Codesign of Communication Controllers - A User Driven Approach" R. Gerndt, Institute for Applied Micoelectronics, Braunschweig, Germany "Formal Verification of Embedded Systems Based on CFSM Networks" Felice Balarin, Cadence Berkeley Laboratories, USA; Luciano Lavagno, Politecnico di Torino, Italy; Harry Hsieh, Alberto Sangiovanni-Vincentelli, Department of Electrical Engineering and Computer Science, University of California at Berkeley; Attila Jurecska, Magneti Marelli, Italy 12:00 - 13:15 Lunch 13:15 - 15:15 Group Discussions Topic 1: Representation Issues in Co-Design Moderator: Giovanni DeMicheli, Stanford University Topic 2: The Role of Flexibility in Co-Design Moderator: Rolf Ernst, University of Braunschweig, Germany 15:15 - 15:30 Coffee break 15:30 - 17:45 Open Poster Session 18:00 - 20:00 Workshop Dinner 20:00 Open discussion about workshop organization, publication issues, benchmarks, etc. Wednesday, March 20 8:00 - 9:00 Continental Breakfast 9:00 - 10:30 Paper session 5: Modeling and Simulation "Towards a Model for Hardware and Software Functional Partitioning" Frank Vahid, Thuy dm Le Department of Computer Science, University of California at Riverside "Implications of Codesign as a Natural Constituent of a Systems Engineering Discipline for Computer Based Systems" Markus Voss, Oliver Hammerschmidt, Universitdt Karlsruhe, Institut fur Mikrorechner und Automation, Germany "Uninterpreted Co-Simulation for Performance Evaluation of Hw/Sw Systems" J.P. Calvez, D. Heller, O. Pasquier IRESTE, Nantes, France "Fast and Accurate Hardware-Software Co-Simulation Using Software Timing Estimates", Claudio Passerone, Luciano Lavagno, Wilsin Gosti, Alberto Sangiovanni-Vincentelli Dept. of EE & CS, University of California at Berkeley 10:30 - 10:45 Coffee break 10:45 - 12:00 "Rump" session: 5 min. statements 12:00 End of workshop Conference Registration Form CODES/CASHE '96 Registration 4th International Workshop on Hardware/Software Co-Design Sheraton at Station Square Pittsburgh, PA USA March 18-20, 1996 Workshop Registration Form Registration and Fees To register, please print out and fill in the attached registration form, attach check and return the registration form and check in US dollars drawn on a US bank (Payable to "Codes/CASHE-96 Workshop" ) to: Professor Donald Thomas CODES/CASHE 96' Workshop Registration Electrical & Computer Engineering Dept. Carnegie Mellon University HH 2111 Pittsburgh, PA 15213 If you want to pay Late/On-Site, we ask that you still fill out the registration form and send it either by email chraska@ece.cmu.edu, fax (412) 268-6662 Attention: Jacqueline Chraska, or regular mail. This will allow us to get an accurate count for planning purposes. Last Name:_______________________________ First Name:______________________ Affiliation______________________________ACM or IEEE Membership #____________ Address: Street___________________________________________________________________ City/State________________________________________________________________ Postal Code/Country_______________________________________________________ Daytime Phone Number_____________________________________________________ Fax number______________________________________________________________ Email___________________________________________________________________ Do you have any special needs:_______________________________________________ The registration fees includes the Sunday reception, Tuesday's dinner, continental breakfasts, two lunches and break refreshments. It also includes a Proceedings to which some of the speakers have contributed papers. Advance Registration Fees Must be received on or before February 26, 1996): Members (ACM or IEEE) $ 320.00 ______________ Non-members $400.00______________ Students $200.00______________ Late/On-Site Registration Fees (after February 26, 1996): Members (ACM or IEEE) $385.00 ______________ Non-members $480.00______________ Students $240.00______________ No refund will be made unless a written request for cancellation is made before February 26, 1996. Accomodations for the CODES/CASHE '96 The Sheraton at Station Square 7 Station Square Drive Pittsburgh, Pennsylvania 15219 Tel: 412-261-2000 Toll-Free Reservations: 1-800-255-7488 Fax: 412-261-2932 A limited number of rooms have been blocked for the Codes/CASHE 96' Workshop. Be sure to make your room reservations early to take advantage of the special rate. Reservations request must be made by February 25, 1996 by 5:00 PM. Eastern Time. After this date, reservations will be based on room and rate availablilty. Rooms will be held until 6:00 PM unless guaranteed with an accepted credit card. The Hotel's check-in time is after 3:00 PM. Hotel check-out time is 12:00 noon. Cancellation policy is 48 hours prior to arrival. Hotel Rates: Single - $111.00 Double - $121.00 Tax not included. When making your Hotel reservation please state that you will be attending the Codes/CASHE 96' Workshop. From codesign-request@ifi.unizh.ch Mon Jan 22 12:19:06 1996 Return-Path: Received: from imag.imag.fr by josef.ifi.unizh.ch with SMTP (PP) id <21686-0@josef.ifi.unizh.ch>; Mon, 22 Jan 1996 12:18:46 +0100 Received: from verdon.imag.fr (verdon.imag.fr [147.171.129.20]) by imag.imag.fr (8.6.11/8.6.9) with ESMTP id MAA28770; Mon, 22 Jan 1996 12:18:37 +0100 Received: (from jerraya@localhost) by verdon.imag.fr (8.6.11/8.6.9) id MAA09197; Mon, 22 Jan 1996 12:19:32 +0100 Date: Mon, 22 Jan 1996 12:19:32 +0100 From: Ahmed Amine Jerraya Message-Id: <199601221119.MAA09197@verdon.imag.fr> X-Mailer: Mail User's Shell (7.2.5 10/14/92) To: isss-people@ics.UCI.EDU, codesign@ifi.unizh.ch Subject: Synthesis paper for Euro-VHDL Cc: jean.mermet@imag.fr Status: RO Dear Colleague, I would like to bring your attention to the deadline for submitting papers to Euro-VHDL which is very closed: February 2, 1996. This year this will be hard Dead-line. In particular the program includes a full topic on synthesis. This is an ideal forum to publish your recent work in important area such as: - HLS from VHDL - RTL Synthesis from VHDL - Logic synthesis from VHDL - Synthesis benchmarks - Synthesis packages - Synthesis semantics - Synthesis standardization - Synthesis for low power Euro-VHDL will take place in conjunction with Euro-DAC in Ceneva, Switzerland on September 16-20, 1996. If you have not received a call for papers or would like to get additional information, please send an E-mail to jean.mermet@imag.fr Best Regards Ahmed Amine Jerraya (Euro-VHDL-96 Topic Chair, "Synthesis) -- ------ Ahmed Amine JERRAYA, Ph. D | Office: (+33) 76 57 47 59 ------ System-Level Synthesis Group | Home : (+33) 76 87 61 74 ------ TIMA/INPG 46 Ave Felix Viallet | Fax : (+33) 76 47 38 14 ------ F-38031 Grenoble Cedex FRANCE | E_mail: ahmed.jerraya@imag.fr From codesign-request@ifi.unizh.ch Fri Feb 2 11:56:26 1996 Return-Path: Received: from ns.DBresearch-berlin.de by josef.ifi.unizh.ch with SMTP (PP) id <04766-0@josef.ifi.unizh.ch>; Fri, 2 Feb 1996 11:07:20 +0100 Received: by mail.DBresearch-berlin.de (/\==/\ Smail3.1.28.1) from caesar.DBresearch-berlin.de with smtp id ; Fri, 2 Feb 96 11:06 MET Message-Id: Date: Fri, 2 Feb 96 11:06 MET From: vhanx@DBresearch-berlin.de (Reinhard von Hanxleden) Received: by caesar.DBresearch-berlin.de (4.1/SMI-4.1) id AA10063; Fri, 2 Feb 96 11:06:15 +0100 To: codesign@ifi.unizh.ch, codes-all@eeel.nist.gov Subject: Co-design Bibliographies? Status: RO Dear Co-designers, are there any publicly available bibliographies on hw/sw codesign around, preferably in BibTeX? Thanks, -- Reinhard > Dr. Reinhard v. Hanxleden Daimler Benz AG phone: +49 (30) 399 82 291 Responsive Systems (F3S/R) fax: +49 (30) 399 82 107 Alt-Moabit 96a e-mail: vhanx@DBresearch-berlin.de D-10559 Berlin Germany From codesign-request@ifi.unizh.ch Tue Feb 13 18:41:38 1996 Return-Path: Received: from stepsun.uni-kl.de by josef.ifi.unizh.ch with SMTP (PP) id <14007-0@josef.ifi.unizh.ch>; Tue, 13 Feb 1996 18:25:29 +0100 Received: from uklirb.informatik.uni-kl.de by stepsun.uni-kl.de id aa20019; 13 Feb 96 18:25 MET Received: from irz1.informatik.uni-kl.de by uklirb.informatik.uni-kl.de id aa09207; 13 Feb 96 18:18 MET Received: by irz1.informatik.uni-kl.de (5.x/SMI-SVR4) id AA07901; Tue, 13 Feb 1996 18:18:19 +0100 From: Juergen Becker AG Hartenstein Message-Id: <9602131718.AA07901@irz1.informatik.uni-kl.de> Subject: codesign course equipment? To: codesign@ifi.unizh.ch Date: Tue, 13 Feb 1996 18:18:19 +0100 (MET) Cc: AG Hartenstein X-Mailer: ELM [version 2.4 PL24] Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Status: RO Hi codesigners, does anybody know about an equipment for an undergraduate course of Hw/Sw Co-Design like an easy interface from a high level programming language to a HDL, so that a cosimulation for short examples would be possible? Or does someone have experience with such an infrastructure and would it be possible to receive it for teaching purposes? Many thanks in advance for possible help and I look forward to your comments, regards, Juergen --------------------------------------------------------------------------- Juergen Becker Universitaet Kaiserslautern Fachbereich Informatik (Bau 12/449) Postfach 3049 67653 Kaiserslautern Tel.: +49 631 205-2625 Fax: +49 631 205-2640 email: jbecker@informatik.uni-kl.de --------------------------------------------------------------------------- From codesign-request@ifi.unizh.ch Wed Feb 14 11:55:48 1996 Return-Path: Received: from polv2k.polito.it by josef.ifi.unizh.ch with SMTP (PP) id <28344-0@josef.ifi.unizh.ch>; Wed, 14 Feb 1996 11:55:27 +0100 Received: by polv2k.polito.it (5.57/Ultrix3.0-C) id AA05209; Wed, 14 Feb 96 11:56:21 +0100 Message-Id: <9602141056.AA05209@polv2k.polito.it> To: Juergen Becker AG Hartenstein Cc: codesign@ifi.unizh.ch Subject: Re: codesign course equipment? In-Reply-To: Your message of "Tue, 13 Feb 96 18:18:19 +0100." <9602131718.AA07901@irz1.informatik.uni-kl.de> Date: Wed, 14 Feb 96 11:56:20 +0100 From: Luciano Lavagno Status: RO Juergen Becker AG Hartenstein writes: > does anybody know about an equipment for an undergraduate > course of Hw/Sw Co-Design like an easy interface from > a high level programming language to a HDL, so that a > cosimulation for short examples would be possible? Depending on when you need it and what level of support you would like, you can try: 1) esterel (free of charge for universities): maps from the esterel language (excellent for teaching because very simple and terse) to C, that can be simulated (graphic debugger) and compiled. It can also generate HW, but no interface is provided. E-mail to esterel-request@cma.cma.fr 2) statecharts (and analogues; university discounts, as far as I know): maps from the graphical hierarchical state diagram to C or synthesizable VHDL or verilog (similar to esterel in many respects, but commercial, with all pros and cons). http://www.ilogix.com/ 3) ptolemy (public domain; good mostly for Data Flow): block diagrams to software for various DSPs; excellent graphical interface. http://ptolemy.eecs.berkeley.edu/ 4) polis (public domain; should be released in about a month): similar capabilities and entry language as esterel (plus a rudimentary state diagram editor), but in addition automatic generation of real-time operating system and interfaces for partitioned system. Uses ptolemy for co-simulation (it generates a ptolemy simulation model from the esterel spec). More capabilities but less guarantees than 1-3. http://www-cad.eecs.berkeley.edu/Respep/Research/hsc/abstract.html This is all I know... Ciao !!!! Luciano -- Luciano Lavagno +39-11-564-4150 (fax 4099) lavagno@polito.it http://www-cad.eecs.berkeley.edu/~luciano/ http://www.polito.it/~lavagno Dip. di Elettronica, Politecnico, C. Duca degli Abruzzi 24, 10129 Torino, ITALY From codesign-request@ifi.unizh.ch Wed Feb 14 14:05:20 1996 Return-Path: Received: from cma.cma.fr by josef.ifi.unizh.ch with SMTP (PP) id <01780-0@josef.ifi.unizh.ch>; Wed, 14 Feb 1996 14:05:08 +0100 Original-Received: by cma.cma.fr, Wed, 14 Feb 96 14:03:17 +0100 PP-warning: Illegal Received field on preceding line Message-Id: <9602141303.AA29718@cma.cma.fr> To: Luciano Lavagno Cc: codesign@ifi.unizh.ch Subject: Re: codesign course equipment? In-Reply-To: Your message of "Wed, 14 Feb 96 11:56:20 +0100." <9602141056.AA05209@polv2k.polito.it> Date: Wed, 14 Feb 96 14:03:17 +0100 From: Ellen Sentovich Status: RO > 1) esterel (free of charge for universities): maps from the esterel language > (excellent for teaching because very simple and terse) to C, that can be > simulated (graphic debugger) and compiled. It can also generate HW, but > no interface is provided. E-mail to esterel-request@cma.cma.fr FYI, there is also a brief Web page: http://cma.cma.fr/Esterel Ellen From codesign-request@ifi.unizh.ch Wed Feb 14 13:36:10 1996 Return-Path: Received: from mailgate.ericsson.se by josef.ifi.unizh.ch with SMTP (PP) id <01182-0@josef.ifi.unizh.ch>; Wed, 14 Feb 1996 13:35:58 +0100 Received: from eua.ericsson.se (eua.ericsson.se [134.138.132.16]) by mailgate.ericsson.se (8.6.11/1.0) with SMTP id NAA10352 for ; Wed, 14 Feb 1996 13:35:35 +0100 Received: from ms.eua.ericsson.se by eua.ericsson.se (4.1/EUA-2.1) id AA12151; Wed, 14 Feb 96 13:35:33 +0100 Received: from euax9i1c33.eua.ericsson.se by ms.eua.ericsson.se (4.1/MS-2.1) id AA03577; Wed, 14 Feb 96 13:35:33 +0100 From: Fredrik.Ostman@uab.ericsson.se (Fredrik Ostman) Received: by euax9i1c33.eua.ericsson.se (5.x/client-1.3) id AA08923; Wed, 14 Feb 1996 13:35:32 +0100 Date: Wed, 14 Feb 1996 13:35:32 +0100 Message-Id: <9602141235.AA08923@euax9i1c33.eua.ericsson.se> To: codesign@ifi.unizh.ch Subject: Re: codesign course equipment? X-Sun-Charset: US-ASCII Status: RO +-----< Juergen Becker AG Hartenstein > | an easy interface from | a high level programming language to a HDL +- Juergen, Have a look at Synthesias HW/SW Cosimulation tool at http://www.synthesia.se/products/hwsw/hwsw.htm and http://www.synthesia.se/products/hwsw/hwswapp.htm They should have a fair deal for universities. Another possibility is EagleI: http://www.eagledes.com/ Both these tools are developments from the cosimulation and Early Integration work I was involved in at Ericsson in the early nineties, presented at Grassau 92 and Igls 93 (and in the Rozenblit book). They should involve very limited set-up overhead if you have HLPL and HDL environments in place. We used C++ and (Vantage) VHDL, but I think there are more options now. Hope this helps, ______ _~ (_/_ _ _ _/) _ . /) / ) , _/) _ __/ _/(_(/_(/__/(_/_/Z_ (_/_/)_/__/))_(I_/)_ Fredrik :Ostman Switch Lab, Ericsson Telecommunication Systems Laboratories Box 1505/Armborstv:agen 14, S-125 25 :ALVSJ:O, Stockholm, Sweden +46 (8) 727 3348, fax +46 (8) 749 0594, Fredrik.Ostman@uab.ericsson.se From codesign-request@ifi.unizh.ch Fri Feb 16 21:36:56 1996 Return-Path: Received: from sol.UVic.CA by josef.ifi.unizh.ch with SMTP (PP) id <14341-0@josef.ifi.unizh.ch>; Fri, 16 Feb 1996 21:36:10 +0100 Received: from shannon.UVic.CA by sol.UVic.CA (4.1/SMI-4.1.3-UVic-2.69MX) id AA12332; Fri, 16 Feb 96 12:31:19 PST Received: by shannon.UVic.CA (4.1/UVicCScServer-1.9) id AA07008; Fri, 16 Feb 96 12:28:59 PST Date: Fri, 16 Feb 96 12:28:59 PST From: wgardner@shannon.uvic.ca (Bill Gardner) Message-Id: <9602162028.AA07008@shannon.UVic.CA> To: dsharp1@shannon.uvic.ca Subject: Pittsburgh conf home page Cc: bookmarks.html@shannon.uvic.ca, codesign@ifi.unizh.ch, grep@shannon.uvic.ca, mail@shannon.uvic.ca Status: RO The next mail will have the http reference in it... \ Bill From codesign-request@ifi.unizh.ch Sat Feb 24 08:46:46 1996 Return-Path: Received: from vttoulu.tko.vtt.fi by josef.ifi.unizh.ch with SMTP (PP) id <28517-0@josef.ifi.unizh.ch>; Sat, 24 Feb 1996 08:37:43 +0100 Received: from raisun3 (raisun3 [130.188.91.54]) by vttoulu.tko.vtt.fi (8.7.1/8.7.1) with SMTP id JAA12418 for ; Sat, 24 Feb 1996 09:37:26 +0200 Received: by raisun3 (4.1/SMI-4.1) id AA06522; Sat, 24 Feb 96 09:37:24 +0200 Date: Sat, 24 Feb 96 09:37:24 +0200 From: ppu@raisun3.tko.vtt.fi (Petri Pulli) Message-Id: <9602240737.AA06522@raisun3> To: codesign@ifi.unizh.ch Subject: Virtual Prototyping /Codesign Status: RO If you are interested in applying virtual reality techniques in codesign for hand-held consumer electronics and telecommunication products, have a look at our research environment. We just got the web pages done: http://www.ele.vtt.fi/projects/vrp/vrp.html Petri Pulli Dr, Research Professor VTT Electronics & University of Oulu Finland From codesign-request@ifi.unizh.ch Fri Feb 23 19:06:08 1996 Return-Path: Received: from hplb.hpl.hp.com by josef.ifi.unizh.ch with SMTP (PP) id <26965-0@josef.ifi.unizh.ch>; Fri, 23 Feb 1996 19:05:51 +0100 Received: from onex.hpl.hp.com (rtaylor.hpl.hp.com) by hplb.hpl.hp.com; Fri, 23 Feb 1996 18:03:41 GMT Received: by onex.hpl.hp.com (1.37.109.16/15.6+ISC) id AA195968621; Fri, 23 Feb 1996 18:03:41 GMT From: Tarek Ben Ismail Message-Id: <9602231803.ZM19594@rtaylor.hpl.hp.com> Date: Fri, 23 Feb 1996 18:03:41 +0000 X-Mailer: Z-Mail (3.2.0 06sep94) To: hlsw-people@ics.UCI.EDU, isss-people@ics.UCI.EDU, ifip-10.5@ics.UCI.EDU, codesign@ifi.unizh.ch, call.europar@lip.ens-lyon.fr, francovhdl@cns.cnet.fr Subject: New Email Address Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Status: RO To all Codesign and System Synthesis people, Please note my new email address : tbi@hplb.hpl.hp.com Sorry if you receive this message more than once, Thank you for your understanding. Regards, Tarek. P.S. My old email (Tarek.Ismail@imag.fr) can be used as a backup in case of delivery problems. -- _________________________________________________________________ Tarek BEN ISMAIL, Ph.D. E-mail : tbi@hplb.hpl.hp.com Hewlett-Packard Labs office : +44 (0) 117 922 8742 Filton Road, Stoke Gifford fax : +44 (0) 117 922 8925 Bristol BS12 6QZ, UK. (omit 0 if calling from outside UK) _________________________________________________________________ From codesign-request@ifi.unizh.ch Wed Mar 6 11:17:43 1996 Return-Path: Received: from 131.246.136.50 by josef.ifi.unizh.ch with SMTP (PP) id <03886-0@josef.ifi.unizh.ch>; Wed, 6 Mar 1996 11:17:35 +0100 Received: from uklirb.informatik.uni-kl.de by stepsun.uni-kl.de id ab28205; 6 Mar 96 11:17 MET Received: from irz1.informatik.uni-kl.de by uklirb.informatik.uni-kl.de id aa16084; 6 Mar 96 11:10 MET Received: by irz1.informatik.uni-kl.de (SMI-8.6/SMI-SVR4) id LAA02411; Wed, 6 Mar 1996 11:10:25 +0100 From: Juergen Becker AG Hartenstein Message-Id: <199603061010.LAA02411@irz1.informatik.uni-kl.de> Subject: H/S Co-Design Bibliography To: codesign@ifi.unizh.ch Date: Wed, 6 Mar 1996 11:10:25 +0100 (MET) Cc: hartenst@rhrk.uni-kl.de X-Mailer: ELM [version 2.4 PL24] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Status: RO please, excuse me for the following book advertisement: Klaus Buchenrieder: Hardware/Software Co-Design An annotated Bibliography; IT Press 1995 - - ISBN 0-9639887-7-8 or (Europe): ISBN 3-929814-07-2 available from IT Press, Chicago, Illinois, USA, Fax: (312) 871-6680 US-Dollars 39.95 Fax in Europe: (+49) 7251 - 14823 Best regards Juergen Becker --------------------------------------------------------------------------- Juergen Becker Universitaet Kaiserslautern Fachbereich Informatik (Bau 12/449) Postfach 3049 67653 Kaiserslautern Tel.: +49 631 205-2625 Fax: +49 631 205-2640 email: jbecker@informatik.uni-kl.de --------------------------------------------------------------------------- From codesign-request@ifi.unizh.ch Wed Apr 3 14:45:12 1996 Return-Path: Received: from imag.imag.fr by josef.ifi.unizh.ch with SMTP (PP) id <17442-0@josef.ifi.unizh.ch>; Wed, 3 Apr 1996 14:44:59 +0200 Received: from verdon.imag.fr (verdon.imag.fr [147.171.129.20]) by imag.imag.fr (8.6.11/8.6.9) with ESMTP id OAA12822; Wed, 3 Apr 1996 14:44:53 +0200 Received: (from jerraya@localhost) by verdon.imag.fr (8.6.11/8.6.9) id OAA15249; Wed, 3 Apr 1996 14:45:29 +0200 Date: Wed, 3 Apr 1996 14:45:29 +0200 From: Ahmed Amine Jerraya Message-Id: <199604031245.OAA15249@verdon.imag.fr> X-Mailer: Mail User's Shell (7.2.5 10/14/92) To: isss-people@ics.UCI.EDU, codesign@ifi.unizh.ch Subject: 7th IEEE International Workshop on Rapid System Prototyping Status: RO 7th IEEE International Workshop on Rapid System Prototyping 19-21 June, 1996 Porto Carras, Thessaloniki, Greece Advanced Program The IEEE International Workshop on Rapid System Prototyping presents and explores the trends in rapid prototyping of Computer Based Systems including, but not limited to, communications, information, and manufacturing systems. The seventh annual workshop will focus on improved approaches to resolving prototyping issues and problems raised by incomplete specifications, increased system complexity and reduced time to market requirements for a multitude of products. Wednesday, June 19, 1996 9:00 AM Opening, Welcoming Remarks 9:15 AM Invited Talk (TBD) 10:15-10:45 Coffee Break 10:45-12:00 Session 1: Emulation 1.1 "Design Verification based on Hardware Emulation", H. N. Nguyen, M. Thill - Bull S.A., France 1.2 "A Novel Approach to Real-Time Verification of Transport System Design using FPGA based Emulator", K. Hayashi, T. Miyazaki, K. Shirakawa, K. Yamada, N. Ohta - NTT Optical Network Systems Labs., Japan 1.3 "An FPGA-Based Codevelopment Platform", E. Mosanya, M. Goeke, J. Linder, J-Y. Perrier, F. Rampogna, E. Sanchez - EPFL, Switzerland 12:00 Lunch 13:30-15:10 Session 2: Hardware Software Codesign 2.1 "Aspects of System Modelling in Hardware/Software Partitioning", P. Voigt Knudsen, J. Madsen - Technical University of Denmark, Denmark 2.2 "Automatic Generation of Interprocess Communication in the PARAGON-System", X. Xiong, P. Gutberlet, W. Rosenstiel - Forschungszentrum Informatik Karlsruhe, Germany 2.3 "Hierarchical Partitioning in a Rapid Prototyping Environment", U. Ober, H.J. Herpel, M. Glesner - Darmstadt University of Technology, Germany 2.4 "Capturing Time Constraints by using Petri-nets in the Context of Hardware/Software Codesign", P. Romero Martins Maciel, Edna Barros - University of Pernambuco, Brazil 15:10 Coffee Break 15:40- 17:20 Session 3: Rapid System Prototyping for Telecom 3.1 "Rapid Prototyping of a CATV Network Termination for ATM-Based Video-on- Demand Services", V. Vande Keere, R. Staelens, J. Vandewege - University of Gent/INTEC-IMEC, Belgium 3.2 "Embedded Test Environment", S. Martin, V. Olive - France Telecom/CNET, France 3.3 "Real-time Emulation for ATM Switching Systems in Broadband ISDN", T. Matsumura, N. Yamanaka - NTT Network Service Systems Labs., Japan, R. Yamaguchi, K. Ishikawa - NTT LSI Labs., Japan 3.4 "Rapid Prototyping System from Message Sequence Chart Based Protocol Specification ", T. Hoshino, K. Ishikawa - NTT LSI Labs., Japan Thursday, June 20, 1996 9:00-10:00 Invited Talk (TBD) 10:00-10:30 Coffee Break 10:30-12:10 Session 4: Cosimulation 4.1 "An Integrated Hardware-Software Cosimulation Environment with Automated Interface Generation", K. Kim, Y. Kim, Y. Shin, K. Choi - Seoul National University, Korea 4.2 "Automatic Generation of Interfaces for Distributed C-VHDL Cosimulation of Embedded Systems: an Industrial Experience", C. Valderrama - TIMA Lab, F. Naabal - TIMA Lab/SGS-Thomson Microelectronics, A.A. Jerraya - TIMA Lab, France 4.3 "Simulating Hardware, Software and Electromechanical Parts Using Communicating Simulators", N.C. Petrellis, A.N. Birbas, M.K. Birbas, E.P. Mariatos, G.D. Papadopoulos - University of Patras, Greece 4.4 "A Smoothly Upgradable Approach to Virtual Emulation of HW/SW Systems", M. Borgatti, R. Rambaldi, G. Gori, R. Guerrieri - Universita degli studi di Bologna, Italy 12:00 Lunch 13:30-15:10 Session 5: System Level Specification 5.1 "Object Oriented Prototyping at the System Level: An Image Reconstruction Application Example", E.P. Mariatos, M.K. Birbas, A.N. Birbas, N. Petrellis - University of Patras, Greece 5.2 "HW/SW Specification using OOM Techniques", M. Calba, J.P. Teixeira, I.C. Teixeira - INESC/IST, Portugal 5.3 "A Multi Formalisms Prototyping Approach from Formal Description to Implementation of Distributed Systems", A. Diagne, F. Kordon, - University P. &M. Curie, France 5.4 "Fast Prototyping of Memory Models in VHDL for Hardware Emulation", K. O'Brien, S. Maginot - LEDA S.A., France 15:10-15:40 Break 15:40-17:20 Session 6: Design Methods 6.1 "New Design and Prototyping Methods are needed in Missile Electronics Industry", M. Foulon, B. Foucault - Matra Defense, France 6.2 "Industrial Approach in Design Methodologies for Mobile Communication Systems", S. Blionas, D.E. Metafas, H.C. Karathanasis - Hellenic Telecommunications & Electronics Industry, Greece 6.3 "ASIC Prototyping With Reprogrammable Implementations Of Large ASICs", D. Brasen - MINC/IST, France, A. Abbara, H. Bogushevitsh - INPG/CSI, France, G. Saucier - MINC/IST, France 6.4 "Rapid-Prototyping of Embedded Systems via Reprogrammable Devices", P. Giusto, S. Cardelli, A. Jurecska - Magneti Marelli S.p.A., Italy, L. Lavagno - CADENCE, USA, A.S. Vanni Vincentelli - U.C. Berkeley, USA Friday, June 21, 1996 08:30-10:10 Session 7: Design Cases 7.1 "C0: The Chameleon 64-bit Microprocessor ASIC Prototype", B. Ramanadin, F. Pogodalla - SGS-Thomson Microelectronics, France 7.2 "Rapid-Prototyping of a CAN-Bus Controller: A Case Study", A. Kirschbaum, F.M. Renner, A. Wilmes, M. Glesner - Darmstadt Univ. of Technology, Germany 7.3 "Rapid Prototyping of a Communication Controller for the CAN Bus", A. Winter, D. Bittruf, Y. Tanurhan, K.D. Mller-Glaser - Forschungszentrum Informatik Karlsruhe, Germany 7.4 "Fast Prototyping Based on Generic and Synthetizable VHDL Models; A Case Study: punctured Viterbi Decoders", C. Deltoso - France Telecom/CNET, France, C. Joanblanq - CCETT, France, M. Cand, P. Senn - France Telecom/CNET, France 10:10-10:40 Coffee Break 10:40-12:20 Session 8: Algorithms for Rapid System Prototyping 8.1 "Implementing DSP Applications on Heterogeneous Targets Using Minimal Size Data Buffers", M. Ad, R. Lauwereins, J.A. Peperstraete - Katholieke Universiteit Leuven, Belgium 8.2 "A Virtual Prototyping Environment", R. Klein - Mentor Graphics, USA 8.3 "Prototyping and Reengineering of Microcontroller-Based Systems", L. Carro, Pereira, A. Suzim - UFRGS, Brazil 8.4 "MCG: A Correct-by-Design Multichip Module Router with Crosstalk Avoidance", J.D. Carothers, D. Li, T. Hameenanttila - The University of Arizona, USA LOCATION The Workshop will be held in Porto Carras in Halkidiki, Greece. Porto Carras is a sea resort close to the city of Thessaloniki. It is built along a spectacular coast on the Aegean sea and is surounded with pine trees and vineyards. The resort cators to both active sports enthousiasts and to those who prefer quiet walks and spending time by the water while enjoying beautiful sunsets. TRANSPORTATION Transportation will be provided to the resort from the Macedonia Airport. A bus will be scheduled to carry the participants at a time convenient to all. This time will be determined by the arrival information provided by the attendants and will be conveyed to them at least 2 weeks before June 18. REGISTRATION & HOTEL INFORMATION All Information about Registration and Venue is available at WWW at:http://www.ece.arizona.edu/conferences/rsp96 ---------------------------------------- Organization Committee: General Chair N. Kanopoulos - DCT Program Chair, A.A. Jerraya - TIMA Laboratory Publicity Chair, J.D. Carothers - Univ. of Arizona Program Committee: K. Anderson - Siemens T. Antonakopoulos - Univ. of Patras J. Arnold - IDA Supercomputing Research Ctr J. Beetem - MITRE S. Blionas - Intracom J-Y. Brunel - Philips V. Calandra - Zycad B. Candaele - Thomson-CSF B. Courtois - TIMA Laboratory W. Debany - Rome Laboratory A. Dollas - Technical Univ. of Crete M. Engels - Katholieke Univ. Leuven P. Fiore - Lockheed M. Glesner - Technische Hochschule Darmstadt P. Henderson - Univ. of Southampton T. Hoshino - NTT P. Hulina - Penn State Univ. F. Kordon - Univ. Paris IV Lab MASI R. Lauwereins - Katholieke Univ. Leuven H.N. Nguyen - Bull S. Note - Philips ITCL V. Olive - France Telecom B. Rector - U.S. Dept. of Defense Y. Tanurhan - FZI C. Tong - Colorado State Univ. S. Winkler - NIST N. Zervos - AT&T Workshop Registration Registration form, 7th RSP: Please type or print, make sure your name appears on the payment document and give your IEEE membership number. Last name: .............................................................. First name: ............................................................. Affiliation ................... Membership # ................... Address: (street).................................................................... (city)...................................................................... (state/country).......................................................... (postal code)............................................................. (fax)....................................(phone)......................... (email).................................................................... The registration package includes both the workshop registration and the hotel registration and should be submittted with a single payment to the general chair by bank check or a personal check drawn in US funds as follow: Before May 24 After May 24 IEEE Member $180 $210 Non IEEE Member $210 $240 Student $50 $50 The workshop registration includes the attendance of all sessions and a copy of the workshop proceedings. Hotel Registration SITHONIA BEACH HOTEL PORTO CARRAS - 630 81 Halkidiki-Greece Telephone: (0375) 71 381. 71 221 Fax (0375) 72 130 DATE OF ARRIVAL:............................................... DATE OF DEPARTURE:.......................................... CONFERENCE RATES: [ ] $420 (per person double occupancy) [ ] $500 single The hotel fee includes: - Round trip transfer from the Macedonia Airport (40km) - Wellcome cocktail and dinner on the 18th - Breakfast, lunch and coffee breaks on the 19, 20, 21 (no lunch on the 21st) - Galla dinner on the 19th - Greek night dinner on the 20th - 3 nights of accomodation - Help desk for the duration of the workshop A number of short excursions will be available for an added fee. Sign-up sheets will be provided at the site of the workshop. Participants wishing to extend their stay can do so at cost of $144 (double room, half-board) or $100 (single, half- board) per day. PAYMENT: Amount Registration ............. Hotel ............. Extra nights ............. TOTAL ............. CREDIT CARD TYPE.............................................. CREDIT CARD NUMBER........................................ EXPIRY DATE: ...................................................... SIGNATURE: ........................................................ Please return this form directly to: Nick Kanopoulos Data Communications Technologies P.O. Box 12198 3040 Cornwallis Road Research Triangle Park, NC 27709 (919) 541-7341 (919) 541-6515 fax rsp@rti.org -- ------ Ahmed Amine JERRAYA, Ph. D | Office: (+33) 76 57 47 59 ------ System-Level Synthesis Group | Home : (+33) 76 87 61 74 ------ TIMA/INPG 46 Ave Felix Viallet | Fax : (+33) 76 47 38 14 ------ F-38031 Grenoble Cedex FRANCE | E_mail: ahmed.jerraya@imag.fr From codesign-request@ifi.unizh.ch Tue Apr 16 11:42:44 1996 Return-Path: Received: from tik1.ethz.ch by josef.ifi.unizh.ch with SMTP (PP) id <01163-0@josef.ifi.unizh.ch>; Tue, 16 Apr 1996 11:42:38 +0200 Received: from tec15.ethz.ch (tec15 [129.132.119.15]) by tik1.ethz.ch (8.7.5/8.7.3) with ESMTP id LAA10299; Tue, 16 Apr 1996 11:42:25 +0200 (MET DST) From: Juergen Teich Received: (from teich@localhost) by tec15.ethz.ch (8.7.5/8.7.3) id LAA01274; Tue, 16 Apr 1996 11:42:22 +0200 (MET DST) Message-Id: <199604160942.LAA01274@tec15.ethz.ch> Subject: The Zurich approach to CODE SIGN To: codesign@ifi.unizh.ch Date: Tue, 16 Apr 1996 11:42:21 +0200 (MET DST) Cc: blickle@tik.ee.ethz.ch (Tobias Blickle), thiele@tik.ee.ethz.ch (Lothar Thiele) X-Mailer: ELM [version 2.4 PL24 PGP6] Content-Type: text Status: RO The following report is now avaliable from the WWW describing the Zurich approach to System Synthesis: "System-Level Synthesis Using Evolutionary Algorithms" Tobias Blickle, Juergen Teich, Lothar Thiele Institut TIK, ETH Zurich, Gloriastr. 35, CH-8092 Zurich, Switzerland. ABSTRACT: ======== In this paper, we consider system-level synthesis as the problem of optimally mapping an algorithm-level specification onto a heterogeneous hardware/software architecture. This problem requires (1) the selection of the architecture (allocation) including general purpose and dedicated processors, ASICs, buses and memories, (2) the mapping of the algorithm onto the selected architecture in space (binding) and time (scheduling) and (3) the design space exploration with the goal to find a set of implementations that satisfy a number of constraints on cost and performance. Existing methodologies often consider a fixed architecture, perform the binding only, do not reflect the tight interdependency between binding and scheduling, require long run-times preventing design space exploration or yield only one implementation with optimal cost. Here, a model is introduced that handles all mentioned requirements and allows the task of system-synthesis to be specified as an optimization problem. Furthermore, the application of an Evolutionary Algorithm to solve this problem is described. Available from http://www.tik.ee.ethz.ch/Publications/TIK-Reports/TIK-Report16abstract.html or http://www.tik.ee.ethz.ch/~teich/ With friendly regards, Juergen ************************************************************************ Dr. Juergen Teich Institut fuer Technische Informatik und Kommunikationsnetze (TIK) Computer Engineering and Communication Networks Lab Eidgenoessische Technische Hochschule (ETH) Zuerich Swiss Federal Institute of Technology (ETH) Zuerich Mail: Institut TIK der ETHZ ETZ-G 86 Gloriastr.35 CH-8092 Zuerich Switzerland Tel: +41-1-63-27037 Fax: +41-1-63-21035 E-Mail: teich@tik.ee.ethz.ch WWW: http://www.tik.ee.ethz.ch/~teich ************************************************************************ From codesign-request@ifi.unizh.ch Thu May 2 09:08:13 1996 Return-Path: Date: Thu, 2 May 1996 08:07:28 +0100 (BST) From: Dr Richard Taylor To: codesign@ifi.unizh.ch Subject: Hewlett-Packard Laboratories Message-Id: Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Status: RO Dear Colleagues, We currently have several vacancies for researchers with expertise in hig high performance compilers, distributed systems, and real time systems. We are looking for people who are just completing (or about to complete) their PhDs (or exceptionally MScs) in these areas. Post docs with several years of research experience are also of interest. The work is all based within the codesign group at Hewlett-Packard Laboratories, Europe. I enclose a brief description the type of people we are after (more details of the labs are available at http://www-hplb.hpl.hp.com/). Our role within HP is to provide leadership in the area of low cost, high performance embedded systems. This covers many areas, from dependability and reliability through system synthesis and compilation for/optimization of wild architectures. Labs is a fun place to work - a heady mixture of academia and industry (we are one step away from the R&D groups that support operating divisions), resources are good and the work challenging. Anyway, if you do know of anyone who might be interested, please ask them to drop a cv to either myself (rwt@hplb.hpl.hp.com) or James Harrison (james@hplb.hpl.hp.com) and we can talk about the posts in more detail. *Outline Job Descriptions* The mission of the Appliance Computing Department of Hewlett-Packard Laboratories, Bristol is to take leading edge research from areas such as super computing, safety-critical systems, and "non traditional" language implementation into high volume, low cost environments. This requires considerable skill, deep technical knowledge and a strong vision of what the big markets of the future will require. The core of this work is involved with developing versatile, flexible and powerful processors for products that are moving out of the domain of the office and into the home. The successful applicants will have expertise in one or more of the following areas: current state-of-the-art compiler techniques, distributed, real time & embedded systems. As part of small teams they must be able to work effectively in a research environment with minimal supervision but as effective and influential team contributors, both on technical aspects and on project strategy and direction. For more details, please get in touch with either Richard Taylor ( (44) 117 922 9545, rwt@hplb.hpl.hp.com) or James Harrison ( (44) 117 922 8289, james@hplb.hpl.hp.com). Richard Taylor, __o o __o __o Hewlett-Packard Laboratories, Bristol, UK. `\<, \\_/\_, `\<,-`\<, rwt@hplb.hpl.hp.com O/ O O O O/----/ O phone : +44 (0) 117 922 9545 fax : +44 (0) 117 922 8925 From codesign-request@ifi.unizh.ch Fri May 10 12:25:17 1996 Return-Path: Received: from pol88b.polito.it by josef.ifi.unizh.ch with SMTP (PP) id <09456-0@josef.ifi.unizh.ch>; Fri, 10 May 1996 12:25:10 +0200 Received: from polgen2.polito.it by polito.it (PMDF V4.2-15 #3020) id <01I4JH03VOEO9KM6II@polito.it>; Fri, 10 May 1996 12:24:15 GMT+1 Received: from polgen9.polito.it by polgen2.polito.it (4.1/SMI-4.1) id AA01465; Fri, 10 May 96 12:24:40 +0100 Date: Fri, 10 May 1996 12:24:40 +0100 From: andrea@polgen2.polito.it (Andrea Di Blas) Subject: TBPS Codesign course announcement To: codesign@ifi.unizh.ch Message-id: <9605101124.AA01465@polgen2.polito.it> X-Envelope-to: codesign@ifi.unizh.ch Content-transfer-encoding: 7BIT Status: RO Dear colleagues, Europractice Training and Best Practice Service is organizing several basic and advanced training courses. In particular, we would like to draw your attention on the course titled "HW/SW Codesign for Embedded Control Application" that will be held in Turin (Italy) on May 27-28. For more information, please have a look at the TBPS home page at http://cie.it.dtu.dk/tbps or contact us: Prof. Pierluigi CIVERA, Dr. Helma ELENS, Eng. Andrea DI BLAS COREP - Politecnico di Torino C.so Duca degli Abruzzi 24 I-10129 ITALY phone: +39 11 564 4080 or 4004, fax: +39 11 564 4112 or 5199 e-mail: civera@polito.it, elens@polito.it diblas@polito.it Best regards, Andrea Di Blas From pilz Mon May 13 09:37:50 1996 Subject: FPGA'97 Call for Papers (fwd) To: codesign@ifi.unizh.ch Date: Mon, 13 May 1996 09:37:50 +0200 (MET DST) X-Mailer: ELM [version 2.4 PL11] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 8bit Content-Length: 3107 Status: RO FPGA'97: Call for Papers 1997 ACM/SIGDA Fifth International Symposium on Field-Programmable Gate Arrays Sponsored by ACM SIGDA, with support from Altera, Xilinx, and Actel Monterey Beach Hotel, Monterey, California February 9-11, 1997 (Web page: http://www.ece.nwu.edu/~hauck/fpga97) The annual ACM/SIGDA International Symposium on Field-Programmable Gate Arrays is the premier conference for presentation of advances in all areas related to the FPGA technology. The topics of interest of this symposium include, but are not limited to: o Advances in FPGA architectures, including design of programmable logic blocks, programmable interconnects, programmable I/Os, and development of new FPGAs and field-configurable memories. o New CAD algorithms and tools for FPGAs, including new algorithms for sequential and combinational logic optimization, technology mapping, partitioning, placement, routing, and development of new FPGA synthesis or layout systems. o Novel applications of FPGAs, including rapid prototyping, logic emulation, reconfigurable custom computing, and dynamically reconfigurable applications. o Advances in field-programmable technology, including new process and fabrication technologies, and field-programmable analog arrays. Authors should submit 20 copies of their original work by September 27, 1996. Each submission should include an 100-250 words abstract, and is limited in length to 12 pages (including figures and tables, minimum point size 10). Notification of acceptance will be sent by November 18, 1996. A proceedings of accepted paper will be published by ACM. Authors must assign copyright of their accepted papers to ACM as a condition of publication. Final versions of accepted papers will be limited to seven pages, and must be submitted by December 6, 1996. All submissions should include the e.mail addresses of the authors, as all correspondence with authors will be done via e.mail. Submissions should be sent to: Prof. Jason Cong FPGA'97 Program Chair UCLA Computer Science Department 4711 Boelter Hall Los Angeles, CA 90095 Phone: (310) 206-2775, Fax: (310) 825-2273, E.mail: fpga97@cs.ucla.edu Organizing Committee: General Chair: Carl Ebeling, University of Washington Program Chair: Jason Cong, UCLA Publicity Chair: Scott Hauck, Northwestern University Finance Chair: Jonathan Rose, University of Toronto Local Chair: Pak Chan, UC Santa Cruz Program Committee: Michael Butts Quickturn Pak Chan UCSC Jason Cong UCLA Carl Ebeling U. Washington Masahiro Fujita Fujitsu Labs Scott Hauck Northwestern Univ. Dwight Hill Synopsys Brad Hutchings BYU Sinan Kaptanoglu Actel David Lewis U. Toronto Jonathan Rose U. Toronto Richard Rudell Synopsys Rob Rutenbar CMU Gabriele Saucier Imag Martine Schlag UCSC Tim Southgate Altera Steve Trimberger Xilinx Martin Wong UT Austin Nam-Sung Woo Lucent Technologies From pilz Mon Jun 17 14:23:19 1996 Subject: mailing list - web page To: codesign@ifi.unizh.ch Date: Mon, 17 Jun 1996 14:23:19 +0200 (MET DST) X-Mailer: ELM [version 2.4 PL11] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 8bit Content-Length: 408 Status: RO The mailing list codesign@ifi.unizh.ch has now a referring www page at http://www.ifi.unizh.ch/groups/richter/people/pilz/codesign.html Greetings Markus -- email: pilz@ifi.unizh.ch Markus Pilz, University of Zurich voice: +41-1-257 43 05 Department of Computer Science fax: +41-1-363 00 35 Winterthurerstr. 190, CH-8057 Zurich www: http://www.ifi.unizh.ch/staff/pilz.html From codesign-request@ifi.unizh.ch Mon Jun 17 14:23:39 1996 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch id <05524-0@josef.ifi.unizh.ch>; Mon, 17 Jun 1996 14:23:21 +0200 Subject: mailing list - web page To: codesign@ifi.unizh.ch Date: Mon, 17 Jun 1996 14:23:19 +0200 (MET DST) X-Mailer: ELM [version 2.4 PL11] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 8bit Content-Length: 407 From: Markus Pilz Sender: pilz@ifi.unizh.ch Message-ID: <"josef.ifi..045:17.05.96.12.23.38"@ifi.unizh.ch> Status: O The mailing list codesign@ifi.unizh.ch has now a referring www page at http://www.ifi.unizh.ch/groups/richter/people/pilz/codesign.html Greetings Markus -- email: pilz@ifi.unizh.ch Markus Pilz, University of Zurich voice: +41-1-257 43 05 Department of Computer Science fax: +41-1-363 00 35 Winterthurerstr. 190, CH-8057 Zurich www: http://www.ifi.unizh.ch/staff/pilz.html From codesign-request@ifi.unizh.ch Tue Jun 18 09:30:14 1996 Return-Path: Received: from imec.be by josef.ifi.unizh.ch with SMTP (PP) id <24358-0@josef.ifi.unizh.ch>; Tue, 18 Jun 1996 09:29:51 +0200 Received: from unimec.imec.be (unimec) by imec.be (5.65c/IDA-1.4.4-IMEC) id AA23783d; Tue, 18 Jun 1996 09:29:19 +0200 Message-Id: <9606180729.AA28514@unimec.imec.be> Original-Received: by unimec.imec.be Tue, 18 Jun 1996 09:29:15 +0200 PP-warning: Illegal Received field on preceding line X-Sender: deman@146.103.1.23 Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Date: Tue, 18 Jun 1996 09:31:56 +0100 To: codesign@ifi.unizh.ch From: deman@imec.be (Hugo De Man) Subject: call for papers ED&TC97 Status: RO ED&TC 97---ED&TC 97---ED&TC 97---ED&TC 97---ED&TC 97---ED&TC 97---ED&TC 97--- !!!!!!!ATTENTION !!!!! CALL FOR PAPERS CALL FOR PAPERS SUBMIT CONTRIBUTION ON or BEFORE SEPT, 6 1996 EUROPEAN DESIGN & TEST CONFERENCE 1997 EDAC ETC ASIC The European Conference European Exhibition on Design Automation Test Conference Paris, France, March 17-20, 1997 Sponsored by the European Design and Automation Association, by the IEEE Computer Society, and by the ACM SIG-DA ED&TC 97---ED&TC 97---ED&TC 97---ED&TC 97---ED&TC 97---ED&TC 97---ED&TC 97--- Dear Co-design Collegues, As programme chair of the European Design & Test Conference 1997 I would like to invite you to submit papers to the conference. I would like to see a strong component of hardware-software codesign in the conference. Please check the topics 2. and 7. in the call for papers. You can find the call on the web page at the bottom of this message. The annual EUROPEAN DESIGN & TEST CONFERENCE has established itself as a forum of excellence for presentations of outstanding industrial and academic technical work on all aspects of research and development of technology for the design and test of electronics-based products. In 1996 the Conference had 396 paper submissions from which international reviewers selected 107 high-quality papers for presentation at the Conference. This number of submissions has made the Conference the largest event within its scope. The conference was attended by over 500 attendees from all over the world. Quality of the technical program is the prime goal of the conference organisers. Having a paper accepted at ED&TC adds a quality label to your research and will give a widespread reputation to your work. In view of your excellent scientific reputation in the field of design technology I would like to invite you to submit one or more contributions to the conference. I also would like you to invite your coworkers or collegues to submit high quality papers to the conference. The deadline for paper submission is Sept, 6 1996. An international team of 100 reviewers will select the best papers for presentation at the conference and publication in the proceedings. The address for submission is : ED&TC 97 Conference Secretariat: For information: CEP Consultants Ltd. tel: +44 131 300 3300 43 Manor Place fax: +44 131 300 3400 Edinburgh, EH3 7EB, UK email: edtc@cep.u-net.com FOR MORE INFORMATION ON THE 13 CONFERENCE TOPICS AND THE LATEST NEWS ON ED&TC SEE WWW PAGE OF ED&TC 97 http://www.imec.be/edtc/97/ Best Regards, Hugo De Man Programme Chair ED&TC 97 deman@imec.be IMEC Kapeldreef 75 B3001 Leuven Belgium Phone 32 16 28 12 01 Fax 32 16 28 15 15 ED&TC 97---ED&TC 97---ED&TC 97---ED&TC 97---ED&TC 97---ED&TC 97---ED&TC 97--- From pilz Tue Jun 18 12:51:09 1996 Subject: mailing list archives To: codesign@ifi.unizh.ch Date: Tue, 18 Jun 1996 12:51:09 +0200 (MET DST) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Content-Length: 518 Status: RO Sorry for disturbing you again, but it is now possible to browse the mail distributed through the codesign mailing list. Check out http://www.ifi.unizh.ch/groups/richter/people/pilz/codesign.html click under 1996 postings: html and have fun... Cheers Markus -- email: pilz@ifi.unizh.ch Markus Pilz, University of Zurich voice: +41-1-257 43 05 Department of Computer Science fax: +41-1-363 00 35 Winterthurerstr. 190, CH-8057 Zurich www: http://www.ifi.unizh.ch/staff/pilz.html From codesign-request@ifi.unizh.ch Tue Jun 18 12:51:17 1996 Return-Path: Received: from ifi.unizh.ch by josef.ifi.unizh.ch id <02766-0@josef.ifi.unizh.ch>; Tue, 18 Jun 1996 12:51:11 +0200 Subject: mailing list archives To: codesign@ifi.unizh.ch Date: Tue, 18 Jun 1996 12:51:10 +0200 (MET DST) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Content-Length: 517 From: Markus Pilz Sender: pilz@ifi.unizh.ch Message-ID: <"josef.ifi..660:18.05.96.10.51.16"@ifi.unizh.ch> Status: O Sorry for disturbing you again, but it is now possible to browse the mail distributed through the codesign mailing list. Check out http://www.ifi.unizh.ch/groups/richter/people/pilz/codesign.html click under 1996 postings: html and have fun... Cheers Markus -- email: pilz@ifi.unizh.ch Markus Pilz, University of Zurich voice: +41-1-257 43 05 Department of Computer Science fax: +41-1-363 00 35 Winterthurerstr. 190, CH-8057 Zurich www: http://www.ifi.unizh.ch/staff/pilz.html From codesign-request@ifi.unizh.ch Fri Jun 21 00:06:47 1996 Return-Path: Received: from aglaia.Stanford.EDU by josef.ifi.unizh.ch with SMTP (PP) id <21748-0@josef.ifi.unizh.ch>; Fri, 21 Jun 1996 00:06:23 +0200 Received: by aglaia.Stanford.EDU (940816.SGI.8.6.9/inc-1.0) id OAA11232; Thu, 20 Jun 1996 14:57:15 -0700 From: mooney@aglaia.Stanford.EDU (Vincent John Mooney III) Message-Id: <199606202157.OAA11232@aglaia.Stanford.EDU> Subject: www page To: codesign@ifi.unizh.ch Date: Thu, 20 Jun 1996 14:57:15 -0800 (PDT) Cc: mooney@aglaia.Stanford.EDU (Vincent John Mooney III), nanni@galileo.stanford.edu X-Mailer: ELM [version 2.4 PL22] Content-Type: text Content-Length: 1688 Status: RO > Hello Vince, > > [...] > > Can you change the email address for me from > > mooney@leland.stanford.edu > > to > > mooney@aglaia.stanford.edu > > > done. > > [...] > > P.S. So how is everything going for you? Things here are > > very well -- I am busily working on some new ideas for > > codesign. You can check out my home page and research > > pages on the WWW for more info at > > http://akebono.stanford.edu/users/mooney/ > > > Nice to hear from you. Well, things are going pretty well here, > as binary translation and runtime code generation is very > popular in this days because of all those people talking about > implementing a fast Java virtual machine. However, there is > still pretty much to do before I will finish my Ph.D. thesis. > > Maybe you want to advertise your work / home page thru the mailing > list? I added your home page to my book marks, so I will visit you > every now and then :-). Sure thing. If anyone is interested in some of the research in progress in CAD at Stanford, feel free to look at my research home page: http://akebono.stanford.edu/users/mooney/research.html > Many greetings from Switzerland > > Markus > > -- > email: pilz@ifi.unizh.ch Markus Pilz, University of Zurich > voice: +41-1-257 43 05 Department of Computer Science > fax: +41-1-363 00 35 Winterthurerstr. 190, CH-8057 Zurich > www: http://www.ifi.unizh.ch/staff/pilz.html Many greetings! Vincent Mooney Computer Systems Laboratory Gates Computer Science Building 3A Room 326, Mail Code 9030 Stanford, CA 94305 Tel.: 415 725-3647 Fax: 415 725-6949 email: mooney@aglaia.stanford.edu WWW: http://akebono.stanford.edu/users/mooney From wolf@EE.Princeton.EDU Thu Jun 27 03:49:17 1996 Return-Path: Received: from ee.Princeton.EDU by josef.ifi.unizh.ch with SMTP (PP) id <16830-0@josef.ifi.unizh.ch>; Thu, 27 Jun 1996 03:49:16 +0200 Received: (from wolf@localhost) by ee.Princeton.EDU (8.6.10/8.6.10-1) id VAA29567 for codesign-request@ifi.unizh.ch; Wed, 26 Jun 1996 21:48:39 -0400 Date: Wed, 26 Jun 1996 21:48:39 -0400 From: Wayne Wolf Message-Id: <199606270148.VAA29567@ee.Princeton.EDU> To: codesign-request@ifi.unizh.ch Subject: Design Automation for Embedded Systems Status: RO Design Automation for Embedded Systems Volume 1, Number 3, June 1996 Jean Paul Calvez, A Co-Design Case Study with the MCSE Methodology A. P. Magalhaes, A Survey on Estimating the Timing Constraints of Hard Real-Time Systems Junji Suzuki and Sadayasu Ono, Entropy CODEC from Behavioral Descriptions Based LSI-CAD for Fully Programmable Image Coding Systems Alessandro Balboni, William Fornaciari, and Donatello Sciuto, Co-Synthesis and Co-Simulation of Control-Dominated Embedded Systems From codesign-request@ifi.unizh.ch Sun Jun 30 11:01:28 1996 Return-Path: Received: from FRCU.EUN.EG by josef.ifi.unizh.ch with SMTP (PP) id <24777-0@josef.ifi.unizh.ch>; Sun, 30 Jun 1996 11:01:19 +0200 Received: from FRCU.EUN.EG (SHALAN@SHAMS) by FRCU.EUN.EG (PMDF V4.2-11 #3805) id <01I6IOP6WJK00004UE@FRCU.EUN.EG>; Sun, 30 Jun 1996 11:57:15 O Date: Sun, 30 Jun 1996 11:57:15 +0000 (O) From: SHALAN@shams.eun.eg Subject: Codesign Questions To: codesign@ifi.unizh.ch Message-id: <01I6IOP6YOPU0004UE@FRCU.EUN.EG> X-VMS-To: FRCU::IN%"codesign@ifi.unizh.ch" MIME-version: 1.0 Content-type: TEXT/PLAIN; CHARSET=US-ASCII Content-transfer-encoding: 7BIT Status: RO Dear Sirs, I am an M.Sc. student and just start with the codesign. I am asked to choose a point to make a research. I collected many papers and get a good idea about the subject. I found that all of the done works are based on a ready made framworks or commercial develop developement enviroments which are not available for me. It is so kind of u if u guide me in this subject and guide me how to make a right and a good start with this HOT SUBJECT. Thanx Yours, Mohamad Shalan From codesign-request@ifi.unizh.ch Thu Aug 8 16:16:06 1996 Return-Path: Received: from david.siemens.de by josef.ifi.unizh.ch with SMTP (PP) id <11605-0@josef.ifi.unizh.ch>; Thu, 8 Aug 1996 16:09:36 +0200 Received: from ztivax.zfe.siemens.de (root@ztivax.siemens.de [146.254.1.2]) by david.siemens.de (8.7.5/8.7.3) with SMTP id QAA12885; Thu, 8 Aug 1996 16:02:28 +0200 (MDT) Received: from micky.zfe.siemens.de (micky) by ztivax.zfe.siemens.de with SMTP id AA03619 (5.67a/IDA-1.5); Thu, 8 Aug 1996 15:52:19 +0200 Received: (from buchen@localhost) by micky.zfe.siemens.de (8.6.12/8.6.12) id PAA00700; Thu, 8 Aug 1996 15:50:57 +0200 Date: Thu, 8 Aug 1996 15:50:57 +0200 From: "Dr. Klaus Buchenrieder" Message-Id: <199608081350.PAA00700@micky.zfe.siemens.de> To: jbecker@informatik.uni-kl.de, steger@fititk02.tu-graz.ac.at Subject: Re: List of HW/SW Codesign approaches Cc: codesign@ifi.unizh.ch, hartenst@rhrk.uni-kl.de Status: RO Sehr geehrter Herr Steger, versuchen Sie doch einmal http://ti-ibm06.informatik.uni-tuebingen.de/~buchen/ dieser Site ist im Aufbau und leider habe ich nur wenig Zeit diesen zu pflegen. --Klaus Buchenrieder From codesign-request@ifi.unizh.ch Thu Aug 8 12:08:29 1996 Return-Path: Received: from fitids01.tu-graz.ac.at by josef.ifi.unizh.ch with SMTP (PP) id <08241-0@josef.ifi.unizh.ch>; Thu, 8 Aug 1996 11:35:54 +0200 Received: by fitids01.tu-graz.ac.at (5.65/DEC-Ultrix/4.3) id AA02097; Thu, 8 Aug 1996 11:33:02 +0100 Received: by fititk02.tu-graz.ac.at.. (5.61/6.24) id AA01019; Thu, 8 Aug 96 11:29:44 +0100 Date: Thu, 8 Aug 1996 11:29:43 +0100 (MET) From: Christian Steger Subject: Re: List of HW/SW Codesign approaches To: Juergen Becker Cc: codesign@ifi.unizh.ch, hartenst@rhrk.uni-kl.de In-Reply-To: <199608070841.KAA20350@irz1.informatik.uni-kl.de> Message-Id: Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Status: RO Some people have problems with my postscript-file. Here the URL where you can get the list: www.id.dtu.dk/~jst/sum95/lectureplan.html Christian Steger ___________________________________________________________________ Dipl.-Ing. Dr. Christian Steger <<<<<<<<<<<<<<<<<< Institut fuer Technische Informatik | ___ ___ ___ | Technische Universitaet Graz, Austria | | | | | Steyrergasse 17/4 | | | | | A-8010 GRAZ | _|_ | _|_ | | | <<<<<<<<<<<<<<<<<< email: steger@iti.tu-graz.ac.at ___________________________________________________________________ From codesign-request@ifi.unizh.ch Wed Aug 7 10:50:25 1996 Return-Path: Received: from stepsun.uni-kl.de by josef.ifi.unizh.ch with SMTP (PP) id <23457-0@josef.ifi.unizh.ch>; Wed, 7 Aug 1996 10:50:18 +0200 Received: from uklirb.informatik.uni-kl.de by stepsun.uni-kl.de id aa04425; 7 Aug 96 10:49 MET DST Received: from irz1.informatik.uni-kl.de by uklirb.informatik.uni-kl.de id aa14906; 7 Aug 96 10:41 MET DST Received: from [131.246.76.132] by irz1.informatik.uni-kl.de (SMI-8.6/SMI-SVR4) id KAA20350; Wed, 7 Aug 1996 10:41:29 +0200 Date: Wed, 7 Aug 1996 10:41:29 +0200 Message-Id: <199608070841.KAA20350@irz1.informatik.uni-kl.de> From: Juergen Becker Reply-To: Juergen Becker To: codesign@ifi.unizh.ch Cc: hartenst@rhrk.uni-kl.de Subject: List of HW/SW Codesign approaches Status: RO Dear Codesigners, does anybody know, if there exists an (almost) complete list of academic codesign approaches (systems) available on the internet, probably with links to this places? Steve Guccione, University of Texas, (guccione@io.com) provides a similar list of FPGA-based custom computing machines with a short description of each machine and contact addresses. I look forward to hear from some of you, regards, Juergen ================================================================= Juergen Becker Universitaet Kaiserslautern Informatik (CS&E) phone: +49 (631) 205 2625, fax: ...2640 Postfach 3049 http://xputers.informatik.uni-kl.de D-67653 Kaiserslautern, Germany e-mail: jbecker@informatik.uni-kl.de .._/ _/ _/_/_/ _/ _/ _/_/_/ _/_/_/ _/_/_/ _/_/ _/ .._/_/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/_/_/ .._/ _/_/_/ _/ _/ _/ _/_/_/ _/_/_/ _/_/ _/_/_/_/_/ ._/_/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/_/ _/ _/_/_/ _/ _/ _/_/ _/ From codesign-request@ifi.unizh.ch Wed Aug 7 15:42:52 1996 Return-Path: Received: from fitids01.tu-graz.ac.at by josef.ifi.unizh.ch with SMTP (PP) id <27539-0@josef.ifi.unizh.ch>; Wed, 7 Aug 1996 15:31:00 +0200 Received: by fitids01.tu-graz.ac.at (5.65/DEC-Ultrix/4.3) id AA01623; Wed, 7 Aug 1996 15:06:20 +0100 Received: by fititk02.tu-graz.ac.at.. (5.61/6.24) id AA00586; Wed, 7 Aug 96 15:02:59 +0100 Date: Wed, 7 Aug 1996 15:02:48 +0100 (MET) From: Christian Steger Subject: Re: List of HW/SW Codesign approaches To: jnrg@it.dtu.dk Cc: jbecker@informatik.uni-kl.de, codesign@ifi.unizh.ch, hartenst@rhrk.uni-kl.de In-Reply-To: <9608070924.AA22029@anor.it.dtu.dk> Message-Id: Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Content-Transfer-Encoding: QUOTED-PRINTABLE Status: RO Find enlosed a postscript file with a co-synthese reading list from Wayne Wolf. Christian Steger ___________________________________________________________________ Dr. Christian Steger =20 =09=09=09=09 <<<<<<<<<<<<<<<<<< Institut fuer Technische Informatik | ___ ___ ___ | Technische Universitaet Graz, Austria | | | | | Steyrergasse 17/4 | | | | | A-8010 GRAZ | _|_ | _|_ | | | <<<<<<<<<<<<<<<<<< email: steger@iti.tu-graz.ac.at ___________________________________________________________________ LISTADMIN: [...] PostScript file deleted Get the file thru ftp directly from the author. codesign-request@ifi.unizh.ch From codesign-request@ifi.unizh.ch Thu Aug 22 12:10:03 1996 Return-Path: Received: from fitids01.tu-graz.ac.at by josef.ifi.unizh.ch with SMTP (PP) id <15424-0@josef.ifi.unizh.ch>; Thu, 22 Aug 1996 12:09:45 +0200 Received: by fitids01.tu-graz.ac.at (5.65/DEC-Ultrix/4.3) id AA02048; Thu, 22 Aug 1996 12:07:30 +0100 Received: by fititk02.tu-graz.ac.at.. (5.61/6.24) id AA00868; Thu, 22 Aug 96 12:02:32 +0100 Date: Thu, 22 Aug 1996 12:02:31 +0100 (MET) From: Christian Steger Subject: experience with Statemate/MAGNUM To: codesign@ifi.unizh.ch Message-Id: Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Status: RO Does anybody have experience with the tool Statemate MAGNUM from i-Logix used for HW/SW-codesign of complex systems? Christian ___________________________________________________________________ Dipl.-Ing. Dr. Christian Steger <<<<<<<<<<<<<<<<<< Institut fuer Technische Informatik | ___ ___ ___ | Technische Universitaet Graz, Austria | | | | | Steyrergasse 17/4 | | | | | A-8010 GRAZ | _|_ | _|_ | | | <<<<<<<<<<<<<<<<<< email: steger@iti.tu-graz.ac.at ___________________________________________________________________ From codesign-request@ifi.unizh.ch Sat Aug 31 05:02:51 1996 Return-Path: Received: from mailgate.Cadence.COM by josef.ifi.unizh.ch with SMTP (PP) id <20049-0@josef.ifi.unizh.ch>; Sat, 31 Aug 1996 05:02:44 +0200 Received: (from smap@localhost) by mailgate.Cadence.COM (8.6.8/8.6.8) id UAA16412; Fri, 30 Aug 1996 20:02:34 -0700 Received: from bsd10.cadence.com(158.140.90.10) by mailgate.cadence.com via smap (V1.0mjr) id sma841460550.016408; Fri Aug 30 20:02:31 1996 Received: from bsd10 (localhost [127.0.0.1]) by bsd10.Cadence.COM (8.6.8/8.6.8) with SMTP id UAA07624; Fri, 30 Aug 1996 20:02:25 -0700 Sender: luciano@cadence.com Message-ID: <3227AB41.5552@ic.eecs.berkeley.edu> Date: Fri, 30 Aug 1996 20:02:25 -0700 From: The POLIS team Organization: U.C. Berkeley X-Mailer: Mozilla 2.01 (X11; I; SunOS 5.4 sun4m) MIME-Version: 1.0 To: codesign@ifi.unizh.ch CC: polis@ic.eecs.berkeley.edu Subject: Announcement: public release of embedded system design software Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Status: RO Dear colleague, it is our pleasure to announce the public availability the POLIS co-design environment for control-dominated embedded systems. POLIS offers an integrated interactive environment for specification, co-simulation, formal verification, and synthesis of embedded systems implemented as a mix of hardware and software components. Most of the information about POLIS, including pointers to source and object code (for various CPUs and OSes) is available at our WEB site http://www-cad.eecs.berkeley.edu/Respep/Research/hsc/abstract.html The software is available under the usual copyright rules of the University of California (see also http://www-cad.eecs.berkeley.edu:80/copyright.html). If you are interested, but do not have WEB access, please contact us via e-mail at polis@ic.eecs.berkeley.edu. Best regards, the POLIS team (currently including Felice Balarin, Massimiliano Chiodo, Alberto Ferrari, Paolo Giusto, Harry Hsieh, Attila Jurecska, Marcello Lajolo, Luciano Lavagno, Claudio Passerone, Claudio Sansoe', Ellen Sentovich, Marco Sgroi, Kei Suzuki, Bassam Tabbara, Reinhard von Hanxleden, and Alberto Sangiovanni-Vincentelli) From codesign-request@ifi.unizh.ch Thu Sep 5 01:40:34 1996 Return-Path: Received: from june.cs.washington.edu by josef.ifi.unizh.ch with SMTP (PP) id <18120-0@josef.ifi.unizh.ch>; Thu, 5 Sep 1996 01:40:27 +0200 Return-Path: Received: (gaetano@localhost) by june.cs.washington.edu (8.7.5/7.2ju) id QAA06783; Wed, 4 Sep 1996 16:40:17 -0700 Date: Wed, 4 Sep 1996 16:40:17 -0700 From: gaetano@cs.washington.edu (Gaetano Borriello) Message-Id: <199609042340.QAA06783@june.cs.washington.edu> To: codesign@ifi.unizh.ch, isss-people@ics.uci.edu Subject: CODES'97 - call for participation Status: RO CALL FOR PARTICIPATION 5th International Workshop on Hardware/Software Co-Design Codes/CASHE '97 Braunschweig, Germany - 24-26 March 1997 SPONSORED BY: IEEE Computer Society, IEEE Circuits and Systems, ACM SIGDA & SIGSOFT, and IFIP WG 10.5 Electronic submission by: 16 December 1996 Notification by: 20 January 1997 THE CODES/CASHE WORKSHOP is the major international forum for the presentation and exchange of ideas in hardware/software co-design. The meeting structure promotes active discussion between all participants in an informal setting via short presentations of accepted papers combined with poster sessions. Group discussions are based on submitted proposals and/or the interests of the participants. AREAS OF INTEREST include, but are not limited to: 1) Computer-aided techniques for HW/SW co-design Specification languages and modeling techniques, design representations, simulation, validation, formal verification, emulation, prototyping, and synthesis. 2) Target architectures Architectures for embedded systems, HW/SW interfaces, communication methods, heterogeneous and embedded system design, case studies. 3) Software for co-design Development environments, real-time operating systems, process scheduling, concurrency management techniques, software synthesis approaches, portability of specifications, system integration and test. 4) System development process Concurrent engineering, design re-use, partitioning, design space exploration, estimation, design process management, device libraries and models. SUBMISSIONS for regular presentations are limited to 5 pages and may include an additional 15 pages of slides that will be included in the proceedings with 4 slides per page. In addition, submitters may also provide a URL for additional information related to their work. The web site for the meeting will list these URLs. Publication in the proceedings is voluntary. PROPOSALS for group discussions are limited to 2 pages highlighting the problem to be addressed, motivation, suggestions for issues to be addressed, and a potential discussion moderator or panel. ELECTRONIC SUBMISSION Submissions must be sent in an e-mail message based on the following template: --------------------------------------------------------------------- Subject: CODES97 submission Submission-type: {PAPER/GROUP} Related-URL: {URL to web page related to submission} Include-in-proceedings: {YES/NO} Number-of-pages: {total pages in appended postscript file} Keywords: {3 key words/phrases describing the work} {uuencoded postscript file} --------------------------------------------------------------------- to codes97@cs.washington.edu by 16 December 1996. The receipt of the message will be immediately acknowledged electronically. Notification of acceptance will be sent to the same e-mail address from which the submission was sent by 20 January 1997. WORKSHOP INFORMATION is available on the web at http://www.cs.washington.edu/homes/gaetano/codes.html or http://www.ida.ing.tu-bs.de/codes.html or send e-mail to codes97@cs.washington.edu. GENERAL CHAIR Prof. Rolf Ernst IDA TU Braunschweig Hans-sommer-Str. 66 D-38106 Braunschweig [Germany] Tel: +49 (531) 391-3730 Fax: +49 (531) 391-4587 Email: ernst@ida.ing.tu-bs.de PROGRAM CHAIR Prof. Gaetano Borriello Department of CS & E University of Washington Box 352350 Seattle, WA 98195-2350 [USA] Tel: +1 (206) 685-9432 Fax: +1 (206) 543-2969 Email: gaetano@cs.washington.edu PROGRAM COMMITTEE Brian Bailey, Mentor Graphics, USA; Joseph Buck, Synopsys, USA; Raul Camposano, Synopsys, USA; Giovanni De Micheli, Stanford Univ, USA; Martyn Edwards, Univ of Manchester (UMIST), UK; Thomas Fuhrman, General Motors, USA; Daniel Gajski, Univ of California at Irvine, USA; Rajesh Gupta, Univ of Illinois, USA; Reiner Hartenstein, Univ of Kaiserslautern, D; Roger Hughes, Abstract Hardware, UK; Ahmed Jerraya, Istitute National Polytechnique de Grenoble, F; Kurt Keutzer, Synopsys, USA; Sanjaya Kumar, Honeywell, USA; Philip Koopman, Carnegie-Mellon Univ, USA; Gregory Peterson, USAF Wright Labs, USA; Wolfgang Rosenstiel, Univ of Tubingen, D; Alberto Sangiovanni-Vincentelli, Univ of California at Berkeley, USA; Donatella Sciuto, Politecnico di Milano, I; Jorgen Staunstrup, Technical Univ of Denmark, DK; Richard Taylor, Hewlett-Packard Laboratories, UK; Don Thomas, Carnegie-Mellon Univ, USA; Frank Vahid, Univ of California at Riverside, USA; Wayne Wolf, Princeton Univ, USA; Hiroto Yasuura, Kyushu Univ, Japan. From codesign-request@ifi.unizh.ch Sat Sep 7 04:45:44 1996 Return-Path: Received: from ee.Princeton.EDU by josef.ifi.unizh.ch with SMTP (PP) id <26128-0@josef.ifi.unizh.ch>; Sat, 7 Sep 1996 04:45:37 +0200 Received: (from scdhar@localhost) by ee.Princeton.EDU (8.6.10/8.6.10-1) id WAA07696; Fri, 6 Sep 1996 22:45:27 -0400 Date: Fri, 6 Sep 1996 22:45:26 -0400 (EDT) From: "Sandeep C. Dhar" To: codesign@ifi.unizh.ch Subject: examples of codesign tasks which incorporate interrupts Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Status: RO Hello, I am looking for examples of moderately complex codesign tasks which incorporate interrupts and would welcome any help from this group. I would like to have the source code (preferably in C) of the main body of the program and of the interrupt service routines as well. If there are any input data streams please include their behaviour characteristics. The sample programs should have some real time constraints. I would like to investigate their expected performance and execution time to completion. I will be glad to provide any additional clarifications. All help will be appropriately acknowledged. Thanks, Sandeep Dhar, Dept. of Electrical Engg., Princeton University, Princeton, NJ 08544 scdhar@ee.princeton.edu From codesign-request@ifi.unizh.ch Wed Sep 25 12:07:37 1996 Return-Path: Received: from newsgw.mentorg.com by josef.ifi.unizh.ch with SMTP (PP) id <21408-0@josef.ifi.unizh.ch>; Wed, 25 Sep 1996 11:49:56 +0200 Received: from bvserver.ebv.mentorg.com by newsgw.mentorg.com (8.6.8.1/CF5.22R) id CAA12721; Wed, 25 Sep 1996 02:01:42 -0700 Received: from eurogw1.mentorg.com by bvserver.ebv.mentorg.com (8.6.8.1/CF5.26R) id KAA18504; Wed, 25 Sep 1996 10:59:24 +0200 Message-ID: Date: 25 Sep 1996 10:59:26 +0200 From: Herman Beke Subject: CAVE WORKSHOP DEC 96 To: codesign@ifi.unizh.ch X-Mailer: Mail*Link SMTP-QM 3.0.2 Content-Type: text Status: RO Subject: Time:10:48 AM OFFICE MEMO CAVE WORKSHOP DEC 96 Date:9/25/96 23rd CAVE WORKSHOP Turnhout BELGIUM December 2-4 1996 LAST CALL FOR CONTRIBUTIONS/PARTICIPATION ----------------------------------------------------------------------------------- CAVE BACKGROUND CAVE is an important annual event for researchers, developers and users of methods and tools for computer-aided design and design automation to discuss and present the state-of-the-art, foster new ideas and share valuable experience. CAVE Workshops operate as a non-profit organisation with the general objective to promote educational, scientific and technical cooperation in and advancement of the field of Design Technology in an international context, and particularly in the area of design and test of microelectronics chips and systems. A more specific objective is however the creation of a stimulating meeting place where design and test-technology specialists and designers can meet in person, get to know each other and spend time together on any relevant topic. Many people also use CAVE Workshops to meet and identify colleagues and suppliers, and not least to find partners for collaborative projects within the framework of ESPRIT, JESSI and other programs. Many projects started as late evening discussions in a CAVE Workshop. HISTORY CAVE was originally conceived in 1983 within the framework of ESPRIT and was supported by this Programme for almost a decade. Over the years CAVE Workshops have had a major impact on the European scene of design technology for VLSI systems design. Several initiatives and projects found their roots in the CAVE Workshops - just think of highly successful initiatives like EuroChip, the academic chip and tools support program, or ED&TC, the European Design & Test Conference and Exhibition. Important standardisation initiatives in design automation also trace back to CAVE initiatives. The European Design and Automation Association, the main sponsor of ED&TC, is also an outgrowth of the CAVE Workshops. SET UP OF A CAVE WORKSHOP As intensive interaction between participants is the main objective of the Workshop, its topic areas and the format for presentations and discussions are designed to act as much as possible as enablers for that function. There is usually no unscheduled time during the Workshop. Over the years the following aspects of the format have established themselves as being quite effective, as well as being highly valued by the participants: Four technical subjects are discussed in half-day sessions in with both talks and posters are presented. The format is set up to give maximum time for information exchange and interaction. A fifth session is a Working Session in which active participation of all attendants is scheduled, with plenary reporting to inform each other about the activities of the individual groups. A break-out meeting in the afternoon of the second day and a special dinner that evening assure that sufficient time is available for the essential social contacts during the Workshop. PARTICIPATION Participation to a CAVE Workshop is restricted to about 70 people. Each of the participants is expected to contribute actively to the programme of the Workshop. The most common way to do this is to offer a talk or poster in one of the topic areas that were chosen for a particular CAVE Workshop. See below for the topics of the 23rd CAVE Workshop and how to offer your contribution. Participation to CAVE Workshops was initially restricted to design technology users and professionals from Europe. The increasing importance of global developments, also in design technology, have led the Executive Committee to opening up the Workshop to a limited number of interested or invited professionals from outside Europe. The majority of participants is still expected to come from Europe. TOPICS OF THE 23rd CAVE WORKSHOP The workshop will focus on the topics indicated below. Short descriptions of the objectives of each session can be found on the CAVE Home Page (address see below). It may be worthwhile to contact a topic-coordinator early if you know of an interesting contribution to the Session. Session 1: DSP Design Methods and Tools ----------------------------------------------------------------- Objectives of the Session: Major challenges in DSP System design for VLSI implementation originate from trends in applications and in technologies. They influence all phases in the design flow: specification, simulation, architecture and layout synthesis, verification and testing. New requirements in applications relate mostly to communications and multimedia. This brings up many design questions related to e.g. real-time operating systems, the value of emulation, efficient high-speed architecture synthesis, etc. Besides, they present new possibilities for design trade-offs by novel requirements like the need to incorporate general purpose and application-specific cores or like the need for low power solutions for portable applications. Tools for support of the above problems are mainly in an early state of development. Nevertheless this Session aims to overview the state of the art in the broad field of Design Methods and Tools for DSP System-on-a-Chip Design. Topic Co-ordinator: Ludwig D.J. Eggermont Tel: +31 40 278 49 61 Fax: +31 40 278 64 22 email: eggermont@cpdc.philips.nl Session 2: Design of Systems-on-a-Chip ----------------------------------------------------------------- Objectives of the Session: Actual VLSI circuits can provide capabilities to design Systems-on-a-Chip formerly achieved with Wafer Scale Integration. This new microelectronic area is under a fast development in response to the industrial requirements for high performance systems subject to constraints such as size, weight, power, cost or working environments. This session aims to cover all the aspects related to the CAD tools used to integrate microelectronic system modules and to perform trade-off studies. Topics for oral or poster presentations include, but are not limited to, CAD for design of large area monolithic ICs and MCM based systems, mixed analog and digital systems, tools to perform 2-D and 3-D simulation, placement and routing, power estimation, clock and signal distribution, cost modeling, thermal analysis, yield prediction, system test, fault location and system repair. Topic Co-ordinator: Carlos Beltran Almeida Tel: +351 3 310 02 40 Fax: +351 1 52 58 43 email: cfb@ dalton.inesc.pt Session 3: Challenges of Mixed-Signal Design ----------------------------------------------------------------- Objectives of the Session: For many European companies, the mixed-signal area presents a vital area for their system design and test. Tools for this domain are still lagging significantly compared to what is available in the digital field. The session will focus on new methodologies for designing and testing mixed-signal chip systems. For mixed-signal design this includes: analogue synthesis, mixed-signal simulation, analogue HDL, mixed-signal floorplanning as well as route and placement, and the mixed-signal test topics typically include transfer of results from design-to-test, mixed-signal verification, how can the chip designer take more responsibility of the mixed-signal chip test and verification? etc. The session will include 5 presentations as well as 1 hour poster presentations, where more people will have the opportunity to present interesting results and/or views on the challenges of mixed-signal. Topic Co-ordinator: Birger Schneider Tel: +45 45762100 Fax: +45 45762200 email: bsc@ microlex.dk Session 4: Microsystems: CAD and Experiences ----------------------------------------------------------------- Objectives of the Session: Microsystem technology, the integration of chemical, mechanical and other sensors and actuators together with electronic components onto silicon systems, is of rapidly growing importance. The most important applications of microsystems are expected to be in information technology industries, the automotive industry, environmental protection, medical technology, production engineering. In order to save costs the development of microsystems is focused on exploiting the technology already available in the IC business. The design of such systems is complicated by the multi-disciplinary nature of the problem. There are mature design tools in many of the individual areas, particularly in the IC and mechanical fields, but little which covers the whole problem. From the complexity point of view the design and construction of microsystems is comparable to that of VLSI ICs. A uniform design environment is very important for reducing time to market. That makes it easier to exploit designs developed for and tested in other widely used applications. Oral and poster presentations are sought on all aspects of CAD for microsystems, including CAD tools, modelling, design methodologies and interesting examples of the use of microsystem CAD. Topic Co-ordinators: Karl-Heinz Diener Tel: +49 351 4640 717 Fax: +49 351 4640 703 email: diener@eas.iis.fhg.de Colin Lyden Tel: +353 21 904 329 Fax: +353 21 270 271 email: lyden@nmrc.ucc.ie Working Session 5: CAVE predictions for 2002 ----------------------------------------------------------------- Objectives of the Session: The workshop will be divided into 5 groups, each brainstorming where Design Technology and CAD will be in 5 year's time. A Plenary Session will then be held to review, combine and vote on the key predictions. A brief look back at the predictions we made in 1986 and 1991 will provide a stimulatiung starting point. Persons wishing to lead discussions or present posters giving strong predictions are asked to contact Gordon Adshead as soon as possible. Topic Co-ordinator: Gordon Adshead Tel: +44 1625 549 770 Fax: +44 1625 549 770 email: gordon.adshead@mdt.u-net.com LOCATION The Workshop will be held in Turnhout, Belgium. The local organiser is the DSP Valley organisation, represented by Georges Gielen from KU Leuven and Herman Beke from EDC/Mentor Graphics, Leuven. Address see below. FEE The Workshop fee is 525 ECU p.p. (340 ECU for non-participating accompanying persons). This fee includes everything: food, drinks with meals, morning coffee & afternoon tea, lodging, special dinner on Tuesday, photograph, transport and entry fee for break-out and transport from and to Brussels Airport resp. on Dec. 1 @ 19.00 hours and Dec. 4 @ 14.30 hours. DEADLINES AND KEY DATES Submission of Abstracts October 4, 1996 Notification of Acceptance November 4, 1996 Arrival for the Workshop December 1, 1996 Workshop December 2-4,1996 SUBMISSION OF ABSTRACTS If you are interested to contribute a talk or poster to one of the sessions above, send an extended abstract (500 words) to the Local Organiser, accompanied of the following information and signature: Name: Affiliation: Address: Tel.: Fax: E-mail: I like to contribute to the 23rd CAVE Workshop a ________ (fill in talk or poster) My contribution fits in Session ___ (fill in 1, 2, 3, 4 or 5) The title of my contribution is: When my contribution is accepted I will pay the registration fee before November 11, 1996 Signature: Date: Place: Suggestion: fill in, print and fax this page (because we need your signature) and your Extended Abstract to the Local Organiser: Herman Beke Abdijstraat 34 B 3001 Leuven Belgium Tel: +32 16 391 411 Fax: +32 16 406 076 email: herman_beke@mentorg.com CAVE HOME PAGE Short descriptions of the objectives of each session are available on the Home Page. For the most recent information on the 23rd CAVE, and for some historical information and photographs, see the WWW Home Page at URL= http://www.IAEhv.nl/users/ldje/cave.html From codesign-request@ifi.unizh.ch Thu Oct 17 16:49:45 1996 Return-Path: Received: from vttoulu.tko.vtt.fi by josef.ifi.unizh.ch with SMTP (PP) id <28300-0@josef.ifi.unizh.ch>; Thu, 17 Oct 1996 16:49:38 +0100 Received: from raisun3 (raisun3 [130.188.91.54]) by vttoulu.tko.vtt.fi (8.7.1/8.7.1) with SMTP id RAA15648; Thu, 17 Oct 1996 17:49:28 +0300 Received: by raisun3 (4.1/SMI-4.1) id AA05022; Thu, 17 Oct 96 17:49:26 +0300 Date: Thu, 17 Oct 96 17:49:26 +0300 From: ppu@raisun3.tko.vtt.fi (Petri Pulli) Message-Id: <9610171449.AA05022@raisun3> To: codesign@ifi.unizh.ch Subject: ?Java Virtual Machine HW Implementations Cc: marko.salmela@vtt.fi Status: RO Dear Co-design experts, My PhD student Marko Salmela is collecting information on state-of-the art of Java language run-time hardware support. I would appreciate if you could give him pointers to any of you know. Enclosed a detailed profile of information he is seeking. Yours Petri Pulli Research professor VTT Electronics and University of Oulu Finland ----- Begin Included Message ----- >From marko.salmela@vtt.fi Thu Oct 17 16:38:51 1996 Hi, I would like to receive any information about or pointers to the following topics: 1) Java chips, 2) Java accelator ICs, 3) synthesizable VHDL models of the Java VM, and 4) products based on Java chips, accelerators or JavaOS. I will prepate a compilation of the information I receive, and send it to this mailing-list. ------------------------------------------------------------------ Marko Salmela Email: Marko.Salmela@vtt.fi VTT Electronics tel: +358 8 551 2356 Kaitovayla 1, Box 1100 Fax: +358 8 551 2320 SF-90571 Oulu WWW: http://www.ele.vtt.fi/ ------------------------------------------------------------------ ----- End Included Message ----- From codesign-request@ifi.unizh.ch Fri Oct 18 15:21:07 1996 Return-Path: Received: from eux100.sgp.st.com by josef.ifi.unizh.ch with SMTP (PP) id <18794-0@josef.ifi.unizh.ch>; Fri, 18 Oct 1996 15:20:38 +0100 Received: from by eux100 with SMTP (1.39.111.2/16.2) id AA060344598; Fri, 18 Oct 1996 15:16:38 +0200 From: STEFANO.PASSONI@st.com X-Openmail-Hops: 2 Date: Fri, 18 Oct 96 15:15:51 +0200 Message-Id: Subject: Re: Java Virtual Machine HW Implementations Mime-Version: 1.0 To: ppu@raisun3.tko.vtt.fi Cc: codesign@ifi.unizh.ch, marko.salmela@vtt.fi Content-Type: text/plain; charset=US-ASCII; name="?Java" Content-Transfer-Encoding: 7bit Status: RO Dear Alls, My name is Stefano Passoni, I work in CASA group (Corporate Advanced System Architectures) of SGS-THOMSON MICROELECTRONICS of Agrate (ITALY). Our group is in charge to study, define and simulate advanced architectures for information technology and multimedia applications. My previous experience is derived from Telecom projects (e.g. hardware design of SDH/ATM gateways or ATM switches...) while current our main activities (information technology segment) are focused in specification and realisation of a basic HW/SW architectures in order to use the Java (SUN object-oriented language) technology within Embedded Systems and as a base for the upcoming Network Computer market and as a base-language for system layer of MPEG. The hardware activity is oriented to look for the best CPU architecture configuration to support the Java instruction set while the software is mainly concentrated in porting of JAVA environment (e.g. run-time, interpreter...) on our CPUs. About Java chips : Sun Micro is developing PICOJAVA that is essentially a byte-code core processor Picojava has been licensed to some companies (SAMSUNG, NEC, MITSUBISHI) for their embedded applications. There are some others attractive stack-based architectures that could be adopt to run Java (consult microprocessor report April 15 : ShBoom CPU). I don't believe that there are synthesizable VHDL models of Java VM (anyway if there are I'm interested). We are also trying to implement a hardware Java interpreter (accelerator) for x86 platform. Hoping to have carried out positive items to discussion, I would like to know that if there is somebody interested to set-up a proposal(for ACTS/ESPRIT projects) to develop an hardware accelerator for Java (byte-code engine ?, specific cells ?). Best regards stefano Passoni ******************************************************************* Stefano Passoni tel. +39 39 6036154 SGS-THOMSON Microelectronics fax +39 39 6036129 C.A.S.A. Group e-mail stefano.passoni@st.com Information Technology system engineer via C. Olivetti, 2 20041 Agrate Brianza (MI) ITALY ******************************************************************* From codesign-request@ifi.unizh.ch Mon Nov 4 21:00:40 1996 Return-Path: Received: from june.cs.washington.edu by josef.ifi.unizh.ch with SMTP (PP) id <29828-0@josef.ifi.unizh.ch>; Mon, 4 Nov 1996 21:00:32 +0100 Return-Path: Received: (gaetano@localhost) by june.cs.washington.edu (8.7.6/7.2ju) id LAA23595; Mon, 4 Nov 1996 11:59:35 -0800 Date: Mon, 4 Nov 1996 11:59:35 -0800 From: gaetano@cs.washington.edu (Gaetano Borriello) Message-Id: <199611041959.LAA23595@june.cs.washington.edu> To: ahmed.jerraya@imag.fr, alberto@ic.EECS.Berkeley.EDU, brian_bailey@mentorg.com, codesign@ifi.unizh.ch, codesign@vhdl.org, ernst@ida.ing.tu-bs.de, fuhrman@gmr.com, gaetano@cs.washington.edu, gajski@uci.edu, gdp@el.wpafb.af.mil, hartenst@rhrk.uni-kl.de, isss-people@ics.uci.edu, jst@it.dtu.dk, keutzer@synopsys.com, koopman@cs.cmu.edu, mde@ap.co.umist.ac.uk, nanni@pegasus.stanford.edu, raul@synopsys.com, rgupta@cs.uiuc.edu, roger@ahl.co.uk, rosenstiel@peanuts.informatik.uni-tuebingen.de, rwt@hpl.hp.co.uk, sciuto@elet.polimi.it, skumar@src.honeywell.com, thomas@ece.cmu.edu, vahid@cs.ucr.edu, wolf@princeton.edu, yasuura@is.kyushu-u.ac.jp Subject: CODES/CASHE'97 - CFP - 16 Dec 96 Status: RO CALL FOR PARTICIPATION 5th International Workshop on Hardware/Software Co-Design Codes/CASHE '97 Braunschweig, Germany - 24-26 March 1997 SPONSORED BY: IEEE Computer Society, IEEE Circuits and Systems, ACM SIGDA & SIGSOFT, and IFIP WG 10.5 Electronic submission by: 16 December 1996 Notification by: 20 January 1997 THE CODES/CASHE WORKSHOP is the major international forum for the presentation and exchange of ideas in hardware/software co-design. The meeting structure promotes active discussion between all participants in an informal setting via short presentations of accepted papers combined with poster sessions. Group discussions are based on submitted proposals and/or the interests of the participants. AREAS OF INTEREST include, but are not limited to: 1) Computer-aided techniques for HW/SW co-design Specification languages and modeling techniques, design representations, simulation, validation, formal verification, emulation, prototyping, and synthesis. 2) Target architectures Architectures for embedded systems, HW/SW interfaces, communication methods, heterogeneous and embedded system design, case studies. 3) Software for co-design Development environments, real-time operating systems, process scheduling, concurrency management techniques, software synthesis approaches, portability of specifications, system integration and test. 4) System development process Concurrent engineering, design re-use, partitioning, design space exploration, estimation, design process management, device libraries and models. SUBMISSIONS for regular presentations are limited to 5 pages and may include an additional 15 pages of slides that will be included in the proceedings with 4 slides per page. In addition, submitters may also provide a URL for additional information related to their work. The web site for the meeting will list these URLs. Publication in the proceedings is voluntary. PROPOSALS for group discussions are limited to 2 pages highlighting the problem to be addressed, motivation, suggestions for issues to be addressed, and a potential discussion moderator or panel. ELECTRONIC SUBMISSION Submissions must be sent in an e-mail message based on the following template: --------------------------------------------------------------------- Subject: CODES97 submission Submission-type: {PAPER/GROUP} Related-URL: {URL to web page related to submission} Include-in-proceedings: {YES/NO} Number-of-pages: {total pages in appended postscript file} Keywords: {3 key words/phrases describing the work} {uuencoded postscript file} --------------------------------------------------------------------- to codes97@cs.washington.edu by 16 December 1996. The receipt of the message will be immediately acknowledged electronically. Notification of acceptance will be sent to the same e-mail address from which the submission was sent by 20 January 1997. WORKSHOP INFORMATION is available on the web at http://www.cs.washington.edu/homes/gaetano/codes.html or http://www.ida.ing.tu-bs.de/codes.html or send e-mail to codes97@cs.washington.edu. GENERAL CHAIR Prof. Rolf Ernst IDA TU Braunschweig Hans-sommer-Str. 66 D-38106 Braunschweig [Germany] Tel: +49 (531) 391-3730 Fax: +49 (531) 391-4587 Email: ernst@ida.ing.tu-bs.de PROGRAM CHAIR Prof. Gaetano Borriello Department of CS & E University of Washington Box 352350 Seattle, WA 98195-2350 [USA] Tel: +1 (206) 685-9432 Fax: +1 (206) 543-2969 Email: gaetano@cs.washington.edu PROGRAM COMMITTEE Brian Bailey, Mentor Graphics, USA; Joseph Buck, Synopsys, USA; Raul Camposano, Synopsys, USA; Giovanni De Micheli, Stanford Univ, USA; Martyn Edwards, Univ of Manchester (UMIST), UK; Thomas Fuhrman, General Motors, USA; Daniel Gajski, Univ of California at Irvine, USA; Rajesh Gupta, Univ of Illinois, USA; Reiner Hartenstein, Univ of Kaiserslautern, D; Roger Hughes, Abstract Hardware, UK; Ahmed Jerraya, Istitute National Polytechnique de Grenoble, F; Kurt Keutzer, Synopsys, USA; Sanjaya Kumar, Honeywell, USA; Philip Koopman, Carnegie-Mellon Univ, USA; Gregory Peterson, USAF Wright Labs, USA; Wolfgang Rosenstiel, Univ of Tubingen, D; Alberto Sangiovanni-Vincentelli, Univ of California at Berkeley, USA; Donatella Sciuto, Politecnico di Milano, I; Jorgen Staunstrup, Technical Univ of Denmark, DK; Richard Taylor, Hewlett-Packard Laboratories, UK; Don Thomas, Carnegie-Mellon Univ, USA; Frank Vahid, Univ of California at Riverside, USA; Wayne Wolf, Princeton Univ, USA; Hiroto Yasuura, Kyushu Univ, Japan. From codesign-request@ifi.unizh.ch Tue Nov 5 16:12:35 1996 Return-Path: Received: from green.eb.ele.tue.nl by josef.ifi.unizh.ch with SMTP (PP) id <18782-0@josef.ifi.unizh.ch>; Tue, 5 Nov 1996 14:46:26 +0100 Received: from pa20 (pa20.eb.ele.tue.nl [131.155.42.20]) by green.eb.ele.tue.nl (8.7.5/1.63) pid 21783 id OAA21783; Tue, 5 Nov 1996 14:42:45 +0100 (MET) Message-Id: <199611051342.OAA21783@green.eb.ele.tue.nl> X-Sender: lech@green.eb.ele.tue.nl X-Mailer: Windows Eudora Version 1.4.3b4 Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Date: Tue, 05 Nov 1996 15:44:11 +0100 To: ahmed.jerraya@imag.fr, alberto@ic.eecs.berkeley.edu, brian_bailey@mentorg.com, codesign@ifi.unizh.ch, codesign@vhdl.org, ernst@ida.ing.tu-bs.de, fuhrman@gmr.com, gaetano@cs.washington.edu, gajski@UCI.EDU, gdp@el.wpafb.af.mil, hartenst@rhrk.uni-kl.de, isss-people@ics.UCI.EDU, jst@it.dtu.dk, keutzer@synopsys.com, koopman@cs.cmu.edu, mde@ap.co.umist.ac.uk, nanni@pegasus.stanford.edu, raul@synopsys.com, rgupta@cs.uiuc.edu, roger@ahl.co.uk, rosenstiel@peanuts.informatik.uni-tuebingen.de, rwt@hpl.hp.co.uk, sciuto@elet.polimi.it, skumar@src.honeywell.com, thomas@ece.cmu.edu, vahid@cs.ucr.edu, wolf@princeton.edu, yasuura@is.kyushu-u.ac.jp From: lech@eb.ele.tue.nl (Lech Jozwiak) Subject: CODES/CASHE'97 - CFP - 16 Dec 96 Status: RO Hallo Andy, ik denk dat het zinvol zou zijn, om een vernieuwde versie van de artiekel van de niet gebeurde Workshop in Zakopane naar deze Workshop stuuren. Groetjes, Lech CALL FOR PARTICIPATION 5th International Workshop on Hardware/Software Co-Design Codes/CASHE '97 Braunschweig, Germany - 24-26 March 1997 SPONSORED BY: IEEE Computer Society, IEEE Circuits and Systems, ACM SIGDA & SIGSOFT, and IFIP WG 10.5 Electronic submission by: 16 December 1996 Notification by: 20 January 1997 THE CODES/CASHE WORKSHOP is the major international forum for the presentation and exchange of ideas in hardware/software co-design. The meeting structure promotes active discussion between all participants in an informal setting via short presentations of accepted papers combined with poster sessions. Group discussions are based on submitted proposals and/or the interests of the participants. AREAS OF INTEREST include, but are not limited to: 1) Computer-aided techniques for HW/SW co-design Specification languages and modeling techniques, design representations, simulation, validation, formal verification, emulation, prototyping, and synthesis. 2) Target architectures Architectures for embedded systems, HW/SW interfaces, communication methods, heterogeneous and embedded system design, case studies. 3) Software for co-design Development environments, real-time operating systems, process scheduling, concurrency management techniques, software synthesis approaches, portability of specifications, system integration and test. 4) System development process Concurrent engineering, design re-use, partitioning, design space exploration, estimation, design process management, device libraries and models. SUBMISSIONS for regular presentations are limited to 5 pages and may include an additional 15 pages of slides that will be included in the proceedings with 4 slides per page. In addition, submitters may also provide a URL for additional information related to their work. The web site for the meeting will list these URLs. Publication in the proceedings is voluntary. PROPOSALS for group discussions are limited to 2 pages highlighting the problem to be addressed, motivation, suggestions for issues to be addressed, and a potential discussion moderator or panel. ELECTRONIC SUBMISSION Submissions must be sent in an e-mail message based on the following template: --------------------------------------------------------------------- Subject: CODES97 submission Submission-type: {PAPER/GROUP} Related-URL: {URL to web page related to submission} Include-in-proceedings: {YES/NO} Number-of-pages: {total pages in appended postscript file} Keywords: {3 key words/phrases describing the work} {uuencoded postscript file} --------------------------------------------------------------------- to codes97@cs.washington.edu by 16 December 1996. The receipt of the message will be immediately acknowledged electronically. Notification of acceptance will be sent to the same e-mail address from which the submission was sent by 20 January 1997. WORKSHOP INFORMATION is available on the web at http://www.cs.washington.edu/homes/gaetano/codes.html or http://www.ida.ing.tu-bs.de/codes.html or send e-mail to codes97@cs.washington.edu. GENERAL CHAIR Prof. Rolf Ernst IDA TU Braunschweig Hans-sommer-Str. 66 D-38106 Braunschweig [Germany] Tel: +49 (531) 391-3730 Fax: +49 (531) 391-4587 Email: ernst@ida.ing.tu-bs.de PROGRAM CHAIR Prof. Gaetano Borriello Department of CS & E University of Washington Box 352350 Seattle, WA 98195-2350 [USA] Tel: +1 (206) 685-9432 Fax: +1 (206) 543-2969 Email: gaetano@cs.washington.edu PROGRAM COMMITTEE Brian Bailey, Mentor Graphics, USA; Joseph Buck, Synopsys, USA; Raul Camposano, Synopsys, USA; Giovanni De Micheli, Stanford Univ, USA; Martyn Edwards, Univ of Manchester (UMIST), UK; Thomas Fuhrman, General Motors, USA; Daniel Gajski, Univ of California at Irvine, USA; Rajesh Gupta, Univ of Illinois, USA; Reiner Hartenstein, Univ of Kaiserslautern, D; Roger Hughes, Abstract Hardware, UK; Ahmed Jerraya, Istitute National Polytechnique de Grenoble, F; Kurt Keutzer, Synopsys, USA; Sanjaya Kumar, Honeywell, USA; Philip Koopman, Carnegie-Mellon Univ, USA; Gregory Peterson, USAF Wright Labs, USA; Wolfgang Rosenstiel, Univ of Tubingen, D; Alberto Sangiovanni-Vincentelli, Univ of California at Berkeley, USA; Donatella Sciuto, Politecnico di Milano, I; Jorgen Staunstrup, Technical Univ of Denmark, DK; Richard Taylor, Hewlett-Packard Laboratories, UK; Don Thomas, Carnegie-Mellon Univ, USA; Frank Vahid, Univ of California at Riverside, USA; Wayne Wolf, Princeton Univ, USA; Hiroto Yasuura, Kyushu Univ, Japan. From codesign-request@ifi.unizh.ch Mon Nov 18 10:44:48 1996 Return-Path: Received: from imag.imag.fr by josef.ifi.unizh.ch with SMTP (PP) id <03064-0@josef.ifi.unizh.ch>; Mon, 18 Nov 1996 10:44:39 +0100 Received: from verdon.imag.fr (verdon.imag.fr [147.171.129.20]) by imag.imag.fr (8.8.1/8.6.9) with ESMTP id KAA12695; Mon, 18 Nov 1996 10:44:29 +0100 (MET) Received: (from jerraya@localhost) by verdon.imag.fr (8.6.11/8.6.9) id KAA26524; Mon, 18 Nov 1996 10:43:50 +0100 X-Mailer: Mail User's Shell (7.2.5 10/14/92) Resent-To: hlsw-people@ics.UCI.EDU, codesign@ifi.unizh.ch Received: (from jerraya@localhost) by verdon.imag.fr (8.6.11/8.6.9) id PAA15283 for jerraya; Sun, 17 Nov 1996 15:59:06 +0100 Resent-Date: Sun, 17 Nov 1996 15:59:06 +0100 Resent-From: Ahmed Amine Jerraya Resent-Message-Id: <199611171459.PAA15283@verdon.imag.fr> X-Mailer: Mail User's Shell (7.2.5 10/14/92) Resent-To: Ahmed-Amine.Jerraya@imag.fr Received: from imag.imag.fr (imag.imag.fr [129.88.30.1]) by verdon.imag.fr (8.6.11/8.6.9) with ESMTP id XAA08589 for ; Thu, 7 Nov 1996 23:54:46 +0100 Received: from ece.arizona.edu (ece1.ece.arizona.edu [128.196.28.166]) by imag.imag.fr (8.8.1/8.6.9) with SMTP id XAA19036 for ; Thu, 7 Nov 1996 23:55:21 +0100 (MET) Received: from desert.ece.arizona.edu (desert-gw.ece.arizona.edu) by ece.arizona.edu (5.0/SMI-SVR4) id AA06108; Thu, 7 Nov 1996 15:54:48 -0700 Received: from mojave.ece.arizona.edu by desert.ece.arizona.edu (SMI-8.6/SMI-SVR4) id PAA12656; Thu, 7 Nov 1996 15:49:40 -0700 Received: by mojave.ece.arizona.edu (SMI-8.6/SMI-SVR4) id PAA29203; Thu, 7 Nov 1996 15:48:09 -0700 Date: Thu, 7 Nov 1996 15:48:09 -0700 From: jdc@desert-gw.ece.arizona.edu (Jo Dale Carothers) Message-Id: <199611072248.PAA29203@mojave.ece.arizona.edu> To: Ahmed-Amine.Jerraya@imag.fr Subject: IPCCC'97 CFP Status: RO This is the text version of the Call for Papers for RSP '97. Please distribute this to anyone that you feel would be interested. A postscript version is also available on the web page referenced below. Thank you for your help. Best regards, Jo Dale Carothers **************************************************************** * * * 8th IEEE International Workshop on Rapid Systems Prototyping * * * **************************************************************** June 24-26, 1997 The Carolina Inn-Chapel Hill, North Carolina CALL FOR PAPERS Reducing Systems Introduction to Market The IEEE International Workshop on Rapid System Prototyping presents and explores the trends in rapid prototyping of Computer Based Systems including, but not limited to, communications, information, manufacturing and transportation systems. The eighth annual worshop will focus on improved approaches to resolving prototyping issues and problems raised by imcomplete specifications, increased system complexity and reduced time to market requirements for a multitude of products. The workshop will include a keynote presentation and formal paper sessions with a wide range of system prototyping topics, which include, but are not limited to the following: * System Emulation * Virtual Prototyping * Hardware-Software Codesign * Tools for hardware prototyping * Tools for software prototyping * The role of FPGAs in system prototyping * Prototyping case studies * Very large scale system engineering * Harware/Software tradoffs * System verification/validation * Prototype to product transition The program committee invites authors to submit five copies of an extended summary or a full paper (preferred) presenting original and unpublished work. Clearly describe the nature of the work, explain its significance, highlight its novel features, and state its current status. Authors of selected papers will be requested to prepare a manuscript for the workshop proceedings. * Papers due: January 30, 1997 * Notification of Acceptance: February 25, 1997 * Final Camera Ready Manuscript due: March 30, 1997 Submit all papers to: For General Information, Contact: Jo Dale Carothers Nick Kanopoulos Dept. of ECE Data Communications Technologies University of Arizona 2200 Gateway Centre Blvd. Tucson, AZ 85721 Suite 201 USA Morrisville, NC 27560 (520) 621-8733 (919) 462-6567 (520) 621-8076 FAX (919) 462-0300 FAX carothers@ece.arizona.edu nick@dct.rti.org Additonal information on the RSP Worshop is available via WWW at http://www-masi.ibp.fr/rsp General Chair N. Kanopoulos - DCT Program Chair J.D. Carothers - Univ. of Arizona Publicity Chair N. Ullah - Motorola Program Committee A.A. Jerraya - INPG/TIMA T. Antonakopoulos - Univ. of Patras J-Y. Brunel - Philips V. Calandra - Zycad B. Candaele - Thomson-CSF B. Courtois - INPG/TIMA W. Debany - Rome Laboratory A. Dollas - Technical Univ. of Crete M. Engels - IMEC/VSDM M. Glesner - Technische Hoschschule Darmstadt T. Hoshino - NTT P. Hulina - Penn. State Univ. F. Kordon - Univ. Paris VI, Lab MASI R. Lauvereins - Katholieke Univ. Leuven C. Tong - Sunrise S. Winkler - NIST N. Zervos - Lucent V. Olive - France Telecom H.N. Nguyen - Bull Y. Tanurhan - FZI V. Berman - Cadence M. Ade - Katholieke Univ. Leuven/ESAT G. Aifantopoulou - TRUTh From codesign-request@ifi.unizh.ch Mon Nov 18 21:01:09 1996 Return-Path: Received: from cma.cma.fr by josef.ifi.unizh.ch with SMTP (PP) id <21733-0@josef.ifi.unizh.ch>; Mon, 18 Nov 1996 21:00:57 +0100 Original-Received: from romeo.cma.fr by cma.cma.fr, Mon, 18 Nov 96 21:00:47 +0100 PP-warning: Illegal Received field on preceding line Received: by romeo.cma.fr; id AA20143; Mon, 18 Nov 1996 21:00:45 +0100 Message-Id: <9611182000.AA20143@romeo.cma.fr> X-Mailer: exmh version 1.6.7 5/3/96 To: codesign@ifi.unizh.ch Subject: Real-Time workshop Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Date: Mon, 18 Nov 1996 21:00:45 +0100 From: Gerard Berry Status: RO Euro-Par'97 =========== Announcing a Euro-Par'97 Workshop ------------------------------------------------------------------------- Real-Time Systems and Constraints ------------------------------------------------------------------------- Program Committee: ------------------ * G'erard Berry, Ecole des Mines, France, Global Chair * Hand-J"urgen Siegert, TU Munich, Germany, Local Chair * Rajeev Alur, AT&T Bell Laboratories, USA, Vice-Chair * G"unter Hommel, TU Berlin, Germany, Vice-Chair Deadline: --------- 20 January 1997 (paper) 1 February 1997 (electronic) General Description: -------------------- Euro-Par is the annual European conference in Parallel Processing. Like the 1996 conference in Lyon, the 1997 version will consist of a number of highly focussed workshops on all aspects of parallel processing, from theory to practice, from academy to industry. The workshops will present the latest advances in their respective domains. In addition, there will be a number of high-level tutorials of general interest plus a series of invited talks. Calls for papers for 20 workshops are being launched. All accepted papers will appear in the proceedings published by Springer-Verlag in the LNCS Series. Workshop Description: --------------------- Workshop #20: Real-Time Systems and Constraints The workshop is dedicated to the design, implementation, and verification techniques for computerized systems that obey real-time constaints. The subject comprises programming languages for real-time systems, associated compiling or synthesis technology, real-time operating systems and schedulers, mixed hardware/software systems, and verification of real-time constraints. We would like the workshop to span from academia to applications and from scientific approaches to well-engineered real-time systems case studies. Topics of interest include: * reactive and real-time languages * codesign for real-time systems * real-time operating systems * code speed evaluation * real-time static or dynamic scheduling * verification of real-time constaints Further information ------------------- is available at URL http://www.uni-passau.de/europar97/. It includes the list of all workshops. Please send all information requests and comments to europar97@fmi.uni-passau.de. Register today on the Euro-Par'97 mailing list by sending us a mail! See below for additional information. Official Address: ----------------- Euro-Par'97, Universitaet Passau, D-94030 Passau, Germany Phone: (+49) (851) 509-3071; Fax: (+49) (851) 509-3092 E-mail: europar97@fmi.uni-passau.de URL: http://www.uni-passau.de/europar97/ ------------------------------------------------------------------------- ADDITIONAL INFORMATION ---------------------- Submissions are expected to be no longer than 12 pages in the LNCS style (page size 12.2 cm x 19.3 cm, 12 pt Computer Modern font). Style files are on the Web at http://www.springer.de/author/tex/help-tex.html (for TeX click on PLNCS, for LaTeX on LLNCS). Text processors other than TeX or LaTeX may be used, but we strongly suggest that the submissions satisfy the LNCS specifications! Submitted papers must not be simultaneously under review for any other conference, and authors must point out any substantial overlap with their previously published work. Papers will be published in three categories: distinguished papers (12 pages), full papers (8 pages), and short papers (4 pages). Authors should state with their submission whether classification as a short paper would be acceptable. Except in extenuating circumstances, submission should be electronic. ! Electronic submissions are mandatory for all people having ! ! access to standard electronic facilities. ! ELECTRONIC SUBMISSIONS should consist of two e-mails: * the first one containing an ASCII cover page, giving the author's full name, address, phone and fax number, e-mail address, a 100-word abstract and keywords, as well as the workshop number (#20) and the workshop title (Real-Time Systems and Constraints), * the second one with the printable file. Accepted formats are uuencode'd compressed EPSF PostScript files (most preferably generated by dvips). ! Important! We are sorry that we are unable to accommodate ! ! other file formats. If at all possible, please attempt to ! ! preview the document with Ghostview and print it on more ! ! than one brand/model of laser printers. If your program ! ! requests it, assume that the document will be printed on a ! ! 300 DPI standard PostScript Unix Sun laser printer. We will ! ! do our best to get all files printed. If a file cannot be ! ! printed in spite of all our efforts, we will have to reject ! ! the electronic submission. In case of doubt, send us a ! ! (possibly preliminary) paper version of the submission ! ! before the 20 January 1997 paper deadline (one copy is ! ! enough in this case). We will assume that the electronic ! ! version of the submission, if printable, is the final one. ! The files should be mailed to europar97@fmi.uni-passau.de and received at this address before 1 February 1997. PLEASE NOTE THAT THIS IS A FIRM DEADLINE. PAPER SUBMISSIONS are only allowed for people without easy access to standard electronic facilities. The cover page must clearly indicate the name, address, phone and fax numbers and e-mail address of the author(s), and contain a 100-word abstract and keywords. The workshop number (#20) and the workshop title (Real-Time Systems and Constraints) relating to each submitted paper must also be clearly indicated on the cover page. Authors should send six copies of their submission to the official address, postmarked before 20 January 1997. PLEASE NOTE THAT THIS IS A FIRM DEADLINE. Proceedings: ------------ All accepted papers will be published by Springer-Verlag in the Lecture Notes in Computer Science Series. Proceedings will be available at the conference. Important Dates: ---------------- Register on the mailing list: Today! Deadline for paper submissions: 20 January 1997 Deadline for electronic submissions: 1 February 1997 Notification of acceptance: 2 May 1997 Final version due: 10 June 1997 Early registration: 30 June 1997 Euro-Par'97 in Passau: 26-29 August 1997 -- Gerard Berry CMA, Ecole des Mines de Paris, BP 207 06904 Sophia-Antipolis CDX Tel. 93 95 74 68 Fax. 93 95 74 88 From codesign-request@ifi.unizh.ch Tue Nov 19 17:24:55 1996 Return-Path: Received: from stepsun.uni-kl.de by josef.ifi.unizh.ch with SMTP (PP) id <24019-0@josef.ifi.unizh.ch>; Tue, 19 Nov 1996 17:24:39 +0100 Received: from sun.rhrk.uni-kl.de by stepsun.uni-kl.de id aa29890; 19 Nov 96 17:24 MET Received: from aix6.rhrk.uni-kl.de by sun.rhrk.uni-kl.de id aa15378; 19 Nov 96 17:24 MET Received: from [131.246.76.156] by aix6 with smtp (Smail3.1.28.1 #7) id m0vPsy9-0000Y1C; Tue, 19 Nov 96 17:24 CET Message-Id: Date: Tue, 19 Nov 96 17:24 CET From: Reiner Hartenstein Reply-To: Reiner Hartenstein To: codesign@ifi.unizh.ch, ah@aifb.uni-karlsruhe.de Subject: Good Idea Wanted Status: RO in case of ..., PLEASE, EXCUSE FOR MULTIPLE COPIES OF THIS E-MAIL Dear colleague, the goal is, to achieve, that HPC, PP, Supercomputing and similar people come to look at reconfigurable logic etc. and applications (see "Goals and Visions" in the following CfP) - as a remedy to the parallel computing crisis ?. Do you have an idea, who would probably be a fascinating speaker on this? Do you have an idea about topics for an attractive panel to stimulate discussion across boundaries of scenes, questioning current main streams? Of course, also your own submission is welcome for the Reconfigurable Architectures Workshop (RAW'97). Waiting for your kind reply: Best regards Reiner Hartenstein ------------------------------------------------------------------------------ R e c o n f i g u r a b l e A r c h i t e c t u r e s C A L L F O R P A P E R S 4th Reconfigurable Architectures Workshop (RAW-97) April 1, 1997, Geneva, Switzerland to be held in conjunction with 11th International Parallel Processing Symposium (IPPS-97) (Sponsored by IEEE Technical Committee on Parallel Processing) http://cuiwww.unige.ch/~ipps97/ Program Chair: Reiner W. Hartenstein, Kaiserslautern University Workshop Chair: Viktor K. Prasanna, University of Southern California This workshop is the 4th one in a series held at Cancun, Mexico (1994), Santa Barbara, California (1995), and Honolulu, Hawaii (1996). RAW-97 is part of the 11th International Parallel Processing Symposium (IPPS-97), held April 1 - 5, 1997 at University of Geneva, Switzerland. RAW-97 will be held at April 1, the first day of IPPS-97. RAW-97 is one of 14 specialized workshops held first or last day of IPPS-97. See http://xputers.informatik.uni-kl.de/RAW/RAW97.html Goals and Visions of the Workshop The recent decade has witnessed enormous technological advances, a deeper appreciation of the power of the use of reconfigurable technology platforms, and a better understanding of computing in time and in space. The building of reconfigurable systems can only be achieved by building on the experience in different areas, and close interaction between them to identify and solve the remaining problems. The primary objective of this workshop is to provide opportunity for creative interaction between researchers actively involved in the fabrication, design, applications and enabling technologies of reconfigurable architectures. Scope of the Workshop The workshop will feature several sessions of submitted paper presentations and proceedings will be available at the symposium and by public ftp. Authors are invited to submit manuscripts which demonstrate original and on-going research in areas of Reconfigurable architectures, implementations, algorithms and applications. The topics of interest include, but are not limited to: Reconfigurable Systems Reconfiguration Models Implementations Systems Complexity Scalable Programmable Logic Architectures Technology CAD tools Applications Evolvable and Adaptable Systems Reconfigurable Custom Computing Machines Reconfigurable Accelerators and their Applications Applications Problem Solving Paradigms Image Processing Geographic Information Systems Graphics and Animation Algorithms(arithmetic/geometric/graph/numerical/randomised) Industrial applications and experiences Bridging the Gap Software to Hardware Migration for Speed-up Run Time to Compile Time Migration for Speed-up Hardware/Software Co-Design using reconfigurable devices Profiling and Hardware / Software Partitioning New Paradigms and Basic Research Aspects Development Tools and Methods High-level Development Support Reconfiguration from Programming Language Sources Innovative Compilation Techniques Adapting Parallelizing Compilation Techniques for Structural Programming Benchmarks for Reconfigurable Hardware Curricula introducing structural programming in CS curricula introducing reconfigurable architectures and technology platforms in CS&E curricula lab courses integrating structural and procedural programming educational experiences on reconfigurable systems experiences in hardware / software co-education Join the Paradigm Switch! We are witnessing the beginning of a paradigm change. Hardware has become soft. A second world of programming joins the traditional procedural programming: the world of structural programming. In the long term this will revolutionize the entire computing science. The mainly procedurally oriented traditional computing science will end up in a duality of computing in time and computing in space. The crystalization point of this overlap is already here. It is the area of systolic array synthesis, where time and space appear within the same formula, and, which provides first mappings between both worlds. (Systolic arrays stress computing in space, because the locality of an operation in a particular PE is a central concept. In classical parallel computing (except SIMD and similar) locality is not interesting, since processors have addresses.) This is just the beginning. You are encouraged to submit your cool ideas, your hot implementations, and your exciting visions - to accelerate this march to new horizons. Bridging the Gap Until recently the polulations of the R&D scene of parallel computing or high performance computing on one side, and the scenes dealing with reconfigurable hardware platforms have been non-overlapping. But both populations have the same goal: high performance by parallelism. Until recently calls for papers and participants on reconfigurable platforms, systems, and applications attracted only hardware experts. Most of them practice hardware / software co-design: linking structurally programmed accelerator hardware to traditional software running on a procedurally programmed host system. But high performance people, supercomputing people, parallel computing people, etc. went only to their own conferences. Until recently only a few of them had heard anything about FPGAs and other reconfigurable platforms and how to use them for speed-up. The time has come to bridge that gap: we need your help. Program Committee (list not completed): Peter Athanas, Virginia Tech (USA) Klaus Buchenrieder, Siemens Research (D) , Steven Casselman, Virtual Computer Corp. (USA) , Bernard Courtois, Univ. Grenoble (F) , Andre' DeHon, Univ. of California, Berkeley (USA) Hossam Elgindy, Univ. of Newcastle (AUS) , Rolf Ernst, Univ. Braunschweig (D) , Manfred Glesner, TH Darmstadt (D) , John Gray, Xilinx Corp. (UK) , Reiner Hartenstein, Univ. Kaiserslautern (D) Brad Hutchings, Brigham Young University (USA) Rong Lin, State Univ. of New York, Geneseo (USA) Viktor Prasanna, Univ. of Southern California (USA) Michal Servit, Techn. Univ. Prague (CR) , John Villasenor, Univ. of California, Los Angeles (USA) Submitting Papers All papers will be reviewed. Please, send five (5) copies of complete paper (up to 10 single spaced, single sided pages) to: Reiner Hartenstein, Universitaet Kaiserslautern, Bau 12 / 4, Postfach 3049, D - 67653 Kaiserslautern, Germany Electronic submissions (in postscript format) are encouraged and should be sent to hartenst@rhrk.uni-kl.de and: abakus@informatik.uni-kl.de (please, use both, simultaneously) The workshop proceedings will be published by a professional publisher, taking care of ISBN number and Library of Congress catalog number. Important Dates: Manuscripts due January 3, 1997. Notification of review decisions 31 January 1997. Final version due 28 February 1997. For Further Information, please contact any of the workshop co-chairs: Reiner W. Hartenstein Universitaet Kaiserslauten (Germany) E-mail: hartenst@rhrk.uni-kl.de and abakus@informatik.uni-kl.de (please, use both, simultaneously), FAX: +49 631 205 2640 and: +49 7251 14823 (please, use both, simultaneously) Viktor K. Prasanna University of Southern California (USA) E-mail: prasanna@ganges.usc.edu FAX: +1 213 740 4418 For updates of your information also frequently check the web page: http://xputers.informatik.uni-kl.de/RAW/RAW97.html for ASCII version see: http://xputers.informatik.uni-kl.de/RAW/RAW97/call_RAW97.txt _________________________________________________________________ Prof. Dr.-Ing. Reiner W. Hartenstein, Universitaet Kaiserslautern Informatik (CS&E) Bau 12 | phone: +49 631 205 2606, fax: -2640 Postfach 3049 | http://xputers.informatik.uni-kl.de D-67653 Kaiserslautern, Germany | e-mail: hartenst@rhrk.uni-kl.de HOME: Postf.1744, D-76607 Bruchsal,Germany | Fax: +49 7251 14823 ..._/ _/ _/_/_/ _/ _/ _/_/_/ _/_/_/ _/_/_/ _/_/........_/ ..._/_/ _/ _/ _/ _/ _/ _/ _/ _/ _/ ........_/_/ ..._/ _/_/_/ _/ _/ _/ _/_/_/ _/_/_/ _/_/...._/_/_/_/_/ ._/_/ _/ _/ _/ _/ _/ _/ _/ _/......._/_/ _/ _/ _/ _/_/ _/ _/_/_/ _/ _/ _/_/........_/ From codesign-request@ifi.unizh.ch Wed Aug 7 11:40:14 1996 Return-Path: Received: from iddth.it.dtu.dk by josef.ifi.unizh.ch with SMTP (PP) id <24681-0@josef.ifi.unizh.ch>; Wed, 7 Aug 1996 11:40:07 +0200 Received: from anor.it.dtu.dk (anor.it.dtu.dk [130.225.76.92]) by iddth.it.dtu.dk (8.6.9/8.6.4) with SMTP id LAA10021; Wed, 7 Aug 1996 11:39:38 +0200 Received: by anor.it.dtu.dk (4.1/SMI-4.1) id AA22029; Wed, 7 Aug 96 11:24:20 +0200 Date: Wed, 7 Aug 96 11:24:20 +0200 From: jnrg@anor.it.dtu.dk (Jesper N. R. Grode) Message-Id: <9608070924.AA22029@anor.it.dtu.dk> To: jbecker@informatik.uni-kl.de Cc: codesign@ifi.unizh.ch, hartenst@rhrk.uni-kl.de In-Reply-To: <199608070841.KAA20350@irz1.informatik.uni-kl.de> (message from Juergen Becker on Wed, 7 Aug 1996 10:41:29 +0200) Subject: Re: List of HW/SW Codesign approaches Reply-To: jnrg@it.dtu.dk Status: RO X-Status: Hi! I have come across one list of codesign frameworks: http://www.ifi.uio.no/~olavlok/co-design.html Regards, Jesper Grode -- Jesper Nicolai Riis Grode Department of Information Technology | E-mail: jnrg@it.dtu.dk Building 344, room 258 | Phone: +45 45 25 37 54 Technical University of Denmark | Fax: +45 45 88 45 30 DK-2800 Lyngby | WWW: http://www.it.dtu.dk/~jnrg/ DK - Denmark | From codesign-request@ifi.unizh.ch Tue Dec 10 00:34:31 1996 Return-Path: Received: from mailgate.Cadence.COM by josef.ifi.unizh.ch with SMTP (PP) id <01395-0@josef.ifi.unizh.ch>; Tue, 10 Dec 1996 00:34:19 +0100 Received: (from smap@localhost) by mailgate.Cadence.COM (8.6.8/8.6.8) id PAA25662 for ; Mon, 9 Dec 1996 15:33:48 -0800 Received: from bsd10.cadence.com(158.140.90.10) by mailgate.Cadence.COM via smap (V1.0mjr) id sma850174427.025656; Mon Dec 9 15:33:47 1996 Received: from localhost (localhost [127.0.0.1]) by bsd10.Cadence.COM (8.6.8/8.6.8) with SMTP id PAA13551 for ; Mon, 9 Dec 1996 15:33:42 -0800 Message-Id: <199612092333.PAA13551@bsd10.Cadence.COM> X-Authentication-Warning: bsd10.Cadence.COM: Host localhost didn't use HELO protocol To: codesign@ifi.unizh.ch Subject: International Workshop on Logic Synthesis 1997 -- Call for papers Date: Mon, 09 Dec 1996 15:33:39 +0000 From: Luciano Lavagno Status: RO X-Status: - --------------------------------------------------------------------------- 1997 IEEE/ACM International Workshop on Logic Synthesis http://www.ee.princeton.edu/iwls97.html Granlibakken Resort, Lake Tahoe, California May 18-21 , 1997 Call for Participation Contents 1. Synopsis 2. Benchmarks 3. About IWLS 4. About Granlibakken 5. Executive Committee 6. Technical Program Committee 7. Sponsored by... Synopsis Logic Synthesis has traditionally focused on optimization techniques for combinational and sequential circuits through the manipulation of Boolean equations and state machines. IWLS '97, the sixth workshop in this series, seeks presentations both on these topics and on new directions in synthesis-based design methodology. Topics of interest include: Area, timing, power optimization Logic synthesis systems CMOS, ECL, GaAS Optimization Designer Experiences with Synthesis Two-level Logic Optimization Interaction with physical design Multi-level Logic Optimization Incremental Synthesis/ECO Support FSM Optimization Asynchronous Logic Synthesis Sequential Circuit Optimization Formal Verification Retiming and resynthesis Optimization at the RTL Level Technology Mapping Timing Verification FPGA and PLD Synthesis Testing and Synthesis for test Don't-Cares and Boolean Relations Interaction with module generators Symbolic Synthesis Use of synthesis in new applications Synthesis in FPGA-Based Emulation Applications of SAT Authors may submit extended abstracts for their proposed presentation. These must be no less than 1000 words and no more than 2500 words. These abstracts are not intended to be complete papers, but rather should convey the main ideas of the proposed presentation. We encourage submissions in the early stages of research which may highlight important new problems without necessarily providing complete solutions. The abstracts may be submitted by e-mailing self-contained Postscript files to iwls-submit@ee.princeton.edu by February 15, 1997. Acceptance notices will be sent by March 31, 1997. A set of workshop notes will be distributed at the conference. There will be no published proceedings. Benchmarks A benchmark set is being assembled by the CAD Benchmarking Laboratory. To contribute new benchmarks, or to obtain information about the existing suite, please write: benchmarks@cbl.ncsu.edu. About IWLS IWLS '93 and IWLS '95 introduced a number of format changes from previous workshops, which the committee tentatively intends to maintain for IWLS '97. These include an open program with high acceptance rate, heavy use of posters and short talks for presentation, and large amounts of time in the schedule for poster presentations. In addition, IWLS '97 will emphasize open discussions and ongoing research which are not provided by the traditional conference format. About Granlibakken The Granlibakken Conference Center is located in Tahoe City on the west shore of Lake Tahoe, 180 miles east of San Francisco. It boasts 160 rooms, clustered into two- and three-bedroom condominiums. Each bedroom is an attractive hotel room with private bath. Many of the clusters share a kitchen, living room and dining room -- a miniature lobby for private meetings. Organizations sending several people to the workshop may wish to rent entire two- and three-bedroom townhouses. The Granlibakken management has reserved space on Thursday, May 22 for organizations who wish to hold private, one-day workshops immediately preceding IWLS, and have agreed to charge organizations the IWLS conference rate for these meetings. Contact Mary Brown at Granlibakken sales (1-800-552-4494) for details. Granlibakken is within 10 minutes' drive of the West's premier ski resorts: Alpine Meadows and Squaw Valley USA. When California enjoys high snowfall, both areas remain open until Memorial Day. A wealth of hiking trails snake through the area. Weather permitting, Granlibakken's tennis courts and pool will be open for use. The weather in late May is variable; warm, sunny days and cool clear nights are the rule. Getting There Granlibakken is easily reached from either the San Francisco Bay Area or Reno, NV. Take Interstate 80 to Truckee. From there, follow State Route 89 south to Tahoe City. Turn right at the stop light in Tahoe City. After 1/4 mile, turn right on Granlibakken road and proceed to the end. Contacts/Executive Committee General Chair Rick Cadence mcgeer@cadence.com (408) McGeer Berkeley Labs 428-5325 Tech. Program Sharad Princeton (609) Chair Malik University sharad@ee.princeton.edu 258-4625 Benchmark Franc (919) Chair Brglez NCSU brglez@cbl.ncsu.edu 248-1925 Conference Kris Cadence (408) Coordinator Lamanno Berkeley Labs krisl@cadence.com 894-2479 Technical Program Committee Pranav Ashar NEC Michel Berkelaar TU-Eindhoven Robert K. Brayton UC Berkeley Franc Brglez NCSU Giovanni de Micheli Stanford Srinivas Devadas MIT Ewald Detjens Mentor Graphics Antun Domic Cadence Masahiro Fujita Fujitsu Laboratories of America Wolfgang Kunz University of Potsdam Luciano Lavagno Politecnico di Torino/Cadence Berkeley Labs Ken McElvain Synplicity Rick McGeer Cadence Berkeley Labs Sharad Malik (chair) Princeton University Shin-ichi Minato NTT Massoud Pedram USC Richard Rudell Synopsys Tsutomu Sasao Kysushu Institute of Technology Gabriele Saucier INPG Ellen Sentovich Cadence Berkeley Labs Fabio Somenzi University of Colorado Leon Stok IBM TJ Watson Research Center Sponsor Sponsored by the IEEE Computer Society, Technical Committee on VLSI. In co-operation sponsoship by ACM/SIGDA is being sought. - ------------------------------------------------------------------------- Sharad Malik Phone: 609-258-4625 Associate Professor Fax: 609-258-3745 Princeton University E-Mail: malik@Princeton.EDU Princeton, NJ 08544 ------- End of Forwarded Message